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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" Subject: [PATCH net-next v1 1/1] octeon_ep: reset firmware ready status Date: Thu, 20 Nov 2025 11:23:44 +0000 Message-ID: <20251120112345.649021-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251120112345.649021-1-vimleshk@marvell.com> References: <20251120112345.649021-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: kUkmHHCYCyr1ZlSjl_MkYP0LBlew2knk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIwMDA3MSBTYWx0ZWRfX+qzxy0/xMiD1 QPFiUSkfC4RmczDg8A9qwpDfj+DncoLho4cAtHsqc24goGAH2qYInpyEOmiFhiCKz/Cmx+hXV1E vUDZijSICkPkNfCaOOhHres0WQ6NsX/8hpxXw0/a0tc9JUnTrMgvWERI7g3GN54J6U1EBJKE3dR FZaTNC+K5GtILzqNIRrOUjzDZiq1F3msDFj1DfVAeZmmj9vUusrMh4kVbBYXvZm98JxDPF7hegH Ha9ocGwnLC0Clf0OuMwMiWJqvrXzBTvIYBPZolFFyjtHHZBeNutbixIiCpInOmgJ38AYzPqBumz BkaaS6KBRFxaBy901ILC/l550J0yIp47sRJUPQ3XXOcTPFfsoGsLwVV0VmB1NvF4vvlUL5UCzAr pCaVKux/lB35z5Nja5cFpDoOGmA6+w== X-Authority-Analysis: v=2.4 cv=IuYTsb/g c=1 sm=1 tr=0 ts=691efa4e cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=v39aYAeCPeV2KakbcL8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: kUkmHHCYCyr1ZlSjl_MkYP0LBlew2knk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-20_04,2025-11-20_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Add support to reset firmware ready status when the driver is removed(either in unload or unbind) Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- .../marvell/octeon_ep/octep_cn9k_pf.c | 22 +++++++++++++++++++ .../marvell/octeon_ep/octep_cnxk_pf.c | 2 +- .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 11 ++++++++++ .../marvell/octeon_ep/octep_regs_cnxk_pf.h | 1 + 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..6f926e82c17c 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -637,6 +637,17 @@ static int octep_soft_reset_cn93_pf(struct octep_devic= e *oct) =20 octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF); =20 + /* Firmware status CSR is supposed to be cleared by + * core domain reset, but due to a hw bug, it is not. + * Set it to RUNNING right before reset so that it is not + * left in READY (1) state after a reset. This is required + * in addition to the early setting to handle the case where + * the OcteonTX is unexpectedly reset, reboots, and then + * the module is removed. + */ + OCTEP_PCI_WIN_WRITE(oct, CN9K_PEMX_PFX_CSX_PFCFGX(0, 0, CN9K_PCIEEP_VSECS= T_CTL), + FW_STATUS_DOWNING); + /* Set core domain reset bit */ OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1); /* Wait for 100ms as Octeon resets. */ @@ -894,4 +905,15 @@ void octep_device_setup_cn93_pf(struct octep_device *o= ct) =20 octep_init_config_cn93_pf(oct); octep_configure_ring_mapping_cn93_pf(oct); + + if (oct->chip_id =3D=3D OCTEP_PCI_DEVICE_ID_CN98_PF) + return; + + /* Firmware status CSR is supposed to be cleared by + * core domain reset, but due to IPBUPEM-38842, it is not. + * Set it to RUNNING early in boot, so that unexpected resets + * leave it in a state that is not READY (1). + */ + OCTEP_PCI_WIN_WRITE(oct, CN9K_PEMX_PFX_CSX_PFCFGX(0, 0, CN9K_PCIEEP_VSECS= T_CTL), + FW_STATUS_RUNNING); } diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..e07264b3dbf8 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -660,7 +660,7 @@ static int octep_soft_reset_cnxk_pf(struct octep_device= *oct) * the module is removed. */ OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECS= T_CTL), - FW_STATUS_RUNNING); + FW_STATUS_DOWNING); =20 /* Set chip domain reset bit */ OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h index ca473502d7a0..d7fa5adbce98 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h @@ -383,6 +383,17 @@ /* bit 1 for firmware heartbeat interrupt */ #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) =20 +#define FW_STATUS_DOWNING 0ULL +#define FW_STATUS_RUNNING 2ULL +#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) ((0x8e0000008000 | = (uint64_t)(pem) << 36 \ + | (pf) << 18 \ + | (((offset) >> 16) & 1) << 16 \ + | ((offset) >> 3) << 3) \ + + ((((offset) >> 2) & 1) << 2)) + +/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */ +#define CN9K_PCIEEP_VSECST_CTL 0x4D0 + #define CN93_PEM_BAR4_INDEX 7 #define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR= 4_INDEX_SIZE) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h index e637d7c8224d..a6b6c9f356de 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h @@ -396,6 +396,7 @@ #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0) /* bit 1 for firmware heartbeat interrupt */ #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) +#define FW_STATUS_DOWNING 0ULL #define FW_STATUS_RUNNING 2ULL #define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) ({ typeof(offset) _= off =3D (offset); \ ((0x8e0000008000 | \ --=20 2.34.1