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[114.145.28.12]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-29b5b1387e3sm22381035ad.24.2025.11.20.02.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 02:39:18 -0800 (PST) From: Daniel Palmer To: geert@linux-m68k.org, schmitzmic@gmail.com, gerg@kernel.org, linux-m68k@lists.linux-m68k.org Cc: linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH v2 2/2] m68k: Implement kernel memory protection Date: Thu, 20 Nov 2025 19:38:54 +0900 Message-ID: <20251120103854.1630306-3-daniel@thingy.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251120103854.1630306-1-daniel@thingy.jp> References: <20251120103854.1630306-1-daniel@thingy.jp> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Every time I boot linux on my various m68k machines I see "This architecture does not have kernel memory protection." I wondered why this was as some of my machines even have one of those fancy MMU doodads. I worked out it was because we don't have CONFIG_ARCH_HAS_STRICT_KERNEL_RWX, found kernel_set_cachemode() seemed like it had the code for setting some extra flags for kernel pages and turned that into something that sets write protect for kernel pages. So now we can make CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=3Dy and provide mark_rodata_ro() to mark the kernel text and rodata as write protected. The test enabled by CONFIG_DEBUG_RODATA_TEST=3Dy says this is working. Tested on Amiga 4000 (060), virt (040), MVME147 (030) Signed-off-by: Daniel Palmer --- arch/m68k/Kconfig | 1 + arch/m68k/mm/init.c | 73 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 11835eb59d94..2137fd19ffbd 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -8,6 +8,7 @@ config M68K select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DMA_PREP_COHERENT if M68K_NONCOHERENT_DMA && !COLDFIRE + select ARCH_HAS_STRICT_KERNEL_RWX if MMU select ARCH_HAS_SYNC_DMA_FOR_DEVICE if M68K_NONCOHERENT_DMA select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS select ARCH_MIGHT_HAVE_PC_PARPORT if ISA diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c index 488411af1b3f..f11597751741 100644 --- a/arch/m68k/mm/init.c +++ b/arch/m68k/mm/init.c @@ -123,3 +123,76 @@ void __init mem_init(void) { init_pointer_tables(); } + +#ifdef CONFIG_MMU +/* + * Based on (basically copy/pasted) kernel_set_cachemode() because + * presumably that is correct and covers the required differences. + */ +static void __mark_ro_data(unsigned long virtaddr, ssize_t size) +{ + pgd_t *pgd_dir; + p4d_t *p4d_dir; + pud_t *pud_dir; + pmd_t *pmd_dir; + pte_t *pte_dir; + + while (size > 0) { + pgd_dir =3D pgd_offset_k(virtaddr); + p4d_dir =3D p4d_offset(pgd_dir, virtaddr); + pud_dir =3D pud_offset(p4d_dir, virtaddr); + if (pud_bad(*pud_dir)) { + pud_clear(pud_dir); + return; + } + pmd_dir =3D pmd_offset(pud_dir, virtaddr); + +#if CONFIG_PGTABLE_LEVELS =3D=3D 3 + if (CPU_IS_020_OR_030) { + unsigned long pmd =3D pmd_val(*pmd_dir); + + if ((pmd & _DESCTYPE_MASK) =3D=3D _PAGE_PRESENT) { + /* We cannot write protect part of an early term */ + if (WARN_ON(size < PMD_SIZE)) + break; + + *pmd_dir =3D __pmd(pmd | _PAGE_RONLY); + virtaddr +=3D PMD_SIZE; + size -=3D PMD_SIZE; + continue; + } + } +#endif + + if (pmd_bad(*pmd_dir)) { + pmd_clear(pmd_dir); + return; + } + + /* We cannot write protect part of a page */ + if (WARN_ON(size < PAGE_SIZE)) + break; + + pte_dir =3D pte_offset_kernel(pmd_dir, virtaddr); + + set_pte(pte_dir, pte_wrprotect(*pte_dir)); + virtaddr +=3D PAGE_SIZE; + size -=3D PAGE_SIZE; + } +} + +void mark_rodata_ro(void) +{ + unsigned long start; + unsigned long end; + + /* kernel text + 1 page , kernel_pg_dir lives in the first page, so skip = that */ + start =3D (unsigned long) _stext + PAGE_SIZE; + end =3D (unsigned long) __end_rodata; + + pr_info("Write protecting kernel text and read-only data: 0x%lx - 0x%lx\n= ", start, end); + __mark_ro_data(start, end - start); + + flush_tlb_all(); +} +#endif --=20 2.51.0