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Wysocki" , Viresh Kumar , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Emil Renner Berthing , Heinrich Schuchardt , E Shattow Cc: Hal Feng , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Date: Thu, 20 Nov 2025 16:29:44 +0800 Message-ID: <20251120082946.109378-4-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20251120082946.109378-1-hal.feng@starfivetech.com> References: <20251120082946.109378-1-hal.feng@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SH0PR01CA0008.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::20) To ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:7::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ2PR01MB1307:EE_|ZQ2PR01MB1275:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c860237-c65e-4908-6383-08de280efdd8 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|52116014|366016|41320700013|38350700014|921020; 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charset="utf-8" Add common board dtsi for use by VisionFive 2 Lite variants. Signed-off-by: Hal Feng Acked-by: Emil Renner Berthing --- .../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++ 1 file changed, 691 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfiv= e-2-lite.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lit= e.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dt= si new file mode 100644 index 000000000000..aa375c4a3fa3 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 StarFive Technology Co., Ltd. + * Copyright (C) 2025 Hal Feng + */ + +/dts-v1/; +#include "jh7110.dtsi" +#include "jh7110-pinfunc.h" +#include +#include +#include + +/ { + aliases { + ethernet0 =3D &gmac0; + i2c0 =3D &i2c0; + i2c2 =3D &i2c2; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0x1 0x0>; + bootph-pre-ram; + }; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&sysgpio 35 GPIO_ACTIVE_HIGH>; + priority =3D <224>; + }; + + leds { + compatible =3D "gpio-leds"; + + led_status_power: led-0 { + gpios =3D <&aongpio 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&cpu_opp { + /delete-node/ opp-375000000; + /delete-node/ opp-500000000; + /delete-node/ opp-750000000; + /delete-node/ opp-1500000000; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + opp-microvolt =3D <800000>; + }; + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + opp-microvolt =3D <800000>; + }; + opp-625000000 { + opp-hz =3D /bits/ 64 <625000000>; + opp-microvolt =3D <800000>; + }; + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-microvolt =3D <1000000>; + }; +}; + +&cpus { + timebase-frequency =3D <4000000>; +}; + +&dvp_clk { + clock-frequency =3D <74250000>; +}; + +&gmac0_rgmii_rxin { + clock-frequency =3D <125000000>; +}; + +&gmac0_rmii_refin { + clock-frequency =3D <50000000>; +}; + +&gmac1_rgmii_rxin { + clock-frequency =3D <125000000>; +}; + +&gmac1_rmii_refin { + clock-frequency =3D <50000000>; +}; + +&hdmitx0_pixelclk { + clock-frequency =3D <297000000>; +}; + +&i2srx_bclk_ext { + clock-frequency =3D <12288000>; +}; + +&i2srx_lrck_ext { + clock-frequency =3D <192000>; +}; + +&i2stx_bclk_ext { + clock-frequency =3D <12288000>; +}; + +&i2stx_lrck_ext { + clock-frequency =3D <192000>; +}; + +&mclk_ext { + clock-frequency =3D <12288000>; +}; + +&osc { + clock-frequency =3D <24000000>; +}; + +&rtc_osc { + clock-frequency =3D <32768>; +}; + +&tdm_ext { + clock-frequency =3D <49152000>; +}; + +&camss { + assigned-clocks =3D <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; + assigned-clock-rates =3D <49500000>, <198000000>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + camss_from_csi2rx: endpoint { + remote-endpoint =3D <&csi2rx_to_camss>; + }; + }; + }; +}; + +&csi2rx { + assigned-clocks =3D <&ispcrg JH7110_ISPCLK_VIN_SYS>; + assigned-clock-rates =3D <297000000>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + /* remote MIPI sensor endpoint */ + }; + + port@1 { + reg =3D <1>; + + csi2rx_to_camss: endpoint { + remote-endpoint =3D <&camss_from_csi2rx>; + }; + }; + }; +}; + +&gmac0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + starfive,tx-use-rgmii-clk; + assigned-clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents =3D <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp =3D <3970>; + motorcomm,rx-data-drv-microamp =3D <2910>; + rx-internal-delay-ps =3D <1500>; + tx-internal-delay-ps =3D <1500>; + }; + }; +}; + +&i2c0 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "okay"; +}; + +&i2c5 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "okay"; + + axp15060: pmic@36 { + compatible =3D "x-powers,axp15060"; + reg =3D <0x36>; + interrupt-controller; + #interrupt-cells =3D <1>; + + regulators { + vcc_3v3: dcdc1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3"; + }; + + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1540000>; + regulator-name =3D "vdd_cpu"; + }; + + emmc_vdd: aldo4 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "emmc_vdd"; + }; + }; + }; + + eeprom@50 { + compatible =3D "atmel,24c04"; + reg =3D <0x50>; + bootph-pre-ram; + pagesize =3D <16>; + }; +}; + +&i2c6 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + status =3D "okay"; +}; + +&mmc0 { + max-frequency =3D <100000000>; + assigned-clocks =3D <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates =3D <50000000>; + bus-width =3D <8>; + bootph-pre-ram; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "okay"; +}; + +&mmc1 { + max-frequency =3D <50000000>; + assigned-clocks =3D <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates =3D <50000000>; + bus-width =3D <4>; + bootph-pre-ram; + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + status =3D "okay"; +}; + +&pcie1 { + enable-gpios =3D <&sysgpio 27 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys =3D <&pciephy1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_pins>; + status =3D "okay"; +}; + +&pwm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; + +&qspi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + nor_flash: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + bootph-pre-ram; + cdns,read-delay =3D <2>; + spi-max-frequency =3D <100000000>; + cdns,tshsl-ns =3D <1>; + cdns,tsd2d-ns =3D <1>; + cdns,tchsh-ns =3D <1>; + cdns,tslch-ns =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + spl@0 { + reg =3D <0x0 0xf0000>; + }; + uboot-env@f0000 { + reg =3D <0xf0000 0x10000>; + }; + uboot@100000 { + reg =3D <0x100000 0xf00000>; + }; + }; + }; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "okay"; +}; + +&syscrg { + assigned-clocks =3D <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_CPU_CORE>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>; + assigned-clock-parents =3D <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates =3D <0>, <0>, <0>, <0>, <500000000>, <1250000000>; +}; + +&sysgpio { + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux =3D , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c2_pins: i2c2-0 { + i2c-pins { + pinmux =3D , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c5_pins: i2c5-0 { + bootph-pre-ram; + + i2c-pins { + pinmux =3D , + ; + bias-disable; /* external pull-up */ + bootph-pre-ram; + input-enable; + input-schmitt-enable; + }; + }; + + i2c6_pins: i2c6-0 { + i2c-pins { + pinmux =3D , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + mmc0_pins: mmc0-0 { + mmc-pins { + pinmux =3D , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength =3D <12>; + input-enable; + }; + }; + + mmc1_pins: mmc1-0 { + clk-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mmc-pins { + pinmux =3D , + , + , + , + ; + bias-pull-up; + drive-strength =3D <12>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux =3D ; + bias-pull-down; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + wake-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + pwm_pins: pwm-0 { + pwm-pins { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + spi0_pins: spi0-0 { + mosi-pins { + pinmux =3D ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux =3D ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux =3D ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux =3D ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + + uart0_pins: uart0-0 { + tx-pins { + pinmux =3D ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pinmux =3D ; + bias-disable; /* external pull-up */ + drive-strength =3D <2>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + + uart1_pins: uart1-0 { + tx-pins { + pinmux =3D ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <2>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + + cts-pins { + pinmux =3D ; + input-enable; + }; + + rts-pins { + pinmux =3D ; + input-enable; + }; + }; + + usb0_pins: usb0-0 { + power-pins { + pinmux =3D ; + input-disable; + }; + + switch-pins { + pinmux =3D ; + input-disable; + }; + }; +}; + +&uart0 { + bootph-pre-ram; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "okay"; +}; + +&usb0 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb0_pins>; + status =3D "okay"; +}; + +&usb_cdns3 { + phys =3D <&usbphy0>, <&pciephy0>; + phy-names =3D "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; + +&U74_1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply =3D <&vdd_cpu>; +}; --=20 2.43.2