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Thu, 20 Nov 2025 00:26:20 -0800 (PST) From: Francesco Lavra To: Lorenzo Bianconi , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/9] iio: imu: st_lsm6dsx: move wakeup event enable mask to event_src Date: Thu, 20 Nov 2025 09:26:09 +0100 Message-Id: <20251120082615.3263892-4-flavra@baylibre.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251120082615.3263892-1-flavra@baylibre.com> References: <20251120082615.3263892-1-flavra@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7525; i=flavra@baylibre.com; h=from:subject; bh=W7dRYFBp5zbk0lTntGV+cJ+DU2JAhLbFX8VsL4eBjeo=; b=owEB7QES/pANAwAKAe3xO3POlDZfAcsmYgBpHtB5qOw5JEdmXERyjwBdrBVvmU1TaXh0S5YdX RcIpIuUQXGJAbMEAAEKAB0WIQSGV4VPlTvcox7DFObt8TtzzpQ2XwUCaR7QeQAKCRDt8TtzzpQ2 XyhZDACdPs2v2eVq6BOYprhQVzlCtevYM7Gs9XfUjl2+ZblLi8C1x6kvPqAjeFXQq8qChBHuAD7 1K2+yClFHflK/kbjDLPRMvACqy5HoV1rawX8wBTSHL4dEpcEv8mJamoE2t9V3Hv1/27KG/SQp7p lNmlDLeNOe/jXkVRPIzPlAU8wVL6Qlx3PibwwpGk8A7EJxhHd4tqz6n4NAPMh46iGYqg76X7yaO lB5GUtdrSIcPcUKu5G1fT/eIuEJgPd+Tf/HhQSA1BPLOK8hqyK7QB6YFeqYHXDehHb2ZIfXTGy5 oB7SMAQaUpRpx7rm1BD3WZx7eklSlPfJYo+js5fQqp1rLxrPp56M71W7MZdX7nby/u/uI22XHaS nzz3rLUyREFDlUPQc9KodKdej0gDgzKIKJL/cERJtcZ8Lh10/k+owcuo47zhwqdIGejCqfjsCOl NJnHiKUi2aaJBGIL5/HmsdaBobCFJK1jFwdvpzuB5HgkUnu3+tmIjgvrD8kZdb3T6nB2U= X-Developer-Key: i=flavra@baylibre.com; a=openpgp; fpr=8657854F953BDCA31EC314E6EDF13B73CE94365F Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mask value being assigned to the irq1_func and irq2_func fields of the irq_config struct is specific to a single event source (i.e. the wakeup event), and as such it should be separate from the definition of the interrupt function registers, which cover multiple event sources. In preparation for adding support for more event types, change the irq1_func and irq2_func type from an {address, mask} pair to an address, and move the mask value to a new field of struct st_lsm6dsx_event_src. No functional changes. Signed-off-by: Francesco Lavra Acked-by: Lorenzo Bianconi --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 7 +- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 81 +++++++------------- 2 files changed, 31 insertions(+), 57 deletions(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_l= sm6dsx/st_lsm6dsx.h index 4c3ff1cc0097..bbb967b2754b 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -249,6 +249,7 @@ enum st_lsm6dsx_event_id { =20 struct st_lsm6dsx_event_src { struct st_lsm6dsx_reg value; + u8 enable_mask; u8 status_reg; u8 status_mask; u8 status_x_mask; @@ -344,8 +345,8 @@ struct st_lsm6dsx_settings { struct { struct st_lsm6dsx_reg irq1; struct st_lsm6dsx_reg irq2; - struct st_lsm6dsx_reg irq1_func; - struct st_lsm6dsx_reg irq2_func; + u8 irq1_func; + u8 irq2_func; struct st_lsm6dsx_reg lir; struct st_lsm6dsx_reg clear_on_read; struct st_lsm6dsx_reg hla; @@ -444,7 +445,7 @@ struct st_lsm6dsx_hw { u8 ts_sip; u8 sip; =20 - const struct st_lsm6dsx_reg *irq_routing; + u8 irq_routing; u8 event_threshold; u8 enable_event; =20 diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu= /st_lsm6dsx/st_lsm6dsx_core.c index a71174e75f44..ce5f9213d476 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -328,14 +328,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -394,6 +388,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -498,14 +493,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -564,6 +553,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -698,14 +688,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -805,6 +789,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -951,14 +936,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -1046,6 +1025,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1168,14 +1148,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -1231,6 +1205,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1347,14 +1322,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x03, .mask =3D BIT(4), @@ -1441,6 +1410,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x45, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1899,10 +1869,12 @@ static int st_lsm6dsx_write_raw(struct iio_dev *iio= _dev, static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state) { const struct st_lsm6dsx_reg *reg; + const struct st_lsm6dsx_event_src *src; + u8 enable_mask; unsigned int data; int err; =20 - if (!hw->settings->irq_config.irq1_func.addr) + if (!hw->irq_routing) return -ENOTSUPP; =20 reg =3D &hw->settings->event_settings.enable_reg; @@ -1915,9 +1887,10 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_= hw *hw, bool state) } =20 /* Enable wakeup interrupt */ - data =3D ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); - return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, - hw->irq_routing->mask, data); + src =3D &hw->settings->event_settings.sources[ST_LSM6DSX_EVENT_WAKEUP]; + enable_mask =3D src->enable_mask; + data =3D ST_LSM6DSX_SHIFT_VAL(state, enable_mask); + return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing, enable_mask, da= ta); } =20 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, @@ -2171,11 +2144,11 @@ st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, =20 switch (drdy_pin) { case 1: - hw->irq_routing =3D &hw->settings->irq_config.irq1_func; + hw->irq_routing =3D hw->settings->irq_config.irq1_func; *drdy_reg =3D &hw->settings->irq_config.irq1; break; case 2: - hw->irq_routing =3D &hw->settings->irq_config.irq2_func; + hw->irq_routing =3D hw->settings->irq_config.irq2_func; *drdy_reg =3D &hw->settings->irq_config.irq2; break; default: --=20 2.39.5