From nobody Tue Dec 2 02:31:39 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04EB3310782; Thu, 20 Nov 2025 08:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763626852; cv=none; b=O+VGRdWmW92WTCKAL0DCM5EMf0d0QwXXPmJBwrvJ2iYXuZdrtz6EcrZr84UHCXOFXxR5WbK6exwDfIBpJvsOXGpb6Di0Y9Cqwn56bXIpMlRm96/NRKeZPoa1cFldFcoYuwjnlMSpuDJ4C9MUkyOeB55A69ALc/mWkLDCTfzGXK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763626852; c=relaxed/simple; bh=R+xgwoG9asN8GLQwfxp9q9Eec4Ut9e977JrOBsFN9cE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=T9PEnoUj+7CDTAqArVsWqJ4JSJeQpMtnmYA2ZgpHa/SVC8mT1LIsukBTRaMYNZQ8oJaAd+tCEdYXpFSzahR5lvb1J1WGRz8WuyYz8rVC+wi13AM+IfNaavZdSqvylwL31bxyMe66HWwOxG5VqHdD6uL7Iyz7EDHZGbI2zuOhdGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=WBYvQv7W; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="WBYvQv7W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=LNGio9bXqtWMt7x AAR1rI4df9MoWFeptJriU6YAyJe0=; b=WBYvQv7Wq3MrpXRwXGoJj0cmL0bMNvA 6OROHVdF+4T/a85Jd3wjmjDOhdt4a3CqprAYnOZh1gE8yVkaXS+Gk8L02Q+DcLZN YBFNnl1fjc3EFRgVd2Ss140VEt92fY3ZsvCHdUUL0uhfsBuRfUk7h6FYrNqAtzHJ 0eWasnQ8zJQQ= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wA3BPAwzx5p45f2BA--.17S9; Thu, 20 Nov 2025 16:20:13 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/8] hwmon: (ina3221) Support write/read functions for 'power' attribute Date: Thu, 20 Nov 2025 03:19:20 -0500 Message-Id: <20251120081921.39412-8-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251120081921.39412-1-wenliang202407@163.com> References: <20251120081921.39412-1-wenliang202407@163.com> X-CM-TRANSID: _____wA3BPAwzx5p45f2BA--.17S9 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFy3tr48WFWxZr1DKrykXwb_yoWrWF4xp3 y0kFWrtr4jq3Wfuws3KFs8Gw1Yqr4xX3y2yr9Fk3sava1UZrn0gryrt3Wqya4UCry3Xr47 tayxAryru3ZrKrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUWRR_UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwB3kuGkezz14EAAA3s Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 adds power attributes to report power data and implements corresponding read/write functions for this purpose. This includes reading power values, reading alert thresholds, reading alert trigger status, and writing alert thresholds. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 79 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index eddf8f83ef30..af6d9ca5ae28 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -92,6 +92,9 @@ enum ina3221_fields { /* Alert Flags: SF is the summation-alert flag */ F_SF, F_CF3, F_CF2, F_CF1, =20 + /* Alert Flags: AFF is the alert function flag */ + F_AFF3, F_AFF2, F_AFF1, + /* sentinel */ F_MAX_FIELDS }; @@ -107,6 +110,10 @@ static const struct reg_field ina3221_reg_fields[] =3D= { [F_CF3] =3D REG_FIELD(INA3221_MASK_ENABLE, 7, 7), [F_CF2] =3D REG_FIELD(INA3221_MASK_ENABLE, 8, 8), [F_CF1] =3D REG_FIELD(INA3221_MASK_ENABLE, 9, 9), + + [F_AFF3] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 1, 1), + [F_AFF2] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 2, 2), + [F_AFF1] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 3, 3), }; =20 enum ina3221_channels { @@ -512,6 +519,60 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static const u8 ina3221_power_reg[][INA3221_NUM_CHANNELS] =3D { + [hwmon_power_input] =3D { SQ52210_POWER1, SQ52210_POWER2, SQ52210_POWER3 = }, + [hwmon_power_crit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3 }, + [hwmon_power_crit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3 }, +}; + +static int ina3221_read_power(struct device *dev, u32 attr, int channel, l= ong *val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + u8 reg =3D ina3221_power_reg[attr][channel]; + int regval, ret; + + switch (attr) { + case hwmon_power_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) { + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret =3D ina3221_wait_for_data(ina); + if (ret) + return ret; + } + + fallthrough; + case hwmon_power_crit: + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return power in mW */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->power_lsb_uW, 1000); + return 0; + case hwmon_power_crit_alarm: + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; + default: + return -EOPNOTSUPP; + } +} + static int sq52210_alert_limit_write(struct ina3221_data *ina, enum sq52210_alert_types type, int channel, long val) { @@ -731,6 +792,18 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_power_crit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_POL, channel, val); + default: + return 0; + } +} + static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -747,6 +820,9 @@ static int ina3221_read(struct device *dev, enum hwmon_= sensor_types type, case hwmon_curr: ret =3D ina3221_read_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_read_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; @@ -770,6 +846,9 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_write_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; --=20 2.17.1