From nobody Tue Dec 2 02:31:39 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71F5530BF4B; Thu, 20 Nov 2025 08:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763626848; cv=none; b=S6fPEW4pEe6jjYDMZ1ZT2gXrtZcubuw0Aeus/gyNxyKSS+BaU0U47Qg/YwxXbVWdgdw+lRX/BDB6jTF9V4NUb2E0ct7PyCTcKMWEdqY0vkDfLxKjnsWFa83qrjO2bmJrJZXSay0dMKT4aS3Xt0q4yFnKJ/g5LOcioYXHSirlD3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763626848; c=relaxed/simple; bh=arwpYGJUIjxXuKPgmtuSCwsJh7/64iVLmuFSATrZch4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=u9Fl62o4B4V1SQQI0f76DDJGptYt7BcO83grSQ1MfH5uy10UfMBcS9iX1vutv0LaktXMO+wdBpikTCqzidBDqbLJlfGJGrv0c3KTEayf/EjyEyQ6JiyPRwdhwdRrOsPSlLc+NJofmuiggxmnLvY3HR+GDh0YCcmd/s6lQqdUSnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=pw1RIh2t; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="pw1RIh2t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=68YJNMeAAH/pTY6 CI+vKV/d3ILppncB+4UrqEUXZkB0=; b=pw1RIh2ty32leTzBoS7cWk5U/7Yjosg w7CNDFZpBd5EjwMhxZEGgq/d9edO9+jOSZu9zMMXU5pBGgVF8L5PQPfCV0T1raVn 3VIndwZBvnlfeBR44iDB5WN1M+uaH/S+hMK3kvH0w5CqxqiOWMrWdP8OJ4s/YFXz Ng4T3SSvDRwE= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wA3BPAwzx5p45f2BA--.17S6; Thu, 20 Nov 2025 16:20:08 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/8] hwmon: (ina3221) Support alert configuration Date: Thu, 20 Nov 2025 03:19:17 -0500 Message-Id: <20251120081921.39412-5-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251120081921.39412-1-wenliang202407@163.com> References: <20251120081921.39412-1-wenliang202407@163.com> X-CM-TRANSID: _____wA3BPAwzx5p45f2BA--.17S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7Zr4ftFy7Wr13ur17Xw47Arb_yoW8KFyfpF 43Ka4rtw12qF4Sgws2kan5KFyFy34xWFW7trnrW34FqFsrGryjvrn5GFyDtFyYvFn5ZFyI q3y7tr4jkanFyaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JjaKZJUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwBjjt2kezzh3PAAA3H Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add alert configuration during chip initialization. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index b5fa984a5a25..5fdcffe4738e 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -65,6 +65,8 @@ =20 #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 +#define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) + #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 #define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ @@ -123,6 +125,7 @@ struct ina3221_input { enum ina3221_ids { ina3221, sq52210 }; =20 struct ina3221_config { + bool has_alerts; /* chip supports alerts and limits */ bool has_current; /* chip has internal current reg */ bool has_power; /* chip has internal power reg */ int calibration_value; /* calculate current_lsb */ @@ -140,6 +143,7 @@ struct ina3221_config { * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @alert_type_select: Used to store the alert trigger type * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode @@ -155,6 +159,7 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + u32 alert_type_select; long current_lsb_uA; long power_lsb_uW; =20 @@ -163,10 +168,12 @@ struct ina3221_data { =20 static const struct ina3221_config ina3221_config[] =3D { [ina3221] =3D { + .has_alerts =3D false, .has_current =3D false, .has_power =3D false, }, [sq52210] =3D { + .has_alerts =3D true, .has_current =3D true, .has_power =3D true, /* @@ -1096,6 +1103,17 @@ static int ina3221_resume(struct device *dev) } } =20 + /* Restore alert config register value to hardware */ + if (ina->config->has_alerts) { + ret =3D regmap_update_bits(ina->regmap, SQ52210_ALERT_CONFIG, + SQ52210_ALERT_CONFIG_MASK, + ina->alert_type_select); + if (ret) { + dev_err(dev, "Unable to select alert type\n"); + return ret; + } + } + return 0; } =20 --=20 2.17.1