From nobody Tue Dec 2 02:06:40 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3A384301014; Thu, 20 Nov 2025 06:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621905; cv=none; b=E2a/ozUJwtRodQozH8SECzMJpCe3xtJfBUYCZxwxTu0n26eg9wfp3QrwCjG8iCC0pxnoniJT1FnN1RlucXms/IbTfVWRTJM7L4sAb3x+CBoivCJsfxIxpVPTp3LAFSMPKBuTVWdqG0NO50Gd70JDnM6AIK1mBsQw+2ONkFeb288= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621905; c=relaxed/simple; bh=/eL7qO9Bg4rxngtC4qoLPKMphY8SvbMqkKlEZehmPKM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bH+Kt7sfX913ZX9n7UbB3rJ4o4QchwNGvcAyPPKI7/X6MByO8EkKcXUjecmPOhRae3Xm6CvWq0oew+b0eCE6ooRyo5GGMVAMVDv8CMNegxHv5MdCH4jPbdnNgyEeRQZ2FWM9MgGjPHQAf0T8SiUtIzracFqXYjJDaaYtH2Idpks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cxbb8EvB5p9_4lAA--.15298S3; Thu, 20 Nov 2025 14:58:12 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S3; Thu, 20 Nov 2025 14:58:07 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Tianrui Zhao , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: [PATCH v3 1/6] KVM: LoongArch: selftests: Add system registers save and restore on exception Date: Thu, 20 Nov 2025 14:57:53 +0800 Message-Id: <20251120065758.3064368-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When system returns from exception with ertn instruction, PC comes from LOONGARCH_CSR_ERA, and CSR_CRMD comes LOONGARCH_CSR_PRMD. Here save CSR register CSR_ERA and CSR_PRMD in stack, and restore them from stack. So it can be modified by exception handler in future. Signed-off-by: Bibo Mao --- tools/testing/selftests/kvm/include/loongarch/processor.h | 5 ++++- tools/testing/selftests/kvm/lib/loongarch/exception.S | 6 ++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/loongarch/processor.h b/to= ols/testing/selftests/kvm/include/loongarch/processor.h index 6427a3275e6a..374caddfb0db 100644 --- a/tools/testing/selftests/kvm/include/loongarch/processor.h +++ b/tools/testing/selftests/kvm/include/loongarch/processor.h @@ -124,18 +124,21 @@ struct ex_regs { unsigned long pc; unsigned long estat; unsigned long badv; + unsigned long prmd; }; =20 #define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc) #define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat) #define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv) +#define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd) #define EXREGS_SIZE sizeof(struct ex_regs) =20 #else #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8) #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8) #define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8) -#define EXREGS_SIZE ((EXREGS_GPRS + 3) * 8) +#define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8) +#define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8) #endif =20 #endif /* SELFTEST_KVM_PROCESSOR_H */ diff --git a/tools/testing/selftests/kvm/lib/loongarch/exception.S b/tools/= testing/selftests/kvm/lib/loongarch/exception.S index 88bfa505c6f5..3f1e4b67c5ae 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/exception.S +++ b/tools/testing/selftests/kvm/lib/loongarch/exception.S @@ -51,9 +51,15 @@ handle_exception: st.d t0, sp, ESTAT_OFFSET_EXREGS csrrd t0, LOONGARCH_CSR_BADV st.d t0, sp, BADV_OFFSET_EXREGS + csrrd t0, LOONGARCH_CSR_PRMD + st.d t0, sp, PRMD_OFFSET_EXREGS =20 or a0, sp, zero bl route_exception + ld.d t0, sp, PC_OFFSET_EXREGS + csrwr t0, LOONGARCH_CSR_ERA + ld.d t0, sp, PRMD_OFFSET_EXREGS + csrwr t0, LOONGARCH_CSR_PRMD restore_gprs sp csrrd sp, LOONGARCH_CSR_KS0 ertn --=20 2.39.3 From nobody Tue Dec 2 02:06:40 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E32CC2D7D2E; Thu, 20 Nov 2025 06:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621902; cv=none; b=ROjK+O5qj4vJfpGJrmth+pDtj1RuL5W/0dMeul97Q/eCEU7Qp1lopDTwgFUJ03V2lLqoO5fzScAHlUNdLUDQYRHIauxyJ1psTiGPChXsefQff2oz+ZLp9diM4ncxJA+JB9zNcGsvOqmR46DGVQmyHmou+EQdaV5AssiU9TCDbj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621902; c=relaxed/simple; bh=mpy38o7IPkXZYDW/opqrxRx3NKysg9a7Zk5SnY8wMKI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UhGnGRZF62qyH4AZnlQ5q8c3jbSOLtEeSsZPq+NIGrFDbktLWizCZfn1XGw11U75tK3NyEiYZbqhF99iMiQIGAXT4Mpqy0QxuRfJO/Vq8S2ZuFJv0sa5zc/HRu8qYuQQhCA1mkXaX798NOBIA8fEEXR+1+yU1z/LBJdjVgRJY8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxxtAHvB5p_f4lAA--.14920S3; Thu, 20 Nov 2025 14:58:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S4; Thu, 20 Nov 2025 14:58:14 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Tianrui Zhao , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: [PATCH v3 2/6] KVM: LoongArch: selftests: Add basic interfaces Date: Thu, 20 Nov 2025 14:57:54 +0800 Message-Id: <20251120065758.3064368-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Add some basic function interfaces such as CSR register access, local irq enable or disable APIs. Signed-off-by: Bibo Mao --- .../kvm/include/loongarch/processor.h | 52 +++++++++++++++++++ .../selftests/kvm/lib/loongarch/processor.c | 5 ++ 2 files changed, 57 insertions(+) diff --git a/tools/testing/selftests/kvm/include/loongarch/processor.h b/to= ols/testing/selftests/kvm/include/loongarch/processor.h index 374caddfb0db..0bf120d23092 100644 --- a/tools/testing/selftests/kvm/include/loongarch/processor.h +++ b/tools/testing/selftests/kvm/include/loongarch/processor.h @@ -113,6 +113,28 @@ #define CSR_TLBREHI_PS_SHIFT 0 #define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT) =20 +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__( \ + "csrrd %[val], %[reg]\n\t" \ + : [val] "=3Dr" (__v) \ + : [reg] "i" (csr) \ + : "memory"); \ + __v; \ +}) + +#define csr_write(v, csr) \ +({ \ + register unsigned long __v =3D v; \ + __asm__ __volatile__ ( \ + "csrwr %[val], %[reg]\n\t" \ + : [val] "+r" (__v) \ + : [reg] "i" (csr) \ + : "memory"); \ + __v; \ +}) + #define EXREGS_GPRS (32) =20 #ifndef __ASSEMBLER__ @@ -133,6 +155,36 @@ struct ex_regs { #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd) #define EXREGS_SIZE sizeof(struct ex_regs) =20 +static inline void local_irq_enable(void) +{ + unsigned int flags =3D CSR_CRMD_IE; + + register unsigned int mask asm("$t0") =3D CSR_CRMD_IE; + + __asm__ __volatile__( + "csrxchg %[val], %[mask], %[reg]\n\t" + : [val] "+r" (flags) + : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) + : "memory"); +} + +static inline void local_irq_disable(void) +{ + unsigned int flags =3D 0; + + register unsigned int mask asm("$t0") =3D CSR_CRMD_IE; + + __asm__ __volatile__( + "csrxchg %[val], %[mask], %[reg]\n\t" + : [val] "+r" (flags) + : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD) + : "memory"); +} + +static inline void cpu_relax(void) +{ + asm volatile("nop" ::: "memory"); +} #else #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8) #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8) diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/= testing/selftests/kvm/lib/loongarch/processor.c index 0ac1abcb71cb..5b5f09acf229 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/processor.c +++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c @@ -344,3 +344,8 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, v= oid *guest_code) regs.pc =3D (uint64_t)guest_code; vcpu_regs_set(vcpu, ®s); } + +uint32_t guest_get_vcpuid(void) +{ + return csr_read(LOONGARCH_CSR_CPUID); +} --=20 2.39.3 From nobody Tue Dec 2 02:06:40 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 854B230146A; Thu, 20 Nov 2025 06:58:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621906; cv=none; b=HdithDV4/TwBo5lHu95DfO9bY3BYwP0HQ3covGLiLB/J/qhX20YWSmH8Ncnecuv1g+Fjwi6U+XuDf67b9b0xRH1vvLPalkgtetY/2LIpWo4rzckwuAhm89Mksg6ugSfB2lKM78mm5ffxRcwHbB8YqVsfI/434o9xqba5LQxJoIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621906; c=relaxed/simple; bh=Hrayqg9KoT2jTaTXtUgtYEvgDpoR9jSt23jxQa+Sthc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nui4Fr7RhLae3BjK9MFIIo9awaNE1lcyit4S/cEypWS45GelCrCgkhucdgTbiRV7Y5Bw49CUPEw3tKx0ufiJKbwkw/avb6qbwzWPOBU4J0tZnvYW0qB1VugsqeJXsICQKOVq/Se05zSGSrDUvfF5xAQ2B/q86NmaztJqeBGaR7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxJ9EJvB5pBP8lAA--.15859S3; Thu, 20 Nov 2025 14:58:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S5; Thu, 20 Nov 2025 14:58:16 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Tianrui Zhao , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: [PATCH v3 3/6] KVM: LoongArch: selftests: Add exception handler register interface Date: Thu, 20 Nov 2025 14:57:55 +0800 Message-Id: <20251120065758.3064368-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Add interrupt and exception handler register interface. When exception happens, execute registered exception handler if exists, else report error. Signed-off-by: Bibo Mao --- .../kvm/include/loongarch/processor.h | 14 +++++++++ .../selftests/kvm/lib/loongarch/processor.c | 29 +++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/tools/testing/selftests/kvm/include/loongarch/processor.h b/to= ols/testing/selftests/kvm/include/loongarch/processor.h index 0bf120d23092..b027f8f4dac7 100644 --- a/tools/testing/selftests/kvm/include/loongarch/processor.h +++ b/tools/testing/selftests/kvm/include/loongarch/processor.h @@ -84,6 +84,11 @@ #define LOONGARCH_CSR_EUEN 0x2 #define LOONGARCH_CSR_ECFG 0x4 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ +#define CSR_ESTAT_EXC_SHIFT 16 +#define CSR_ESTAT_EXC_WIDTH 6 +#define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT) +#define EXCCODE_INT 0 /* Interrupt */ +#define INT_TI 11 /* Timer interrupt*/ #define LOONGARCH_CSR_ERA 0x6 /* ERA */ #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ #define LOONGARCH_CSR_EENTRY 0xc @@ -155,6 +160,15 @@ struct ex_regs { #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd) #define EXREGS_SIZE sizeof(struct ex_regs) =20 +#define VECTOR_NUM 64 +typedef void(*handler_fn)(struct ex_regs *); +struct handlers { + handler_fn exception_handlers[VECTOR_NUM]; +}; + +void vm_init_descriptor_tables(struct kvm_vm *vm); +void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_f= n handler); + static inline void local_irq_enable(void) { unsigned int flags =3D CSR_CRMD_IE; diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/= testing/selftests/kvm/lib/loongarch/processor.c index 5b5f09acf229..20ba476ccb72 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/processor.c +++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c @@ -11,6 +11,7 @@ #define LOONGARCH_GUEST_STACK_VADDR_MIN 0x200000 =20 static vm_paddr_t invalid_pgtable[4]; +static vm_vaddr_t exception_handlers; =20 static uint64_t virt_pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int leve= l) { @@ -184,6 +185,13 @@ void assert_on_unhandled_exception(struct kvm_vcpu *vc= pu) void route_exception(struct ex_regs *regs) { unsigned long pc, estat, badv; + int vector; + struct handlers *handlers; + + handlers =3D (struct handlers *)exception_handlers; + vector =3D (regs->estat & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; + if (handlers && handlers->exception_handlers[vector]) + return handlers->exception_handlers[vector](regs); =20 pc =3D regs->pc; badv =3D regs->badv; @@ -192,6 +200,27 @@ void route_exception(struct ex_regs *regs) while (1) ; } =20 +void vm_init_descriptor_tables(struct kvm_vm *vm) +{ + void *addr; + + vm->handlers =3D __vm_vaddr_alloc(vm, sizeof(struct handlers), + LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); + + addr =3D addr_gva2hva(vm, vm->handlers); + memset(addr, 0, vm->page_size); + exception_handlers =3D vm->handlers; + sync_global_to_guest(vm, exception_handlers); +} + +void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_f= n handler) +{ + struct handlers *handlers =3D addr_gva2hva(vm, vm->handlers); + + assert(vector < VECTOR_NUM); + handlers->exception_handlers[vector] =3D handler; +} + void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) { int i; 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cxf9MOvB5pCf8lAA--.15813S3; Thu, 20 Nov 2025 14:58:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S6; Thu, 20 Nov 2025 14:58:21 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Shuah Khan , Tianrui Zhao Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, loongarch@lists.linux.dev Subject: [PATCH v3 4/6] KVM: LoongArch: selftests: Add timer interrupt test case Date: Thu, 20 Nov 2025 14:57:56 +0800 Message-Id: <20251120065758.3064368-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Add timer test case based on common arch_timer code, timer interrupt with one-shot and period mode is tested. Signed-off-by: Bibo Mao --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../kvm/include/loongarch/arch_timer.h | 84 ++++++++++++ .../kvm/include/loongarch/processor.h | 10 ++ .../selftests/kvm/lib/loongarch/processor.c | 4 +- .../selftests/kvm/loongarch/arch_timer.c | 125 ++++++++++++++++++ 5 files changed, 222 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/loongarch/arch_time= r.h create mode 100644 tools/testing/selftests/kvm/loongarch/arch_timer.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 148d427ff24b..9d01f4d0e3f9 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -210,6 +210,7 @@ TEST_GEN_PROGS_riscv +=3D mmu_stress_test TEST_GEN_PROGS_riscv +=3D rseq_test TEST_GEN_PROGS_riscv +=3D steal_time =20 +TEST_GEN_PROGS_loongarch =3D arch_timer TEST_GEN_PROGS_loongarch +=3D coalesced_io_test TEST_GEN_PROGS_loongarch +=3D demand_paging_test TEST_GEN_PROGS_loongarch +=3D dirty_log_perf_test diff --git a/tools/testing/selftests/kvm/include/loongarch/arch_timer.h b/t= ools/testing/selftests/kvm/include/loongarch/arch_timer.h new file mode 100644 index 000000000000..b6399e748f72 --- /dev/null +++ b/tools/testing/selftests/kvm/include/loongarch/arch_timer.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * LoongArch Constant Timer specific interface + */ +#ifndef SELFTEST_KVM_ARCH_TIMER_H +#define SELFTEST_KVM_ARCH_TIMER_H + +#include "processor.h" +/* LoongArch timer frequency is constant 100MHZ */ +#define TIMER_FREQ (100UL << 20) +#define msec_to_cycles(msec) (TIMER_FREQ * (unsigned long)(msec) / 1000) +#define usec_to_cycles(usec) (TIMER_FREQ * (unsigned long)(usec) / 1000000) +#define cycles_to_usec(cycles) ((unsigned long)(cycles) * 1000000 / TIMER_= FREQ) + +static inline unsigned long timer_get_cycles(void) +{ + unsigned long val =3D 0; + + __asm__ __volatile__( + "rdtime.d %0, $zero\n\t" + : "=3Dr"(val) + : + ); + + return val; +} + +static inline void timer_set_next_cmp_ms(unsigned int msec, bool period) +{ + unsigned long val; + + val =3D msec_to_cycles(msec) & CSR_TCFG_VAL; + val |=3D CSR_TCFG_EN; + if (period) + val |=3D CSR_TCFG_PERIOD; + csr_write(val, LOONGARCH_CSR_TCFG); +} + +static inline void disable_timer(void) +{ + csr_write(0, LOONGARCH_CSR_TCFG); +} + +static inline unsigned long timer_get_val(void) +{ + return csr_read(LOONGARCH_CSR_TVAL); +} + +static inline unsigned long timer_get_cfg(void) +{ + return csr_read(LOONGARCH_CSR_TCFG); +} + +static inline void timer_irq_enable(void) +{ + unsigned long val; + + val =3D csr_read(LOONGARCH_CSR_ECFG); + val |=3D ECFGF_TIMER; + csr_write(val, LOONGARCH_CSR_ECFG); +} + +static inline void timer_irq_disable(void) +{ + unsigned long val; + + val =3D csr_read(LOONGARCH_CSR_ECFG); + val &=3D ~ECFGF_TIMER; + csr_write(val, LOONGARCH_CSR_ECFG); +} + +static inline void __delay(uint64_t cycles) +{ + uint64_t start =3D timer_get_cycles(); + + while ((timer_get_cycles() - start) < cycles) + cpu_relax(); +} + +static inline void udelay(unsigned long usec) +{ + __delay(usec_to_cycles(usec)); +} +#endif /* SELFTEST_KVM_ARCH_TIMER_H */ diff --git a/tools/testing/selftests/kvm/include/loongarch/processor.h b/to= ols/testing/selftests/kvm/include/loongarch/processor.h index b027f8f4dac7..61f6e215046b 100644 --- a/tools/testing/selftests/kvm/include/loongarch/processor.h +++ b/tools/testing/selftests/kvm/include/loongarch/processor.h @@ -83,6 +83,8 @@ #define LOONGARCH_CSR_PRMD 0x1 #define LOONGARCH_CSR_EUEN 0x2 #define LOONGARCH_CSR_ECFG 0x4 +#define ECFGB_TIMER 11 +#define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER)) #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ #define CSR_ESTAT_EXC_SHIFT 16 #define CSR_ESTAT_EXC_WIDTH 6 @@ -111,6 +113,14 @@ #define LOONGARCH_CSR_KS1 0x31 #define LOONGARCH_CSR_TMID 0x40 #define LOONGARCH_CSR_TCFG 0x41 +#define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2)) +#define CSR_TCFG_PERIOD_SHIFT 1 +#define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT) +#define CSR_TCFG_EN (0x1UL) +#define LOONGARCH_CSR_TVAL 0x42 +#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ +#define CSR_TINTCLR_TI_SHIFT 0 +#define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) /* TLB refill exception entry */ #define LOONGARCH_CSR_TLBRENTRY 0x88 #define LOONGARCH_CSR_TLBRSAVE 0x8b diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/= testing/selftests/kvm/lib/loongarch/processor.c index 20ba476ccb72..436990258068 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/processor.c +++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c @@ -271,8 +271,8 @@ static void loongarch_vcpu_setup(struct kvm_vcpu *vcpu) TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } =20 - /* user mode and page enable mode */ - val =3D PLV_USER | CSR_CRMD_PG; + /* kernel mode and page enable mode */ + val =3D PLV_KERN | CSR_CRMD_PG; loongarch_set_csr(vcpu, LOONGARCH_CSR_CRMD, val); loongarch_set_csr(vcpu, LOONGARCH_CSR_PRMD, val); loongarch_set_csr(vcpu, LOONGARCH_CSR_EUEN, 1); diff --git a/tools/testing/selftests/kvm/loongarch/arch_timer.c b/tools/tes= ting/selftests/kvm/loongarch/arch_timer.c new file mode 100644 index 000000000000..a8b7ff05faf6 --- /dev/null +++ b/tools/testing/selftests/kvm/loongarch/arch_timer.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * The test validates one-shot constant timer IRQ using CSR_TCFG and + * CSR_TVAL registers. + */ +#include "arch_timer.h" +#include "kvm_util.h" +#include "processor.h" +#include "timer_test.h" +#include "ucall_common.h" + +static void guest_irq_handler(struct ex_regs *regs) +{ + uint64_t xcnt, val, cfg, xcnt_diff_us; + unsigned int intid; + uint32_t cpu =3D guest_get_vcpuid(); + struct test_vcpu_shared_data *shared_data =3D &vcpu_shared_data[cpu]; + + intid =3D !!(regs->estat & BIT(INT_TI)); + + /* Make sure we are dealing with the correct timer IRQ */ + GUEST_ASSERT_EQ(intid, 1); + + cfg =3D timer_get_cfg(); + if (cfg & CSR_TCFG_PERIOD) { + WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter - 1); + if (shared_data->nr_iter =3D=3D 0) + disable_timer(); + csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR); + return; + } + + /* + * On physical machine, value of LOONGARCH_CSR_TVAL is BIT_ULL(48) - 1 + * On virtual machine, its value counts down from BIT_ULL(48) - 1 + */ + val =3D timer_get_val(); + xcnt =3D timer_get_cycles(); + xcnt_diff_us =3D cycles_to_usec(xcnt - shared_data->xcnt); + + /* Basic 'timer condition met' check */ + __GUEST_ASSERT(val > cfg, + "val =3D 0x%lx, cfg =3D 0x%lx, xcnt_diff_us =3D 0x%lx", + val, cfg, xcnt_diff_us); + + csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR); + WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1); +} + +static void guest_test_oneshot_timer(uint32_t cpu) +{ + uint32_t irq_iter, config_iter; + uint64_t us; + struct test_vcpu_shared_data *shared_data =3D &vcpu_shared_data[cpu]; + + shared_data->nr_iter =3D 0; + shared_data->guest_stage =3D 0; + us =3D msecs_to_usecs(test_args.timer_period_ms) + test_args.timer_err_ma= rgin_us; + for (config_iter =3D 0; config_iter < test_args.nr_iter; config_iter++) { + shared_data->xcnt =3D timer_get_cycles(); + + /* Setup the next interrupt */ + timer_set_next_cmp_ms(test_args.timer_period_ms, false); + /* Setup a timeout for the interrupt to arrive */ + udelay(us); + + irq_iter =3D READ_ONCE(shared_data->nr_iter); + __GUEST_ASSERT(config_iter + 1 =3D=3D irq_iter, + "config_iter + 1 =3D 0x%x, irq_iter =3D 0x%x.\n" + " Guest timer interrupt was not triggered within the specified\n" + " interval, try to increase the error margin by [-e] option.\n", + config_iter + 1, irq_iter); + } +} + +static void guest_test_period_timer(uint32_t cpu) +{ + uint32_t irq_iter; + uint64_t us; + struct test_vcpu_shared_data *shared_data =3D &vcpu_shared_data[cpu]; + + shared_data->nr_iter =3D test_args.nr_iter; + shared_data->xcnt =3D timer_get_cycles(); + us =3D msecs_to_usecs(test_args.timer_period_ms) + test_args.timer_err_ma= rgin_us; + timer_set_next_cmp_ms(test_args.timer_period_ms, true); + /* Setup a timeout for the interrupt to arrive */ + udelay(us * test_args.nr_iter); + irq_iter =3D READ_ONCE(shared_data->nr_iter); + __GUEST_ASSERT(irq_iter =3D=3D 0, + "irq_iter =3D 0x%x.\n" + " Guest period timer interrupt was not triggered within the specified\= n" + " interval, try to increase the error margin by [-e] option.\n", + irq_iter); +} + +static void guest_code(void) +{ + uint32_t cpu =3D guest_get_vcpuid(); + + timer_irq_enable(); + local_irq_enable(); + guest_test_oneshot_timer(cpu); + guest_test_period_timer(cpu); + + GUEST_DONE(); +} + +struct kvm_vm *test_vm_create(void) +{ + struct kvm_vm *vm; + int nr_vcpus =3D test_args.nr_vcpus; + + vm =3D vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); + vm_init_descriptor_tables(vm); + vm_install_exception_handler(vm, EXCCODE_INT, guest_irq_handler); + + /* Make all the test's cmdline args visible to the guest */ + sync_global_to_guest(vm, test_args); + return vm; +} + +void test_vm_cleanup(struct kvm_vm *vm) +{ + kvm_vm_free(vm); +} --=20 2.39.3 From nobody Tue Dec 2 02:06:40 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7E43D3074B2; Thu, 20 Nov 2025 06:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621915; cv=none; b=cj1W/aDk61RGpcZD+vW7/hKcRfPXBnkQ4hpitoYQQzo9TIoiDZ0QeMzlwyZjcwb/xiR0AlRdKG0xtVnS6YMcbTH+MEWylgCh0qFAHMTJlBMzpusfJVzFRvtYziFD0WOFV/NC9Dbv2UbKaLdVgpuAKoA/Qxa+0XkVDGWvYYIv/FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621915; c=relaxed/simple; bh=p+KMt1TLy15eZk16ICKi5cOb+za9KmA9NZgpKgv6oI0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jlxhyaOtSX0E8Caydaa/MXsnI9PbnqPm9Ql9oVnB4n2pF6CC1HDao2HGxIM4xIvqLtsQHyZv1qPhKjnyRYOvA0tyMEZ8uQSVBYs2HpUk/jYuxyMHF/Hh0qqLw7R+GCg0Oza8TIcodMrCTxoADOcLSnFeoLY8TZE6HJVxmzR8qlI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx778PvB5pDf8lAA--.14120S3; Thu, 20 Nov 2025 14:58:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S7; Thu, 20 Nov 2025 14:58:23 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH v3 5/6] KVM: LoongArch: selftests: Add SW emulated timer test Date: Thu, 20 Nov 2025 14:57:57 +0800 Message-Id: <20251120065758.3064368-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" This test case setup one-shot timer and execute idle instruction immediately to indicate giving up CPU, hypervisor will emulate SW hrtimer and wakeup vCPU when SW hrtimer is fired. Signed-off-by: Bibo Mao --- .../selftests/kvm/loongarch/arch_timer.c | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tools/testing/selftests/kvm/loongarch/arch_timer.c b/tools/tes= ting/selftests/kvm/loongarch/arch_timer.c index a8b7ff05faf6..ff6c141f0e2b 100644 --- a/tools/testing/selftests/kvm/loongarch/arch_timer.c +++ b/tools/testing/selftests/kvm/loongarch/arch_timer.c @@ -93,6 +93,45 @@ static void guest_test_period_timer(uint32_t cpu) irq_iter); } =20 +static void do_idle(void) +{ + unsigned int intid; + unsigned long estat; + + __asm__ __volatile__("idle 0" : : : "memory"); + + estat =3D csr_read(LOONGARCH_CSR_ESTAT); + intid =3D !!(estat & BIT(INT_TI)); + + /* Make sure pending timer IRQ arrived */ + GUEST_ASSERT_EQ(intid, 1); + csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR); +} + +static void guest_test_emulate_timer(uint32_t cpu) +{ + uint32_t config_iter; + uint64_t xcnt_diff_us, us; + struct test_vcpu_shared_data *shared_data =3D &vcpu_shared_data[cpu]; + + local_irq_disable(); + shared_data->nr_iter =3D 0; + us =3D msecs_to_usecs(test_args.timer_period_ms); + for (config_iter =3D 0; config_iter < test_args.nr_iter; config_iter++) { + shared_data->xcnt =3D timer_get_cycles(); + + /* Setup the next interrupt */ + timer_set_next_cmp_ms(test_args.timer_period_ms, false); + do_idle(); + + xcnt_diff_us =3D cycles_to_usec(timer_get_cycles() - shared_data->xcnt); + __GUEST_ASSERT(xcnt_diff_us >=3D us, + "xcnt_diff_us =3D 0x%lx, us =3D 0x%lx.\n", + xcnt_diff_us, us); + } + local_irq_enable(); +} + static void guest_code(void) { uint32_t cpu =3D guest_get_vcpuid(); @@ -101,6 +140,7 @@ static void guest_code(void) local_irq_enable(); guest_test_oneshot_timer(cpu); guest_test_period_timer(cpu); + guest_test_emulate_timer(cpu); =20 GUEST_DONE(); } --=20 2.39.3 From nobody Tue Dec 2 02:06:40 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 89DDC3081C6; Thu, 20 Nov 2025 06:58:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621917; cv=none; b=gfeA7USU2kEMQCo7Rqn9IYiejpiMOSMzBrB039tqfbZoPAXFqaVxFsfxo4+L0+YGTFgYEIcRIRNJK6N2VzElTYkbhSQdYWBiGhujichlfAZHFsqZzJ0Ps8XHVVyUwRans1KLeBfKWAMar6DWvGsvXhefrC+yy0/cP2WJUABMUdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763621917; c=relaxed/simple; bh=q8mZSXuohzehippU/FPYAjDpmwhTDFyBypn/Kwam0zE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Lxmpe+5gDcMUiwYfVa/rMLtcnhelrL1JEJn/L8PEd9tlFgpyl1YXjon6XFZNZW7NQ8ML363OBdbKi4iaXDL2ExsEqSd24bp5HwjTCeEhGAzTkRN0hsi4cb89Hfgy2dQXjfnA0UeyI34v5zpcMzzr9PYM85DlKJWBplIJwPETYUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx5tASvB5pE_8lAA--.16511S3; Thu, 20 Nov 2025 14:58:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxicD3ux5pSkU5AQ--.5850S8; Thu, 20 Nov 2025 14:58:25 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Sean Christopherson , Huacai Chen , Tianrui Zhao , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: [PATCH v3 6/6] KVM: LoongArch: selftests: Add time counter test Date: Thu, 20 Nov 2025 14:57:58 +0800 Message-Id: <20251120065758.3064368-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251120065758.3064368-1-maobibo@loongson.cn> References: <20251120065758.3064368-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxicD3ux5pSkU5AQ--.5850S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With time counter test, it is to verify that time count starts from 0 and always grows up then. Signed-off-by: Bibo Mao --- .../selftests/kvm/lib/loongarch/processor.c | 9 ++++++ .../selftests/kvm/loongarch/arch_timer.c | 29 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/= testing/selftests/kvm/lib/loongarch/processor.c index 436990258068..ac2ffd076bff 100644 --- a/tools/testing/selftests/kvm/lib/loongarch/processor.c +++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c @@ -3,6 +3,7 @@ #include #include =20 +#include #include "kvm_util.h" #include "processor.h" #include "ucall_common.h" @@ -256,6 +257,11 @@ static void loongarch_set_csr(struct kvm_vcpu *vcpu, u= int64_t id, uint64_t val) __vcpu_set_reg(vcpu, csrid, val); } =20 +static void loongarch_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t= val) +{ + __vcpu_set_reg(vcpu, id, val); +} + static void loongarch_vcpu_setup(struct kvm_vcpu *vcpu) { int width; @@ -279,6 +285,9 @@ static void loongarch_vcpu_setup(struct kvm_vcpu *vcpu) loongarch_set_csr(vcpu, LOONGARCH_CSR_ECFG, 0); loongarch_set_csr(vcpu, LOONGARCH_CSR_TCFG, 0); loongarch_set_csr(vcpu, LOONGARCH_CSR_ASID, 1); + /* time count start from 0 */ + val =3D 0; + loongarch_set_reg(vcpu, KVM_REG_LOONGARCH_COUNTER, val); =20 val =3D 0; width =3D vm->page_shift - 3; diff --git a/tools/testing/selftests/kvm/loongarch/arch_timer.c b/tools/tes= ting/selftests/kvm/loongarch/arch_timer.c index ff6c141f0e2b..d1cdf7f4ae55 100644 --- a/tools/testing/selftests/kvm/loongarch/arch_timer.c +++ b/tools/testing/selftests/kvm/loongarch/arch_timer.c @@ -132,10 +132,39 @@ static void guest_test_emulate_timer(uint32_t cpu) local_irq_enable(); } =20 +static void guest_time_count_test(uint32_t cpu) +{ + uint32_t config_iter; + unsigned long start, end, prev, us; + + /* Assuming that test case starts to run in 1 second */ + start =3D timer_get_cycles(); + us =3D msec_to_cycles(1000); + __GUEST_ASSERT(start <=3D us, + "start =3D 0x%lx, us =3D 0x%lx.\n", + start, us); + + us =3D msec_to_cycles(test_args.timer_period_ms); + for (config_iter =3D 0; config_iter < test_args.nr_iter; config_iter++) { + start =3D timer_get_cycles(); + end =3D start + us; + /* test time count growing up always */ + while (start < end) { + prev =3D start; + start =3D timer_get_cycles(); + __GUEST_ASSERT(prev <=3D start, + "prev =3D 0x%lx, start =3D 0x%lx.\n", + prev, start); + } + } +} + static void guest_code(void) { uint32_t cpu =3D guest_get_vcpuid(); =20 + /* must run at first */ + guest_time_count_test(cpu); timer_irq_enable(); local_irq_enable(); guest_test_oneshot_timer(cpu); --=20 2.39.3