From nobody Tue Dec 2 01:50:46 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345102BDC23 for ; Thu, 20 Nov 2025 21:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672788; cv=none; b=Kq2xF0XigTw9S5pblPs+KCsaa4IxMqVXW36Lx+NuHiL1vLXlqhqFtv4q7NvEU09jtMAul1jd7tZ3ndBfsWTuL9FLBuOUq48sP9Kgi9WfetOrSGs4ameXdr5me3tPMI/72/qTEILoGkUUl8J3WdF43UJiS/Hjjnde2KKy6rZ3pgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672788; c=relaxed/simple; bh=AEAW1zkV8OeqaCPbh6SWv6MdSofvSEdgd3/hIrLWqaw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G/4gOgEhbdJtYeCSYD6cefPiYD4Y7J0BCXCBrHV/vQGw986nAy5hQcUINGf9ZFnzcVD0ZT/dRZFGgX6gAfeZce1RaR2MdfGm7ciX0uccNOjB4CtyviDlpAckwAtZ4Cow2uQwJZvRJ+kPAgE7SVmHr1B5wyvuXTbNvZSsh3eBBQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=joAWUcDn; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="joAWUcDn" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-477632b0621so9434995e9.2 for ; Thu, 20 Nov 2025 13:06:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1763672784; x=1764277584; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4P55c+msKlLldk8RQlFeWnhvqXv9aJ+FbKMuCPpgPH4=; b=joAWUcDndOoNaIKDQfnBYU+hgMr6KdpHrGnnkJA7vSlNJHMwdnou8m7q+okTlJM599 5Vnya8vIAoo/C6f52hgNViii0v3FM92SPrBKS+S02vyuJg0tKi3t2aRqXCvYwtBW+Uhp kmKWOF8x+0pYHV+n815jcHwwIyIvHDTlhUp/qYbylt1NlLLjc5xteY89rTfUeg4W49Bs WUrnN6NEPH4xZWxCFs+evcvt2wGz6hnjMU3ovqorppRu+ldgirCtpENXgOZXdR1ZMv0V 7PBVTrcNQEa5l2AUxehdQhfSxeE+hWPVTJTdvLzaF5d7hExQcXJYq4WAcsS+CPoB5yDW ZUvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763672784; x=1764277584; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4P55c+msKlLldk8RQlFeWnhvqXv9aJ+FbKMuCPpgPH4=; b=qw9Y/Dm1uX78nJWngNxWsnyWqUyjPwaGmF2Apo3MjYxxVmvQ0KQ/xdMEqX3I3CP3pq O2+LUoHnqKOCQj5jCGdyGSTRn4M5RivWfLAJUJsNSuWAnmW5RdYoSDNuMm9ogJNuGRBX RM7UXudCHiqYhbQFqnU4CnuvJ2t8tTGzk4v5PWypfsk0ON+DnNMjPJUhBcvq8sv7Y8kI ZGbh+ukkhjIP/jqphMncrVx9OEn3trH1AxvOvbWE3/Jh6V+mlXVJDTLFCNZCWkBy0tVv eWoDsxA9qELLwsMaLv4BG4Ugwqvb9grZaaMuV1UetipBIyNUPVeF/c8uwmgMGGEXOptk LUGQ== X-Forwarded-Encrypted: i=1; AJvYcCWq68oJoSIvhcImBUuUuzcaU2eLff5jKELCwoCAFeAxY5cq6pMc98pDC5JS1EChZdR1rGQ3a14VhmpkvN4=@vger.kernel.org X-Gm-Message-State: AOJu0YwOxx59lDCPgFRYrY/XjiXbFZ6pRN93sVcjaBUWuk3XZiRTRuOB KwSiHvUCv2Pz8sOt88Sqv3DEJV00vssCNsd6jn/TX6VpRkPI5JLx7i0sBm1oEdT593Q= X-Gm-Gg: ASbGnct7XASdEDCtzvJeiYYQvh2MZmJHG2uxyiRJ44DQwjJlv6QHtke9w+kulTK2mHZ CSLx88TuicEt9RnyR9zR55uKu8bNWaNlJ6GBFrVAPVFWCVbyaKqTeKkSODmM+TyX3ha/acQWH50 nhB6MFkC21cihJVrrysYK0M1SktcZv0hnVCgHkCkPysA0fctD3ZVP1eA6x5RhSWaDA4xXtYE5fD GlSIhyDs2hXggWrmJ9J594U6e+Ye0f+PHI1JY9S5Ww9mA1HVaIAL2JSVXuyJLZ/766+bqhDPb87 q45ywO4EReXw2BzHlQOt4yn1xp2ot+YTLAPYAtlvvAaAWluNP+06sjbV7rms2FvSLPV6UB7VUmU LXYLa4fPtondR0M6IacFe+1TNr1FUPkSDWl+zvBYkzxAmBpJfSxQPu2srvty2dpDe6k6AZtdMfD JvSoFFGRYpR0ZNaKzdcMTvFVOPFJ+R6ut9QtKT+Nw= X-Google-Smtp-Source: AGHT+IGIJwaSzwyO+MTFf7E/UmXMY9JoeBa+FWmaF27jX5h2wNx7Xs7QpA0f1RkN48GTo1rGH2syUA== X-Received: by 2002:a05:6000:228a:b0:42b:3090:2680 with SMTP id ffacd0b85a97d-42cb9a0c90emr4361812f8f.10.1763672784217; Thu, 20 Nov 2025 13:06:24 -0800 (PST) Received: from gpeter-l.roam.corp.google.com ([150.228.9.80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e5b6sm7321287f8f.1.2025.11.20.13.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 13:06:23 -0800 (PST) From: Peter Griffin Date: Thu, 20 Nov 2025 21:06:11 +0000 Subject: [PATCH 1/4] dt-bindings: clock: google,gs101-clock: Add DPU clock management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251120-dpu-clocks-v1-1-11508054eab8@linaro.org> References: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> In-Reply-To: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> To: =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3579; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=AEAW1zkV8OeqaCPbh6SWv6MdSofvSEdgd3/hIrLWqaw=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBpH4LKxot89zhu24NNYx1+eiy+Zwr9lORhgN/Jz xQZOkSi7H+JAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaR+CygAKCRDO6LjWAjRy uo3aD/9g9k0zz3UXUDo7aMqJSONMZmDHvPz/woh+qQn2TNuKjaDa146nRp9NPCQVUIwKcDx6aRU pChHevHf+p7y3yDwltHYJenGXOth8wgzZKHFnIUiehTSnqMC2tPuCv7mEbDYCpYfEUrql2NQX4M BdvAJZs0AFMQzRijdxZyBJi5awaVcg5+jRqinP/EnCYM28jTGlSn7zWDdbrehJQ9YJSCcUyjTUg FtkaKbzJ9XNnbBuO56V0MamL3YVb4gwJLt8Ajv/2RiWvl7b/nFl/ByXfApCLBYYjjhq+7PJEx8s RcJ5OvrRGyyzd2m39Ix6Lng7/F9XbmuDfPi2lq1LkG7uEqeIXOyL2GYDSMTzOj/EdRMfSjL8Stm Bh8p+ZYAHin9iW/SSfSiqzzwzDkjfDUR0Nj1uBRfEv9KfSUCqKuTNda3Rgx1f0JUv6AiAx5zPls udrSZqPNh0mN3adzPUamcGaAKOa7Khlhewh2kFhimdhYo2zziABZiyIM0Co8Q3QABOCuG9MxT0X bxJsEJKopm/ZVPcKEh8UAiH7QRZc9CFLonoNvVQ2xCZcS72LIiijR1BSjSuXfFvQ2hUXgoJd+xx E4KXBF2E9fAIN9Rvi7Y1Pgh30pT8SWTMTLkKwps2dWL1Sb8Ovv22FHNQQpWOAxATgUmswVnhDrP uxGprmJfFeMEtww== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add dt schema documentation and clock IDs for the Display Process Unit (DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler, enhancer and compressor. Signed-off-by: Peter Griffin --- .../bindings/clock/google,gs101-clock.yaml | 19 ++++++++++++ include/dt-bindings/clock/google,gs101.h | 36 ++++++++++++++++++= ++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 09e679c1a9def03d53b8b493929911ea902a1763..1257be9c54a42ea2387e1112e53= b5ee1f03e09f5 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -34,6 +34,7 @@ properties: - google,gs101-cmu-hsi2 - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 + - google,gs101-cmu-dpu =20 clocks: minItems: 1 @@ -171,6 +172,24 @@ allOf: - const: bus - const: ip =20 + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: DPU bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings= /clock/google,gs101.h index 442f9e9037dc33198a1cee20af62fc70bbd96605..4ee46503663c1f8d9463536c347= de5d991474145 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -634,4 +634,40 @@ #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 =20 +/* CMU_DPU */ +#define CLK_MOUT_DPU_BUS_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_PCLK 3 +#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK 4 +#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM 5 +#define CLK_GOUT_DPU_DPUF_ACLK_DMA 6 +#define CLK_GOUT_DPU_DPUF_ACLK_DPP 7 +#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK 8 +#define CLK_GOUT_DPU_GPC_DPU_PCLK 9 +#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK 10 +#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK 11 +#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK 12 +#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK 13 +#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK 14 +#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK 15 +#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK 16 +#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK 17 +#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK 18 +#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK 19 +#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK 20 +#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK 21 +#define CLK_GOUT_DPU_SSMT_DPU0_ACLK 22 +#define CLK_GOUT_DPU_SSMT_DPU0_PCLK 23 +#define CLK_GOUT_DPU_SSMT_DPU1_ACLK 24 +#define CLK_GOUT_DPU_SSMT_DPU1_PCLK 25 +#define CLK_GOUT_DPU_SSMT_DPU2_ACLK 26 +#define CLK_GOUT_DPU_SSMT_DPU2_PCLK 27 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1 28 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2 29 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1 30 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2 31 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1 32 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2 33 +#define CLK_GOUT_DPU_SYSREG_DPU_PCLK 34 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ --=20 2.52.0.rc2.455.g230fcf2819-goog From nobody Tue Dec 2 01:50:46 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50D472FE04D for ; Thu, 20 Nov 2025 21:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672789; cv=none; b=TOVYXxnBj30s3qZCAhhuLjR8Vg15r0dqlD99wtv5HMuXwcmY+fVbIy3ugD1MhZdow/he4EBwoxpWRDLZvaaqPcbZtOBLXjAG9g+6xD/g8OU6cozNDLueyWtqY21e8AsxdhAEAxPj+PXz5Hf43E5broAc4/f3SUVDhhUcTc7bTgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672789; c=relaxed/simple; bh=hy/K6BGPw/RHqXahng2GeGBJJaR09CDU5bF5fZ2rVfM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TcNgzPuofGPYkxMHvKYoTKVkN8cnaeCvjxlJ9p/HIxuJvy1KtRAesH0vCSdbi4+vxWP8XvTZkE53axIxwwG28h9jxcz+kBrgYTQc2c4PV2GNw/oAl3f9lPFhz/7VuTMFOSt2ofqg7mLUIRGqPU+o0hIu9TmFo3u1G6hS5N481K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ksY/XdeT; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ksY/XdeT" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-42b32a3e78bso1128562f8f.0 for ; Thu, 20 Nov 2025 13:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1763672786; x=1764277586; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jGrpLSO7RqibWTIvvE58el48N4AMLKKXatRNlJSRkbc=; b=ksY/XdeTq12K5zcwXZXCAyyQ1GpS9oIl5WW+JfRFrHInfHHKRyXkeZ/y5/3NlF6LHT pJLiGPcM95lDO0RL/s3NwzAkqHAJAQQ1//bYMsytQr+BCvtkKNhHf+XeNnBRMrwD7yNd scGDD+5D0+Ex/4xhMIRfhUfrMqu7FtzRUMvIRVauK4+5s0BJciHpB3HiCyImeaovdjjo YLauLeLlUfntlC2QkVBV7Dzr6c4LyFWBFSvyFdM5wdxlBwvZT0M/K9vSxkC2j15madjb MHVr0Of7w446jxcsTlk/0tOWFUdXnikpRXqGTyawgmhX3Kk7O43hd6dI7EDUfW/oCXNf 1z7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763672786; x=1764277586; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jGrpLSO7RqibWTIvvE58el48N4AMLKKXatRNlJSRkbc=; b=Nenf40v0B5tmOAY2T2ho8OevvDle+8b7X5Sr7Eef82+52WRJacZeGDUuhmHiF9mFYC Yj2U4UbZHVNDRDQ+0wqUEUMjase1iLiBEzLPAF4JfK5AoBIzXsj8LUmMCL5V5a8+t1e5 gYH5r01FzKQR8WITEQJab6GJhQXEuT0sknh63527D0bcT/wQHb8H7bNA0DQVR3deH4qb tMRyajVfCQmifMvDM4SjkftumljLggFtns7iVDMnVV00rzxfkfvZYuRtXm1NylNjYOck 8qzF4hQqFvFQMPeCmkcZfugmyw9JlZci+t0ZFh+fZNq6fXHHgQhbnughW9AErWKheGrz yzvw== X-Forwarded-Encrypted: i=1; AJvYcCUehIOj3ityAN2TW5zvmTEduIDQmN9aT3Iyv6ROPSwEIhoa4LsD4A65tYVMwoBraXgartISZIUNScsoU1Y=@vger.kernel.org X-Gm-Message-State: AOJu0Ywd4a14rcAXuSgtWLQScR9iBqTpDnPZtxB4y/DZzZP4YOi/fjOv VifV1BXKZzxUKIpjLd0cuy4croRWGRznitlhioKfKdnsNJI4LP7tdlDRGqq6jT+v7kA= X-Gm-Gg: ASbGncu3o6fRuk/oGoWTlJ106Y8enavAjbcEgg1IbvZlWlJowjM5QVq9N2mSxvev7Fg A8XVIl8cLmOsPeJS0uNqFPE2eXTTIuoZDi5mWADz37+BlpCpihL7Nf/zMct5aYwicM7ZCjrRUAr Pmb5PdThCS65s412pC/roCaSmnTaCSNMZRwC83UAsM+h2wjTFdryvIPzk0wUZQSCzANltQTY+5D TqpOSsNcs1wpOTcyPr0OpITie+FJYxGIUwB02fNd/TuzmnKt+M9Rkpz9ajT929oVbt9KjE25ID8 lzxSVMMwdsTL2WvRcFx/1b7qdtBQn1njsAacokHws/4pmMThtqp4QVaz1WAHTHT0foaJsprA/XV jKBy+1p/sEYyNTWAHMGjiRsNoGXwoyvyER2XBjpXTILpyDrOHWb8tYc9UR6zSSnrk3nAFrz3smw zr3YiTeLQWzvNpvHxp9r09GT5bWJMq02fYghYppCA= X-Google-Smtp-Source: AGHT+IGRh9YI5GYMBjiLuiPtf2I0mkD9KZvk950BHI0yExr1aKpde6+NDWQM8tzXu5YIrtApVzQJ6A== X-Received: by 2002:a5d:5f96:0:b0:42c:a449:d68c with SMTP id ffacd0b85a97d-42cbfb0864cmr837159f8f.30.1763672785635; Thu, 20 Nov 2025 13:06:25 -0800 (PST) Received: from gpeter-l.roam.corp.google.com ([150.228.9.80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e5b6sm7321287f8f.1.2025.11.20.13.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 13:06:25 -0800 (PST) From: Peter Griffin Date: Thu, 20 Nov 2025 21:06:12 +0000 Subject: [PATCH 2/4] dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251120-dpu-clocks-v1-2-11508054eab8@linaro.org> References: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> In-Reply-To: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> To: =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1265; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=hy/K6BGPw/RHqXahng2GeGBJJaR09CDU5bF5fZ2rVfM=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBpH4LKmGf5AQvj6tGjpwDAMh3/sbxlKcWzGEccy rqgIKhyMUeJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaR+CygAKCRDO6LjWAjRy ug9pD/92Ed6TgocOI6TPwbPNBdeEnDmaN0qY7edZYHy4zhr+Gqir3v12M4hhu2ud2IAwFzx2Y2Q rGB1UHYXGMZkAMdhKqNZodUw6eopkvqUaqtyCrEtcRsaAxRgATFlHrpu7RxfrUgtmq1W6rMFGbY SnbW69Q5TzevSTfcEI3RoMQs5U9D37YZDj8eIcJ27UD5q3E2yrHdcDhZteWBSMAsU6X/9d4PMZ4 Fcyxk4TYEvasQHtPlhVEZ+ZrLIDkhjtr9DNkrWjsySnF465j8RnQScishN/C8gkOnUovNnTe/kT XyWOuuFHXSVCVSNFMLyZ9a2z+JtcgHqeT97ZOe2mnCLsM0WgeJC42acNdWBf3FieyO4eHrPVcUb RhHWgjj2v5FGWMXSJvL9O3Vrh1SpYsALsP6PQV66oxlynFV98xm6aGn3EEHIcrejftac5aYvT6X L9xSwuphPBxze2APX9E7DdxP13V5vOkHEnt5IcVPEnvdYEJDwnSezTOZ3a2oo93E0czHmthuKE+ I6YeT6WOhIeWn5oTVEax8H/vgA79Ge/jStIgofj1dc6ZhvvM0W7Dq6iPNovAZqle9yxuR80L4Jj 18skMFYo5GvGaFvc1MSaZ5I8biqifpLFNJK6xEgwZMgMnNB/qpNCNuZ5Xu+uymKPKldanRA2G8S qS21wV5IaZNh13g== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add dedicated compatibles for gs101 dpu sysreg controllers to the documentation. Signed-off-by: Peter Griffin --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index 5e1e155510b3b1137d95b87a1bade36c814eec4f..9c63dbcd4d77f930b916087b800= 8c7f9888a56f5 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -15,6 +15,7 @@ properties: - items: - enum: - google,gs101-apm-sysreg + - google,gs101-dpu-sysreg - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg - google,gs101-misc-sysreg @@ -92,6 +93,7 @@ allOf: compatible: contains: enum: + - google,gs101-dpu-sysreg - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg - google,gs101-misc-sysreg --=20 2.52.0.rc2.455.g230fcf2819-goog From nobody Tue Dec 2 01:50:46 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E848E305946 for ; Thu, 20 Nov 2025 21:06:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672791; cv=none; b=o73h3HCZVIdqmYiHXv3yxc+ydMNsZdy9OaQRnMnR0pnGdOtQU+tlpYf1XTMT6ptQCUPdcNtNIoKvM+CXps0vJV/Y5KYqAI/l8bhy1ty25QTfQBAVqVgiF38xV+3NQcmyJZg9GVHOfhGQ9wPQo1LMWrcb+y01mhClnq95m8mY3as= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672791; c=relaxed/simple; bh=aNCzham8+aVa4ydfofiJCpY6230eXXu6sfYAAe0zyFc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QYOydC9swOrtfRlCOeybyn/Sm7BozbefARZuSuUBXBMRpRazU8lAu19jA33EdSIYJhAZt9SWdcysp4lQv/o+r16whGF8jYIUIrjnarqWPfP01S2Rrhlec3lhEWn3tif49ELWuPHIJjgxnGGHZpZZ7ebCY1c57fNVopDULmuyIO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yrkGHTJw; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yrkGHTJw" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4779cb0a33fso13174875e9.0 for ; Thu, 20 Nov 2025 13:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1763672787; x=1764277587; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qr/XskJwABWEjaSIE0O5A6j6G7kGiwuQg/lwCc3XY9w=; b=yrkGHTJwfyha6n9pxPdVG0RvPterHAVbnHcS9jQp6R09X2kr6b2vnhwjYNV+UPUdM0 jIuadVa7x6u6hgPoR2+oOfHWRKCy8qAVn+vJm/+XO/fGMzryoc9HCR/58QJi4onCD0VM vglKXupEsWODIfIZj1GyZ0bFxpzE+09CmkxbHXxZmwsQoLJK30jHStMF/C1hrzlG802b y5PYOw9NyMYSNI+nVhyqs8A+LXnDHzXo6n1sAt05UalVXAL0oF+AwT89TTNp4Wzn+mgs cpQD0WOI58JPhfk6A4zetPbr6omxPffhqdk/GG08Fa1GR4BdhpCx2CVEYtdVG+ue1LRM 1QZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763672787; x=1764277587; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qr/XskJwABWEjaSIE0O5A6j6G7kGiwuQg/lwCc3XY9w=; b=k6/rQCEm3HmuIayhz0HL0wn7/vCfuaI5X3GXKoJ30f029iqQ2fN9AeuZWBPzpuEWL7 Zq/57R3FgYw/BBTrgOXv7FxTDC9zbZ+QQiv6b5JYMnBOFXlDZZQbAkK43/yVo5+MglC4 5YeKSwLoG7VDNdERE32h59LycENEX9XRdp1IuIUayFXP1z5POyBTrLkrWjDLsmuTENDf jDRBKVttpriOTjlT7Xwf+wBDp+5gg2Tal1LhIrV69A5sJFJBpmK+vXJHW3LxNM6o1JWt zg83MrTMAiAEO8Ywu2DPovT4+993DdbD0oo8Zcau4mIbh3cuho9BvVfg0TjQnEv8RYwm sKVA== X-Forwarded-Encrypted: i=1; AJvYcCXDmURC8m92WCF3it+pJ0rHQRCM/fRDj/0TWVdrRwn6mLXQle68XzqYiakPTU3OC3KIzTM0UeHKgUTThc0=@vger.kernel.org X-Gm-Message-State: AOJu0Ywu4dg1EYKQ0W6UWnQXsP2N7c1IFmvND2u6LnkanT+9/eMZQaRB Ggc0FGOddR7T2wK3C+j4TgzQNczwk6c607LsKcc76/TfZ717Q+ZpnnAHUUHzFGDuH3M= X-Gm-Gg: ASbGnct98NYS5Dqhv1knZuX9PVAgr1MY1sBh0CMu3soxCG2ZtnDd7vBKyY4GsBfQmwD QhHd5wOvy9x/JIEZnDpyUxOUCJ5uWZuK32o/51NCQRX897G3nfryefvzKRBANlYHejJfOOqEnyV VjK1OusErADK9o8kLFz6kCFJCAAffY4IIdPPp1d2dU3OLNjmWz68FHD8G5fB5E5XCfFoWGrQHbo HjrP34PGKKVpe90hqxQdQRmUfpHbu8/8Oqoe15KCna6dusxJUlZiKyBf5kcxrdSem4rZPRpuJB6 D2QDKjvfWvJXPTNpaKbAjQa8ON/qK0o1GGxJCI8XgHKWTkcUF8fS8yL4563qRYZSmslNx0i2wqd FQeG5SCsA3BJVL+oyj76zk5pDhN6NZ9uAjznY/hR1EStZEUmP+yst8fOfZA+SOGimtzYQ8zHO3d CIiZ+XFN03IG2wFtVW4hrxDl7/239McHtkvTQFfZE= X-Google-Smtp-Source: AGHT+IEz77AFQRfOz9D9vMUdFJ4yGf63OlGCx9aS4W+OUx3VSIJC3ZvMc8VWi7zfzOHOEQpRahi04w== X-Received: by 2002:a05:600c:4e8e:b0:477:5aaa:57a3 with SMTP id 5b1f17b1804b1-477c017512dmr1362985e9.2.1763672787259; Thu, 20 Nov 2025 13:06:27 -0800 (PST) Received: from gpeter-l.roam.corp.google.com ([150.228.9.80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e5b6sm7321287f8f.1.2025.11.20.13.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 13:06:26 -0800 (PST) From: Peter Griffin Date: Thu, 20 Nov 2025 21:06:13 +0000 Subject: [PATCH 3/4] arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251120-dpu-clocks-v1-3-11508054eab8@linaro.org> References: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> In-Reply-To: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> To: =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1465; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=aNCzham8+aVa4ydfofiJCpY6230eXXu6sfYAAe0zyFc=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBpH4LLBaSMM+CzWBnI+jbY8yriXjZIgzTuqgBbt XOueJtJHVmJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaR+CywAKCRDO6LjWAjRy uultD/9/WEZe1LMumFGfEPAYEzFSldfvB0k+LVj0rv0zPwwvTx9bWMSMphDpfG/vtDnRjDlqHq0 lVjj0ycrXuuHr8qSj+CfpWyJGAgMOX5Q6zyVPqRIZSFZZ6GKXhhlOpJFMiX/EefDQ3R3MRHTqtm gBN2qVq62RHuC9N6ML/tpDy8FFyZowi079wwudvgH3vMIxzofB8uDOco2ZmtLvuB3ljgsvxqjre S32IFyuScIqC7eGNn6cZSOO6wkNBMQ+8jE8JLcUyCEcfQt/MSSG8AJtzVRPHm3H9frQJ9kxvt9u pPtPiTzDev4YVKvj3JuP92W2fIBDa+w76LS2/qXOtfeVMLYzxauowIOoiuIT7pdX3KBcw//+G4F wZlpQQHKfQ0emHnE9uy317YaAp/8Bn4tNq5VvJnIy4MqUnhE+3+W3O9gAziK4CM7ls4KrkyaNIz yty3Erw/zBNTmXn+XThp2u3tMi+uyKczmtBJVAVJI202nz4CihHA2N2DUscKw54L4ev8isGmM/+ 4ZrOzOQGkcbk6daBOTfGxx8xe/6mQEvjVp0eFnIpSxYz1fgl7zi5iGcA7cjdGGjJhdJYtxbC3RA tWH3oYeUKBM/Tym1qSnnfWUt8f8NXpVuUJSgyp/M7h69CXLd+qezf2g+Vaj9rLeyW64suoUKNBH GIJKENkgYHs92ag== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable the cmu_dpu clock management unit. It feeds some of the display IPs. Additionally add the sysreg_dpu node which contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable dynamic root clock gating of bus components. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index c39ca4c4508f046ca16ae86be42468c7245561b8..ac326db437fa8fe437cf11167bd= 8c1ce5c2ec186 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1798,6 +1798,23 @@ pinctrl_gsacore: pinctrl@17a80000 { status =3D "disabled"; }; =20 + cmu_dpu: clock-controller@1c000000 { + compatible =3D "google,gs101-cmu-dpu"; + reg =3D <0x1c000000 0x10000>; + #clock-cells =3D <1>; + + clocks =3D <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_DPU_BUS>; + clock-names =3D "oscclk", "bus"; + samsung,sysreg =3D <&sysreg_dpu>; + }; + + sysreg_dpu: syscon@1c020000 { + compatible =3D "google,gs101-dpu-sysreg", "syscon"; + reg =3D <0x1c020000 0x10000>; + clocks =3D <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>; + }; + cmu_top: clock-controller@1e080000 { compatible =3D "google,gs101-cmu-top"; reg =3D <0x1e080000 0x10000>; --=20 2.52.0.rc2.455.g230fcf2819-goog From nobody Tue Dec 2 01:50:46 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C221430BBBA for ; Thu, 20 Nov 2025 21:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672793; cv=none; b=Y7arfL+yumcJMo+enbnE0KsUB9vCUBAoLhdXbPtRGOuKCOtzhSVt2xtAARW03XT6jwNZcncH3QLqDOOsrq6wf7fN3p9H+xJoH/t/m38WVrIL5CwCzIH1ppXyFVnyNc3RZf4iCjZc1qJRg2uCjJFHX86JkblaiT+Fv8UCEy7KTr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763672793; c=relaxed/simple; bh=QHk8SiPa/eaPMZxAsAQiLzZk+6fLpZAERsS/cFDDl8A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=moYSqeknnTQ7YBTqdxXGlpQ+pT03Q6c1LZuQvsFYa3CjXiWieiK3K95TWef++FEofu0TiueGQcRfigQpssq/cPuaU9dqtgtX1ZojBi2yyqWowX7j3/pfrLe0KdjPvJfTuUXMfs1S34MTq3/Bet2Ss5g9y1u6VCSEvhGAwfdIzIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LVRZkR60; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LVRZkR60" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-42b3c965df5so766117f8f.1 for ; Thu, 20 Nov 2025 13:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1763672789; x=1764277589; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=K8BXYkJo09cffbco27DiXaVUKDDylvywu2kiuIHEYbM=; b=LVRZkR60NkJPy9hN4oUaj+PKWggxEnjH9hAs+JvT1CLT2xmdsydrIwVvXAKULSpOMj s1YMeWvKbO8/uc45Mb0EeVzEUO+Q26cdl7Vdn/i+2NSbmSHA79vWu73Ae5nRKBPKS0Dj YDifd4GGbjzPhsCXD/+9WvekRGwKiJF024OQrpSc6kbPXEuvp9o1ttgQBZRrRrIlqbGB kOugUlPuTRVhNFCyx1ulBZBUH8qkWe3RuG6XHBO9YqFr9JPqLUNdMU3uIB77585ZN+FT vGXykntK6N3+4EHmU5q4/N2o5ZiiX4O9Zt1Ya8Bz4qtnzmug761QiGhhIj66Oo+okXnN adDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763672789; x=1764277589; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=K8BXYkJo09cffbco27DiXaVUKDDylvywu2kiuIHEYbM=; b=fZhpcBz6UxFsnnXcqaFtWQz75xiJHIRBEtKUi5BPGFYrtRsv/f7GJqwnqVYzsq9Ugq p+2pIjKXC2WbHKNnutouDuR0Mqu8muGCHJEt+maXj5AYFZydrfzKbHn0S15DpUgf5NWa McMAsDVyRwr7DXiXiin9VPhE0CON0BomaAIctilNGJhVZFQ4fNU63yoGgMhYW4ZhQkqQ WhFfxK7eE0jFGgJJxGlTAS0UWn/QvQ9SWGE0yRoUCh4uEK2GKN50ebmHoWog2LbgCq+t 3op/AHy4v7uYBIi1kxbJq+c7xcXC2gPVWVSQvh0UkuQ/i1H3cY6Hsk4tz5YiEBK+pDH5 o/KQ== X-Forwarded-Encrypted: i=1; AJvYcCVuqg2DkHt989eeOEZ9KY8GFWKil3giY6YAMAp/cdBhUi8sIX/jnBjbNDwmNt0TJ6SabGUcVyjV7NDiYKE=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0Lv/Xom0at6uFpmZhp6antRG74y/lXLyLkw6PW01dzaHfiyH7 i444aadJT1oRdRnGKS406dtjK0SyjCinhlMqrzjulYH7q24VpyA2MceR1D+KpGYXcE0= X-Gm-Gg: ASbGncuYUOgNxvwWhzH7CYmmzZ/oAM2JtW0dwePGnv6IQzW1X+O8u3LPbIIbjWCkM6K vUiveS1yYgjFpsds7KuUSEpARfjyU5iXxzPenppqvPt7yg6ifbFmArDHSPfn0VA606AJkPnM+ny pU/3Y1tToeEwI9YEbhIB7eAUmigfSym2jMur7o7NlnU4z5GVd4RcBziphEYKSDfWxsCgl9Gyux4 Ipt2+oUs/SplnJUEvLnUHmXHatMcOkwHFA5w5plIVkoVRefTuyLqqJGq7urN7wbqwLqIXm16AQC 7w7VYssGeG+9qob2QrAdcm4k2BLcsEN0BuXKkbsxwwIxaPNdMGAqaS4d/wcSqgVbJVS+A7htOQ7 OJHCx75bV5QvvUXmqNOnb5ztAjErCvXBEtzWo8ZsMYBIG+d4h3wmhkq2/2HYSMre0k+MsXPu6TT zlYCD8HbH16k8HQGqVE3zBIv3gUhLBZTQxPi/5L6I= X-Google-Smtp-Source: AGHT+IF1y8NS7fSk9ziWEi5PszSWt8O9ekApxvVjAqVjXDU6OKQ3ZcI1ywbVKU56ntpqV90CAcY/xw== X-Received: by 2002:a5d:5d0a:0:b0:42b:4177:7136 with SMTP id ffacd0b85a97d-42cb9a6075fmr5196598f8f.32.1763672789027; Thu, 20 Nov 2025 13:06:29 -0800 (PST) Received: from gpeter-l.roam.corp.google.com ([150.228.9.80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e5b6sm7321287f8f.1.2025.11.20.13.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 13:06:28 -0800 (PST) From: Peter Griffin Date: Thu, 20 Nov 2025 21:06:14 +0000 Subject: [PATCH 4/4] clk: samsung: gs101: add support for Display Process Unit (DPU) clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251120-dpu-clocks-v1-4-11508054eab8@linaro.org> References: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> In-Reply-To: <20251120-dpu-clocks-v1-0-11508054eab8@linaro.org> To: =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Will McVicker , Juan Yescas , Doug Anderson , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15641; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=QHk8SiPa/eaPMZxAsAQiLzZk+6fLpZAERsS/cFDDl8A=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBpH4LLaQE+sYqCV4pJQLUBYS+awWcWDoBUANWyY B9Qz+UNyreJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaR+CywAKCRDO6LjWAjRy umlID/93RgADTcD22ilasX9gZ4Sdeps/lGe7ouZBzFVb4ZJ1GW+ehklO8xMW9bocRQ0bPS8dchZ jU/EZUk5+PLE20IJPra5D+QaCr06c7yuKHIIWXhcY73kbs+UaxSwnq1jpTpOinQifo4TPaMqWzB u4MHhUlyVw9jlHs5Zj0vs/gjTJmyXpSzzfGv3IOo3Pg0VElyt3OVSZEbWWU0oqzT5pXEdG0bciy Fb3FP6AaVBr7/vYjCuQmzN0+WQcTn90URC0L29DaxMBLG/4s85ro9OBdCneE/t+IDa6NWC2cJcQ 29mtKBjvUDBZF6FudmmIBnmgUmpJytm09zq69+NJaBhFmgVZo50JQWd5IXzuR7xE31DO6O9MXqE UoIwdSPGm5VnsUvKTAqdp/X8Pi/UNuDsmv2c65QAFrXsGYwMrOLLosR87tiU0ow43ao4ZTT2czC 1Po77OSkwdmnzw2OPmYigiIxLorjsGI1gQLLj3s/m+8YlGTV9KXHEwsZPTxw6ZM/4iSNWGO9+ku BT+0zU16Q3dMLfTyxjnh+AuI6zOtq0ixt7BZc/C6QeEPpzW0/uDFTP5EBiHNVzmaY9fjxJ2JEfT +r2Mvtf+9PmQe0NqNEXr1/ZjRIw2PLVatn+B46Y+MTh06xVBW+2ldE6JT7gkNGfuTEMVDjyRIOz FQTpfE2EtNlNy6Q== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA cmu_dpu is the clock management unit used for the Display Process Unit block. It generates clocks for image scaler, compressor etc. Add support for the muxes, dividers and gates in cmu_dpu. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 283 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 283 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 8551289b46eb88ec61dd1914d0fe782ae6794000..82f2343ecc63cc285343cc79692= f3a199a9c16cc 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -25,6 +25,7 @@ #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) +#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1) =20 #define GS101_GATE_DBG_OFFSET 0x4000 #define GS101_DRCG_EN_OFFSET 0x104 @@ -4426,6 +4427,285 @@ static const struct samsung_cmu_info peric1_cmu_inf= o __initconst =3D { .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; =20 +/* ---- CMU_DPU ----------------------------------------------------------= --- */ + +/* Register Offset definitions for CMU_DPU (0x1c000000) */ +#define PLL_CON0_MUX_CLKCMU_DPU_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_DPU_BUS_USER 0x0604 +#define DPU_CMU_DPU_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 +#define CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK = 0x2004 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM 0x2008 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA 0x200c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP 0x2010 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK 0x2020 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK 0x2024 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK 0x2028 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK 0x202c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK 0x2034 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK 0x2038 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK 0x203c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK 0x2040 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK 0= x2044 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK 0= x2048 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK 0x204c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK 0x2054 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1 0x2064 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2 0x2068 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1 0x206c +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2 0x2070 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1 0x2074 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2 0x2078 +#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK 0x207c +#define PCH_CON_LHM_AXI_P_DPU_PCH 0x3000 +#define PCH_CON_LHS_AXI_D0_DPU_PCH 0x3004 +#define PCH_CON_LHS_AXI_D1_DPU_PCH 0x3008 +#define PCH_CON_LHS_AXI_D2_DPU_PCH 0x300c +#define QCH_CON_DPUF_QCH_DPU_DMA 0x3010 +#define QCH_CON_DPUF_QCH_DPU_DPP 0x3014 +#define QCH_CON_DPU_CMU_DPU_QCH 0x301c +#define QCH_CON_D_TZPC_DPU_QCH 0x3020 +#define QCH_CON_GPC_DPU_QCH 0x3024 +#define QCH_CON_LHM_AXI_P_DPU_QCH 0x3028 +#define QCH_CON_LHS_AXI_D0_DPU_QCH 0x302c +#define QCH_CON_LHS_AXI_D1_DPU_QCH 0x3030 +#define QCH_CON_LHS_AXI_D2_DPU_QCH 0x3034 +#define QCH_CON_PPMU_DPUD0_QCH 0x3038 +#define QCH_CON_PPMU_DPUD1_QCH 0x303c +#define QCH_CON_PPMU_DPUD2_QCH 0x3040 +#define QCH_CON_SSMT_DPU0_QCH 0x3044 +#define QCH_CON_SSMT_DPU1_QCH 0x3048 +#define QCH_CON_SSMT_DPU2_QCH 0x304c +#define QCH_CON_SYSMMU_DPUD0_QCH_S1 0x3050 +#define QCH_CON_SYSMMU_DPUD0_QCH_S2 0x3054 +#define QCH_CON_SYSMMU_DPUD1_QCH_S1 0x3058 +#define QCH_CON_SYSMMU_DPUD1_QCH_S2 0x305c +#define QCH_CON_SYSMMU_DPUD2_QCH_S1 0x3060 +#define QCH_CON_SYSMMU_DPUD2_QCH_S2 0x3064 +#define QCH_CON_SYSREG_DPU_QCH 0x3068 +#define QUEUE_CTRL_REG_BLK_DPU_CMU_DPU 0x3c00 + +static const unsigned long dpu_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, + PLL_CON1_MUX_CLKCMU_DPU_BUS_USER, + DPU_CMU_DPU_CONTROLLER_OPTION, + CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0, + CLK_CON_DIV_DIV_CLK_DPU_BUSP, + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, + PCH_CON_LHM_AXI_P_DPU_PCH, + PCH_CON_LHS_AXI_D0_DPU_PCH, + PCH_CON_LHS_AXI_D1_DPU_PCH, + PCH_CON_LHS_AXI_D2_DPU_PCH, + QCH_CON_DPUF_QCH_DPU_DMA, + QCH_CON_DPUF_QCH_DPU_DPP, + QCH_CON_DPU_CMU_DPU_QCH, + QCH_CON_D_TZPC_DPU_QCH, + QCH_CON_GPC_DPU_QCH, + QCH_CON_LHM_AXI_P_DPU_QCH, + QCH_CON_LHS_AXI_D0_DPU_QCH, + QCH_CON_LHS_AXI_D1_DPU_QCH, + QCH_CON_LHS_AXI_D2_DPU_QCH, + QCH_CON_PPMU_DPUD0_QCH, + QCH_CON_PPMU_DPUD1_QCH, + QCH_CON_PPMU_DPUD2_QCH, + QCH_CON_SSMT_DPU0_QCH, + QCH_CON_SSMT_DPU1_QCH, + QCH_CON_SSMT_DPU2_QCH, + QCH_CON_SYSMMU_DPUD0_QCH_S1, + QCH_CON_SYSMMU_DPUD0_QCH_S2, + QCH_CON_SYSMMU_DPUD1_QCH_S1, + QCH_CON_SYSMMU_DPUD1_QCH_S2, + QCH_CON_SYSMMU_DPUD2_QCH_S1, + QCH_CON_SYSMMU_DPUD2_QCH_S2, + QCH_CON_SYSREG_DPU_QCH, + QUEUE_CTRL_REG_BLK_DPU_CMU_DPU, +}; + +/* List of parent clocks for Muxes in CMU_DPU */ +PNAME(mout_dpu_bus_user_p) =3D { "oscclk", "dout_cmu_dpu_bus" }; + +static const struct samsung_mux_clock dpu_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_DPU_BUS_USER, "mout_dpu_bus_user", + mout_dpu_bus_user_p, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 4, 1), +}; + +static const struct samsung_div_clock dpu_div_clks[] __initconst =3D { + DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "", + CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock dpu_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_DPU_PCLK, "gout_dpu_dpu_pclk", + "dout_dpu_busp", + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK, "gout_dpu_clk_dpu_oscclk_clk", + "oscclk", + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM, "gout_dpu_ad_apb_dpu_dma_pclkm", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, + 21, 0, 0), + GATE(CLK_GOUT_DPU_DPUF_ACLK_DMA, "gout_dpu_dpuf_aclk_dma", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 21, 0, 0), + GATE(CLK_GOUT_DPU_DPUF_ACLK_DPP, "gout_dpu_dpuf_aclk_dpp", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 21, 0, 0), + GATE(CLK_GOUT_DPU_D_TZPC_DPU_PCLK, "gout_dpu_d_tzpc_dpu_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_GPC_DPU_PCLK, "gout_dpu_dpu_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK, "gout_dpu_lhm_axi_p_dpu_i_clk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK, "gout_dpu_lhs_axi_d0_dpu_i_clk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK, "gout_dpu_lhs_axi_d1_dpu_i_clk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK, "gout_dpu_lhs_axi_d2_dpu_i_clk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD0_ACLK, "gout_dpu_ppmu_dpud0_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD0_PCLK, "gout_dpu_ppmu_dpud0_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD1_ACLK, "gout_dpu_ppmu_dpud1_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD1_PCLK, "gout_dpu_ppmu_dpud1_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD2_ACLK, "gout_dpu_ppmu_dpud2_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_PPMU_DPUD2_PCLK, "gout_dpu_ppmu_dpud2_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_CLK_DPU_BUSD_CLK, "gout_dpu_clk_dpu_busd_clk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_CLK_DPU_BUSP_CLK, "gout_dpu_clk_dpu_busp_clk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU0_ACLK, "gout_dpu_ssmt_dpu0_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU0_PCLK, "gout_dpu_ssmt_dpu0_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU1_ACLK, "gout_dpu_ssmt_dpu1_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU1_PCLK, "gout_dpu_ssmt_dpu1_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU2_ACLK, "gout_dpu_ssmt_dpu2_aclk", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SSMT_DPU2_PCLK, "gout_dpu_ssmt_dpu2_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1, "gout_dpu_sysmmu_dpud0_clk_s1", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2, "gout_dpu_sysmmu_dpud0_clk_s2", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1, "gout_dpu_sysmmu_dpud1_clk_s1", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2, "gout_dpu_sysmmu_dpud1_clk_s2", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1, "gout_dpu_sysmmu_dpud2_clk_s1", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, + 21, 0, 0), + GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2, "gout_dpu_sysmmu_dpud2_clk_s2", + "mout_dpu_bus_user", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 21, 0, 0= ), + GATE(CLK_GOUT_DPU_SYSREG_DPU_PCLK, "gout_dpu_sysreg_dpu_pclk", + "dout_dpu_busp", + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info dpu_cmu_info __initconst =3D { + .mux_clks =3D dpu_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(dpu_mux_clks), + .div_clks =3D dpu_div_clks, + .nr_div_clks =3D ARRAY_SIZE(dpu_div_clks), + .gate_clks =3D dpu_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(dpu_gate_clks), + .nr_clk_ids =3D CLKS_NR_DPU, + .clk_regs =3D dpu_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(dpu_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D DPU_CMU_DPU_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, +}; + /* ---- platform_driver --------------------------------------------------= --- */ =20 static int __init gs101_cmu_probe(struct platform_device *pdev) @@ -4443,6 +4723,9 @@ static const struct of_device_id gs101_cmu_of_match[]= =3D { { .compatible =3D "google,gs101-cmu-apm", .data =3D &apm_cmu_info, + }, { + .compatible =3D "google,gs101-cmu-dpu", + .data =3D &dpu_cmu_info, }, { .compatible =3D "google,gs101-cmu-hsi0", .data =3D &hsi0_cmu_info, --=20 2.52.0.rc2.455.g230fcf2819-goog