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[2003:eb:5f27:c400:b58a:f32d:fc3c:bd97]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477b82e8ea6sm4909795e9.8.2025.11.19.10.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Nov 2025 10:47:39 -0800 (PST) From: iansdannapel@gmail.com To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, mdf@kernel.org, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, neil.armstrong@linaro.org, mani@kernel.org, kever.yang@rock-chips.com, dev@kael-k.io, iansdannapel@gmail.com Subject: [PATCH v5 3/3] fpga-mgr: Add Efinix SPI programming driver Date: Wed, 19 Nov 2025 19:47:06 +0100 Message-ID: <20251119184708.566461-4-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251119184708.566461-1-iansdannapel@gmail.com> References: <20251119184708.566461-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Ian Dannapel Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs. Signed-off-by: Ian Dannapel --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 256 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..b5d60ba62900 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -83,6 +83,13 @@ config FPGA_MGR_XILINX_SPI FPGA manager driver support for Xilinx FPGA configuration over slave serial interface. =20 +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI" + depends on SPI + help + FPGA manager driver support for Efinix FPGAs configuration over SPI + (passive mode only). + config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..adbd51d2cd1e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) +=3D ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) +=3D xilinx-core.o obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) +=3D xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) +=3D xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) +=3D efinix-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) +=3D zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) +=3D zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) +=3D versal-fpga.o diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c new file mode 100644 index 000000000000..953cf94f1f03 --- /dev/null +++ b/drivers/fpga/efinix-spi.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * FPGA Manager Driver for Efinix + * + * Copyright (C) 2025 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel + * + * Load Efinix FPGA firmware over SPI using the serial configuration inter= face. + * + * Note: Only passive mode (host initiates transfer) is currently supporte= d. + */ + +#include +#include +#include +#include +#include +#include + +/* 13 dummy bytes =E2=86=92 104 SPI clock cycles (8 bits each) + * Used to meet the requirement for >100 clock cycles idle sequence. + */ +#define EFINIX_SPI_IDLE_CYCLES_BYTES 13 + +/* tDMIN: Minimum time between deassertion of CRESET_N to first + * valid configuration data. (32 =C2=B5s) + */ +#define EFINIX_TDMIN_US_MIN 35 +#define EFINIX_TDMIN_US_MAX 40 + +/* tCRESET_N: Minimum CRESET_N low pulse width required to + * trigger re-configuration. (320 ns) + */ +#define EFINIX_TCRESETN_DELAY_MIN_US 1 +#define EFINIX_TCRESETN_DELAY_MAX_US 2 + +/* tUSER: Minimum configuration duration after CDONE goes high + * before entering user mode. (25 =C2=B5s) + */ +#define EFINIX_TUSER_US_MIN 30 +#define EFINIX_TUSER_US_MAX 35 + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *cdone; + struct gpio_desc *reset; + bool bus_locked; +}; + +static void efinix_spi_reset(struct efinix_spi_conf *conf) +{ + gpiod_set_value(conf->reset, 1); + usleep_range(EFINIX_TCRESETN_DELAY_MIN_US, EFINIX_TCRESETN_DELAY_MAX_US); + gpiod_set_value(conf->reset, 0); + usleep_range(EFINIX_TDMIN_US_MIN, EFINIX_TDMIN_US_MAX); +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf =3D mgr->priv; + + if (conf->cdone && gpiod_get_value(conf->cdone) =3D=3D 1) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_transfer assert_cs =3D { + .cs_change =3D 1, + }; + struct spi_message message; + int ret; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EOPNOTSUPP; + } + + spi_bus_lock(conf->spi->controller); + conf->bus_locked =3D true; + spi_message_init_with_transfers(&message, &assert_cs, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + spi_bus_unlock(conf->spi->controller); + conf->bus_locked =3D false; + return ret; + } + + /* Reset with CS asserted */ + efinix_spi_reset(conf); + + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct spi_transfer write_xfer =3D { + .tx_buf =3D buf, + .len =3D count, + .cs_change =3D 1, /* Keep CS asserted */ + }; + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_message message; + int ret; + + spi_message_init_with_transfers(&message, &write_xfer, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", ret); + if (conf->bus_locked) { + spi_bus_unlock(conf->spi->controller); + conf->bus_locked =3D false; + } + } + return ret; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + unsigned long timeout =3D + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + struct spi_transfer clk_cycles =3D { + .len =3D EFINIX_SPI_IDLE_CYCLES_BYTES, + }; + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_message message; + int ret =3D -1, done =3D 0; + bool expired =3D false; + u8 *dummy_buf; + + dummy_buf =3D kzalloc(EFINIX_SPI_IDLE_CYCLES_BYTES, GFP_KERNEL); + if (!dummy_buf) { + ret =3D -ENOMEM; + goto unlock_spi; + } + + clk_cycles.tx_buf =3D dummy_buf; + spi_message_init_with_transfers(&message, &clk_cycles, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + dev_err(&mgr->dev, "SPI error in write complete: %d\n", ret); + goto free_buf; + } + + if (conf->cdone) { + while (!expired) { + done =3D gpiod_get_value(conf->cdone); + if (done < 0) { + ret =3D done; + goto free_buf; + } + if (done) + break; + + usleep_range(10, 20); + expired =3D time_after(jiffies, timeout); + } + + if (expired) { + dev_err(&mgr->dev, "Timeout waiting for CDONE\n"); + ret =3D -ETIMEDOUT; + goto free_buf; + } + } + + usleep_range(EFINIX_TUSER_US_MIN, EFINIX_TUSER_US_MAX); + +free_buf: + kfree(dummy_buf); +unlock_spi: + if (conf->bus_locked) { + spi_bus_unlock(conf->spi->controller); + conf->bus_locked =3D false; + } + return ret; +} + +static const struct fpga_manager_ops efinix_spi_ops =3D { + .state =3D efinix_spi_state, + .write_init =3D efinix_spi_write_init, + .write =3D efinix_spi_write, + .write_complete =3D efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + conf =3D devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi =3D spi; + + conf->reset =3D devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->reset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->reset), + "Failed to get RESET gpio\n"); + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, -EINVAL, + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf->cdone =3D devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); + if (IS_ERR(conf->cdone)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), + "Failed to get CDONE gpio\n"); + + mgr =3D devm_fpga_mgr_register(&spi->dev, + "Efinix FPGA Manager", + &efinix_spi_ops, conf); + + conf->bus_locked =3D false; + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct of_device_id efinix_spi_of_match[] =3D { + { .compatible =3D "efinix,trion-spi", }, + { .compatible =3D "efinix,titanium-spi", }, + { .compatible =3D "efinix,topaz-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, efinix_spi_of_match); + +static const struct spi_device_id efinix_ids[] =3D { + { "trion-spi", 0 }, + { "titanium-spi", 0 }, + { "topaz-spi", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + +static struct spi_driver efinix_spi_driver =3D { + .driver =3D { + .name =3D "efinix-spi", + .of_match_table =3D efinix_spi_of_match, + }, + .probe =3D efinix_spi_probe, + .id_table =3D efinix_ids, +}; + +module_spi_driver(efinix_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel "); +MODULE_DESCRIPTION("Efinix FPGA SPI Programming Driver"); --=20 2.43.0