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[2003:eb:5f27:c400:b58a:f32d:fc3c:bd97]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477b82e8ea6sm4909795e9.8.2025.11.19.10.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Nov 2025 10:47:31 -0800 (PST) From: iansdannapel@gmail.com To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, mdf@kernel.org, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, neil.armstrong@linaro.org, mani@kernel.org, kever.yang@rock-chips.com, dev@kael-k.io, iansdannapel@gmail.com Subject: [PATCH v5 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings Date: Wed, 19 Nov 2025 19:47:05 +0100 Message-ID: <20251119184708.566461-3-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251119184708.566461-1-iansdannapel@gmail.com> References: <20251119184708.566461-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ian Dannapel Add device tree bindings documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel --- .../bindings/fpga/efinix,trion-spi.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi= .yaml diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi.yaml b= /Documentation/devicetree/bindings/fpga/efinix,trion-spi.yaml new file mode 100644 index 000000000000..9ac37e5e5094 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitst= reams + through "SPI Passive Mode". + Note: Additional pins hogs for bus width configuration must be set + elsewhere, if necessary. Only bus width 1x serial is supported. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.p= df + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efinix,trion-spi + - efinix,titanium-spi + - efinix,topaz-spi + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible =3D "efinix,trion-spi"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + spi-cpha; + spi-cpol; + reset-gpios =3D <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios =3D <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... --=20 2.43.0