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b=gfQ204axWcaobDcSdI8wYDzyXXF6ZcEm3hTf+Z8PMthU4kqmW3F8tHr149AONxJbG ao4gzWzDUC7E3ZdsKFNlL7B9jYRJgdN8FeFepm5hJTLffe38eizhXjBw3WcB7S/bpj voxLa7mZsjLLxWXUt5Bq4EDiz6ZlHu02RQFArt7QdB2jw/UiF+T0g0hp+KXtBhckZX 4AESnh2Uk24ZmVBiLVw6J/xnx5szQfQ0X7RrvzdPFAgJZdEFgwnqOEW35zIgtXI0Gi r0jG+RKDxXCMUqPF5/oZs9fVdTtN1hZnAZ9qkcTxJPMNToOftbsWNUgUAEgtWhZ593 7tgVdUMuoACXg== Received: from localhost.localdomain (unknown [92.206.121.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: gerddie) by bali.collaboradmins.com (Postfix) with ESMTPSA id 76AAC17E0FFA; Wed, 19 Nov 2025 17:43:45 +0100 (CET) From: gert.wollny@collabora.com To: Christian Gmeiner Cc: Lucas Stach , Russell King , David Airlie , Daniel Vetter , Marek Vasut , etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Gert Wollny , Christian Gmeiner Subject: [PATCH v5 1/5] drm/etnaviv: Add command stream definitions required for a PPU flop reset Date: Wed, 19 Nov 2025 17:45:47 +0100 Message-ID: <20251119164624.9297-2-gert.wollny@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251119164624.9297-1-gert.wollny@collabora.com> References: <20251110144625.18653-1-gert.wollny@collabora.com> <20251119164624.9297-1-gert.wollny@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gert Wollny v2: move some defines that resided in etnaviv_flop_reset.c into the header as well v3: fix spacing/tab stops Signed-off-by: Gert Wollny Reviewed-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/state_3d.xml.h | 97 ++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/state_3d.xml.h b/drivers/gpu/drm/etnav= iv/state_3d.xml.h index ebbd4fcf3..b9e9b78df 100644 --- a/drivers/gpu/drm/etnaviv/state_3d.xml.h +++ b/drivers/gpu/drm/etnaviv/state_3d.xml.h @@ -4,6 +4,103 @@ =20 /* This is a cut-down version of the state_3d.xml.h file */ =20 +#define VIVS_CL_CONFIG 0x00000900 +#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 +#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 +#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS= __SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) +#define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070 +#define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4 +#define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERS= E_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK) +#define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100 +#define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200 +#define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400 +#define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000 +#define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12 +#define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SI= ZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK) +#define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000 +#define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16 +#define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SI= ZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK) +#define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000 +#define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20 +#define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SI= ZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK) + +#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 +#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 +#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS= __SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) + +#define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000 +#define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24 +#define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORD= ER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK) + +#define VIVS_CL_GLOBAL_WORK_OFFSET_X 0x0000092c +#define VIVS_CL_GLOBAL_WORK_OFFSET_Y 0x00000934 +#define VIVS_CL_GLOBAL_WORK_OFFSET_Z 0x0000093c + +#define VIVS_CL_KICKER 0x00000920 +#define VIVS_CL_THREAD_ALLOCATION 0x0000091c +#define VIVS_CL_UNK00924 0x00000924 + +#define VIVS_CL_WORKGROUP_COUNT_X 0x00000940 +#define VIVS_CL_WORKGROUP_COUNT_Y 0x00000944 +#define VIVS_CL_WORKGROUP_COUNT_Z 0x00000948 +#define VIVS_CL_WORKGROUP_SIZE_X 0x0000094c +#define VIVS_CL_WORKGROUP_SIZE_Y 0x00000950 +#define VIVS_CL_WORKGROUP_SIZE_Z 0x00000954 + +#define VIVS_CL_GLOBAL_SCALE_X 0x00000958 +#define VIVS_CL_GLOBAL_SCALE_Y 0x0000095c +#define VIVS_CL_GLOBAL_SCALE_Z 0x00000960 + +#define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8 +#define VIVS_PS_CONTROL_EXT 0x00001030 +#define VIVS_PS_ICACHE_COUNT 0x00001094 +#define VIVS_PS_ICACHE_PREFETCH 0x00001048 + +#define VIVS_PS_INPUT_COUNT 0x00001008 +#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f +#define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT= __SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) + + +#define VIVS_PS_NEWRANGE_LOW 0x0000087c +#define VIVS_PS_NEWRANGE_HIGH 0x00001090 +#define VIVS_PS_SAMPLER_BASE 0x00001058 + +#define VIVS_PS_UNIFORM_BASE 0x00001024 +#define VIVS_PS_INST_ADDR 0x00001028 + +#define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_= REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMP= S__MASK) + +#define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0)) +#define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 +#define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004 + +#define VIVS_SH_CONFIG 0x00015600 +#define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 + +#define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0)) +#define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004 +#define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800 + +#define VIVS_VS_HALTI5_UNK008A0 0x000008a0 +#define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f +#define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0 +#define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A= __SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK) + + +#define VIVS_VS_ICACHE_CONTROL 0x00000868 +#define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001 + +#define VIVS_VS_ICACHE_INVALIDATE 0x000008b0 + +#define VIVS_VS_OUTPUT_COUNT 0x00000804 +#define VIVS_VS_OUTPUT_COUNT_COUNT__MASK 0x000000ff +#define VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_VS_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_OUTPUT_COUNT_COU= NT__SHIFT) & VIVS_VS_OUTPUT_COUNT_COUNT__MASK) + #define VIVS_TS_FLUSH_CACHE 0x00001650 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 =20 --=20 2.51.0