From nobody Tue Dec 2 02:32:03 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8D73022B8B6; Wed, 19 Nov 2025 16:16:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763568969; cv=none; b=L5nJpEhSrSVFSKNnFPikS1CfOV/qZMzxo3zi6aZ74eio9P8vrmif3dJZNT9kLZKDBuuWYmRDTgxVBzOm2fSWz8YTeSVTQWV5K8IJ9/uNPXj31zYyRCu42ygfo6sP6u+yYTY2WNUBppy1K+cHaquTVoAZyCCUD/HqGQIDGy4TrGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763568969; c=relaxed/simple; bh=td1FXpsyeOo0z8n6/jZTxrVUj9CyEe4ZtIsoF4TbqWI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GHSSULEqTsM9MzpLChJuKS2rZBgPH+2Qw9kURqdgAb8quvrF7YyDFb8wnNwfEbofQLco6se/Ob78cUBYSnt3LVHflmRVXAT/BQAS8DAy9zDlbLrmldOFWEcMMe/bXAPvhs1Z2myAaogsYh0RwRyIGd2DT33LnjrdrONv/3ZfAXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: YgnUu6ZITZ+OHFVKuMegrQ== X-CSE-MsgGUID: dlUMYyJYSC+Cp5wQUAm6RA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 20 Nov 2025 01:16:03 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.87]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 481DE406C471; Thu, 20 Nov 2025 01:15:59 +0900 (JST) From: Cosmin Tanislav To: Fabrizio Castro , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel Cc: linux-spi@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v4 08/13] spi: rzv2h-rspi: add support for variable transfer clock Date: Wed, 19 Nov 2025 18:14:29 +0200 Message-ID: <20251119161434.595677-9-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251119161434.595677-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251119161434.595677-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a more complicated clocking setup for the SPI transfer clock than RZ/V2H, as the clock from which it is generated supports multiple dividers. To prepare for adding support for these SoCs, do the following changes. Use the minimum frequency of SPI clock to calculate the SPI controller's min_speed_hz, and the maximum frequency to calculate max_speed_hz. Apply the clock rate found by the .find_tclk_rate() to the found clock. Signed-off-by: Cosmin Tanislav --- V4: * no changes V3: * no changes V2: * fix missing unwind goto quit_resets drivers/spi/spi-rzv2h-rspi.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c index e9d8ee919261..be45269e8853 100644 --- a/drivers/spi/spi-rzv2h-rspi.c +++ b/drivers/spi/spi-rzv2h-rspi.c @@ -308,6 +308,7 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_pri= v *rspi, u32 hz) struct rzv2h_rspi_best_clock best_clock =3D { .error =3D ULONG_MAX, }; + int ret; =20 rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, RSPI_SPBR_SPR_MAX, &best_clock); @@ -323,6 +324,10 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_pr= iv *rspi, u32 hz) if (!best_clock.clk_rate) return -EINVAL; =20 + ret =3D clk_set_rate(best_clock.clk, best_clock.clk_rate); + if (ret) + return 0; + rspi->use_pclk =3D best_clock.clk =3D=3D rspi->pclk; rspi->spr =3D best_clock.spr; rspi->brdv =3D best_clock.brdv; @@ -426,8 +431,8 @@ static int rzv2h_rspi_probe(struct platform_device *pde= v) struct device *dev =3D &pdev->dev; struct rzv2h_rspi_priv *rspi; struct clk_bulk_data *clks; - unsigned long tclk_rate; int irq_rx, ret, i; + long tclk_rate; =20 controller =3D devm_spi_alloc_host(dev, sizeof(*rspi)); if (!controller) @@ -460,8 +465,6 @@ static int rzv2h_rspi_probe(struct platform_device *pde= v) if (!rspi->tclk) return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n"); =20 - tclk_rate =3D clk_get_rate(rspi->tclk); - rspi->resets[0].id =3D "presetn"; rspi->resets[1].id =3D "tresetn"; ret =3D devm_reset_control_bulk_get_optional_exclusive(dev, RSPI_RESET_NU= M, @@ -493,9 +496,23 @@ static int rzv2h_rspi_probe(struct platform_device *pd= ev) controller->unprepare_message =3D rzv2h_rspi_unprepare_message; controller->num_chipselect =3D 4; controller->transfer_one =3D rzv2h_rspi_transfer_one; + + tclk_rate =3D clk_round_rate(rspi->tclk, 0); + if (tclk_rate < 0) { + ret =3D tclk_rate; + goto quit_resets; + } + controller->min_speed_hz =3D rzv2h_rspi_calc_bitrate(tclk_rate, RSPI_SPBR_SPR_MAX, RSPI_SPCMD_BRDV_MAX); + + tclk_rate =3D clk_round_rate(rspi->tclk, ULONG_MAX); + if (tclk_rate < 0) { + ret =3D tclk_rate; + goto quit_resets; + } + controller->max_speed_hz =3D rzv2h_rspi_calc_bitrate(tclk_rate, RSPI_SPBR_SPR_MIN, RSPI_SPCMD_BRDV_MIN); --=20 2.52.0