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Wed, 19 Nov 2025 11:47:27 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5AJBlQl2026192 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Nov 2025 11:47:26 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 19 Nov 2025 03:47:22 -0800 From: Md Sadre Alam To: , , , , , , CC: Subject: [PATCH v5] mmc: sdhci-msm: Enable ICE for CQE-capable controllers with non-CQE cards Date: Wed, 19 Nov 2025 17:16:53 +0530 Message-ID: <20251119114653.751992-1-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LNJkxqjwwuy5VY0D3b0ontuoojNjXHoy X-Authority-Analysis: v=2.4 cv=ZKHaWH7b c=1 sm=1 tr=0 ts=691dae4f cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=QyXUC8HyAAAA:8 a=raka8JUDq7p2293nCkMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE5MDA5MyBTYWx0ZWRfX/VfKmYOuFhoi NekxdKmA8KaA2FC7aTs/cvYehLVOlQraOkaOwK+1qFCk0KM5kfyXUQMY9i1zC1Qv0qDcUCTu1CD zRlokWf6aumhxXf+rH7vceu3G8t8o7rFIXZpWn8F+Utp10CfDQ9Zodow50+HpOIAIu0f9c71sF9 q/CAr4/ViGGpm3lngb9cVeAhXnGdWG/5B+ZsRGkP1Om3z1tlg4YShcM/dI+K0Ti+Q2tDKs03po6 wVo9AHlkCW64yNu5Dkh7FiUppniNVfs1JZhdd98GIkqFRU5495hAwbYzpaWi285gnbtIR9pFbLt y0vWpCIhsBI0c5Lhth/PL4dH/odxqwditWtr3ogS3VL3dmhcGbzDIUhXqN5ZgCUz9+m83uBZoMC Q4RFvuy5ZL3/o8ljBwqCTp6TBsi2mA== X-Proofpoint-ORIG-GUID: LNJkxqjwwuy5VY0D3b0ontuoojNjXHoy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-19_03,2025-11-18_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511190093 Enable Inline Crypto Engine (ICE) support for CQE-capable sdhci-msm controllers when used with eMMC cards that do not support CQE. This addresses the scenario where: - The host controller supports CQE (and has CQHCI crypto infrastructure) - The eMMC card does not support CQE - Standard (non-CMDQ) requests need crypto support This allows hardware-accelerated encryption and decryption for standard requests on CQE-capable hardware by utilizing the existing CQHCI crypto register space even when CQE functionality is not available due to card limitations. The implementation: - Adds ICE register definitions for non-CQE crypto configuration - Implements per-request crypto setup via sdhci_msm_ice_cfg() - Hooks into the request path via mmc_host_ops.request for non-CQE requests - Uses CQHCI register space (NONCQ_CRYPTO_PARM/DUN) for crypto configuration With this, CQE-capable controllers can benefit from inline encryption when paired with non-CQE cards, improving performance for encrypted I/O while maintaining compatibility with existing CQE crypto support. Signed-off-by: Md Sadre Alam Acked-by: Adrian Hunter --- Change in [v5] * Removed unused variable * Added proper comment for sdhci_msm_request() * Removed sdhci_msm_ice_enable(); it is already invoked during resume Change in [v4] * Moved ICE initialization for non cmdq into sdhci_msm_ice_cfg() and made it conditional on mrq->crypto_ctx to enable lazy setup. * Added msm_host->ice_init_done guard to prevent redundant initialization. * Updated commit message Change in [v3] * Refactored logic to use separate code paths for crypto_ctx !=3D NULL and crypto_ctx =3D=3D NULL to improve readability. * Renamed bypass to crypto_enable to align with bitfield semantics. * Removed slot variable * Added ICE initialization sequence for non-CMDQ eMMC devices before __sdhci_add_host() Change in [v2] * Moved NONCQ_CRYPTO_PARM and NONCQ_CRYPTO_DUN register definitions into sdhci-msm.c * Introduced use of GENMASK() and FIELD_PREP() macros for cleaner and more maintainable bitfield handling in ICE configuration. * Removed redundant if (!mrq || !cq_host) check from sdhci_msm_ice_cfg() as both are guaranteed to be valid in the current call path. * Added assignment of host->mmc_host_ops.request =3D sdhci_msm_request; to integrate ICE configuration into the standard request path for non-CMDQ eMMC devices. * Removed sdhci_crypto_cfg() from sdhci.c and its invocation in sdhci_reque= st() Change in [v1] * Added initial support for Inline Crypto Engine (ICE) on non-CMDQ eMMC devices. drivers/mmc/host/sdhci-msm.c | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4e5edbf2fc9b..69c67242519c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -157,6 +157,18 @@ #define CQHCI_VENDOR_CFG1 0xA00 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) =20 +/* non command queue crypto enable register*/ +#define NONCQ_CRYPTO_PARM 0x70 +#define NONCQ_CRYPTO_DUN 0x74 + +#define DISABLE_CRYPTO BIT(15) +#define CRYPTO_GENERAL_ENABLE BIT(1) +#define HC_VENDOR_SPECIFIC_FUNC4 0x260 +#define ICE_HCI_SUPPORT BIT(28) + +#define ICE_HCI_PARAM_CCI GENMASK(7, 0) +#define ICE_HCI_PARAM_CE GENMASK(8, 8) + struct sdhci_msm_offset { u32 core_hc_mode; u32 core_mci_data_cnt; @@ -300,6 +312,7 @@ struct sdhci_msm_host { u32 dll_config; u32 ddr_config; bool vqmmc_enabled; + bool ice_init_done; }; =20 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_h= ost *host) @@ -2009,6 +2022,91 @@ static int sdhci_msm_ice_keyslot_evict(struct blk_cr= ypto_profile *profile, return qcom_ice_evict_key(msm_host->ice, slot); } =20 +static void sdhci_msm_non_cqe_ice_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct mmc_host *mmc =3D msm_host->mmc; + struct cqhci_host *cq_host =3D mmc->cqe_private; + u32 config; + u32 ice_cap; + + config =3D sdhci_readl(host, HC_VENDOR_SPECIFIC_FUNC4); + config &=3D ~DISABLE_CRYPTO; + sdhci_writel(host, config, HC_VENDOR_SPECIFIC_FUNC4); + ice_cap =3D cqhci_readl(cq_host, CQHCI_CAP); + if (ice_cap & ICE_HCI_SUPPORT) { + config =3D cqhci_readl(cq_host, CQHCI_CFG); + config |=3D CRYPTO_GENERAL_ENABLE; + cqhci_writel(cq_host, config, CQHCI_CFG); + } +} + +static int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *= mrq) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct mmc_host *mmc =3D msm_host->mmc; + struct cqhci_host *cq_host =3D mmc->cqe_private; + unsigned int crypto_params =3D 0; + int key_index; + bool crypto_enable; + u64 dun =3D 0; + + if (mrq->crypto_ctx) { + if (!msm_host->ice_init_done) { + sdhci_msm_non_cqe_ice_init(host); + msm_host->ice_init_done =3D true; + } + + crypto_enable =3D true; + dun =3D mrq->crypto_ctx->bc_dun[0]; + key_index =3D mrq->crypto_key_slot; + crypto_params =3D FIELD_PREP(ICE_HCI_PARAM_CE, crypto_enable) | + FIELD_PREP(ICE_HCI_PARAM_CCI, key_index); + + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); + cqhci_writel(cq_host, lower_32_bits(dun), NONCQ_CRYPTO_DUN); + } else { + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); + } + + /* Ensure crypto configuration is written before proceeding */ + wmb(); + + return 0; +} + +/* + * sdhci_msm_request - Handle non-CQE MMC requests with crypto support + * @mmc: MMC host + * @mrq: MMC request + * + * This function is called for non-CQE requests only. The MMC block layer + * routes requests as follows: + * + * if (host->cqe_enabled) + * ret =3D mmc_blk_cqe_issue_rw_rq(mq, req); // =E2=86=92 cqhci_reque= st() + * else + * ret =3D mmc_blk_mq_issue_rw_rq(mq, req); // =E2=86=92 sdhci_msm_r= equest() + * + * For CQE requests, crypto is handled in cqhci_request() in + * drivers/mmc/host/cqhci-core.c using the existing CQE crypto infrastruct= ure. + * + * For non-CQE requests, this function provides crypto support by configur= ing + * the ICE (Inline Crypto Engine) registers before passing the request to + * the standard SDHCI request handler. + */ +static void sdhci_msm_request(struct mmc_host *mmc, struct mmc_request *mr= q) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + if (mmc->caps2 & MMC_CAP2_CRYPTO) + sdhci_msm_ice_cfg(host, mrq); + + sdhci_request(mmc, mrq); +} + static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops =3D { .keyslot_program =3D sdhci_msm_ice_keyslot_program, .keyslot_evict =3D sdhci_msm_ice_keyslot_evict, @@ -2759,6 +2857,9 @@ static int sdhci_msm_probe(struct platform_device *pd= ev) =20 msm_host->mmc->caps |=3D MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; =20 +#ifdef CONFIG_MMC_CRYPTO + host->mmc_host_ops.request =3D sdhci_msm_request; +#endif /* Set the timeout value to max possible */ host->max_timeout_count =3D 0xF; =20 --=20 2.34.1