From nobody Tue Dec 2 02:42:58 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ED9D30E0D9 for ; Tue, 18 Nov 2025 22:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763504614; cv=none; b=qTAH4+Nrl9668roNirsjoAwO40W6sn4jxMTwJgunKU21BXCCbjahpPMpHMqYV7IvjKYDg0QATqyJNjTH7TvwKpd/BmkcUa6viPMXRFXqk7UXWuWe5pfK+zKHR27+/s1s8UoD4R8Fp7O4GXgdYOVknlN4JeseiO0wZkynwwRsqWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763504614; c=relaxed/simple; bh=gkOFf1GrseR4lyx+m5A0i8MM9/uAsLY1WwIpa5M2Cos=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=fj9fzgohwPO3uE7Tu+UyJ9CvghPMslysmaSf231jH87bno4sgQkF0rY4A+uUbopI6Knwv/C4N/PU5qOUzAASxBx7MNqXViLdLq6hBpebC4kZxqIVvJj/BF9Z+TXlz05dSllIltRSMcM07ZGcV/qm7O96drk9yPzw2KVSF5XSYSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=eRzBtuA2; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="eRzBtuA2" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-29845b18d1aso101843035ad.1 for ; Tue, 18 Nov 2025 14:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1763504613; x=1764109413; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=EoozWi2o0AP/cWaOLQLnk9g/zPkjhcGQ8ZSDyR31DRY=; b=eRzBtuA2psnUx1ZmHHnHjodKCcsmSe+Lh0yyURFF7Suo9lkxcjIoIFhCQm+k5IHf5u fePC/ykirHpsd7Or9Hwb+ZDZJa9pni7C9YvKMFgkW/+2woGs8rRRZgi8LCO+qGQVhkbV 5RPTU9ttBIQfrLMz97kddttIzP+gqUtj9N5Wk7DM9B+whEZb8rs4fGNW/y9UEyzFRGjw cCsV6aqs98r3lc9sLDzaVfJzc+ml0XbghzQJQ/2ERNK8oVANBqA8XgEHNTYDll59fUVO l77p0dIE+tW98tufK8Ka9ExBoLXc8Ruzs7uxSTXM5fKl75GDlC1mNxpiUQcg4M15yOoJ bflg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763504613; x=1764109413; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=EoozWi2o0AP/cWaOLQLnk9g/zPkjhcGQ8ZSDyR31DRY=; b=TIHVQEnGwurKP4JZwiCfFo798tRyywTGpqqmDVhzytxpXvQ1niJBxVdxQOnKLBTaW+ +pV9ZLWu+nSrWwQonearT17QjChmd0yE9Z1mRkFyxlSPPBjDW43KwJpVjFJto5eVfNUb mqb0GoRTTfW+v2hZe1gICwA35GDghB6VPT2dv/v8oHVlCzEwXtuwnMEK0U30OtjWZHC4 OMKZamYC1QFnkSf1yFztvU4cuLlPfIg10srO4YSDdXXYanm9bAcxcHTflWNFQiG9lzR3 Cyp4lk8YBBm3XHFrWJbTs4ltD91HURwLKANEAy0PjFRC5Csrez1vFrUG3QRX/bRNx8Al +YiA== X-Forwarded-Encrypted: i=1; AJvYcCUgSCC0B8elJahPFNBs1nFdSS3nQoT6qsu9MtF+M5Dx5e4XJrIEKM+qzdxHEvVpmk2kBda8yzvXW1PnfFA=@vger.kernel.org X-Gm-Message-State: AOJu0YzFIWGY3Xl3OvorNs0rJAy905+5NndwttljZ261KqA58V/sWljW D1+vATLN+xMlN2BImf6R8DyM/Yg0EY/SmA7mOMSn//aLyO5tnxEEeJcU42Mmrbj5Fk5MctvM4HQ z8Ebhtg== X-Google-Smtp-Source: AGHT+IGBpr2o1tN68nNDCesi9FJp0PssJ7eoZdkj6lok22m/Q8r6RJE+NAbbob2Q0BzsFgmO0oAokh9ajl8= X-Received: from plbjc5.prod.google.com ([2002:a17:903:25c5:b0:295:68e0:66ed]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:11c6:b0:297:e1f5:191b with SMTP id d9443c01a7336-2986a6abf3cmr224167275ad.11.1763504612758; Tue, 18 Nov 2025 14:23:32 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 18 Nov 2025 14:23:25 -0800 In-Reply-To: <20251118222328.2265758-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251118222328.2265758-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.rc1.455.g30608eb744-goog Message-ID: <20251118222328.2265758-2-seanjc@google.com> Subject: [PATCH v2 1/4] KVM: SVM: Handle #MCs in guest outside of fastpath From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , "Kirill A. Shutemov" Cc: kvm@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Rick Edgecombe , Jon Kohler , Tony Lindgren Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle Machine Checks (#MC) that happen in the guest (by forwarding them to the host) outside of KVM's fastpath so that as much host state as possible is re-loaded before invoking the kernel's #MC handler. The only requirement is that KVM invokes the #MC handler before enabling IRQs (and even that could _probably_ be relaxed to handling #MCs before enabling preemption). Waiting to handle #MCs until "more" host state is loaded hardens KVM against flaws in the #MC handler, which has historically been quite brittle. E.g. prior to commit 5567d11c21a1 ("x86/mce: Send #MC singal from task work"), the #MC code could trigger a schedule() with IRQs and preemption disabled. That led to a KVM hack-a-fix in commit 1811d979c716 ("x86/kvm: move kvm_load/put_guest_xcr0 into atomic context"). Note, except for #MCs on VM-Enter, VMX already handles #MCs outside of the fastpath. Reviewed-by: Rick Edgecombe Reviewed-by: Jon Kohler Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9aac0eb3a490..bf34378ebe2d 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4321,14 +4321,6 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm= _vcpu *vcpu, u64 run_flags) =20 vcpu->arch.regs_avail &=3D ~SVM_REGS_LAZY_LOAD_SET; =20 - /* - * We need to handle MC intercepts here before the vcpu has a chance to - * change the physical cpu - */ - if (unlikely(svm->vmcb->control.exit_code =3D=3D - SVM_EXIT_EXCP_BASE + MC_VECTOR)) - svm_handle_mce(vcpu); - trace_kvm_exit(vcpu, KVM_ISA_SVM); =20 svm_complete_interrupts(vcpu); @@ -4631,8 +4623,16 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu, =20 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) { - if (to_svm(vcpu)->vmcb->control.exit_code =3D=3D SVM_EXIT_INTR) + switch (to_svm(vcpu)->vmcb->control.exit_code) { + case SVM_EXIT_EXCP_BASE + MC_VECTOR: + svm_handle_mce(vcpu); + break; + case SVM_EXIT_INTR: vcpu->arch.at_instruction_boundary =3D true; + break; + default: + break; + } } =20 static void svm_setup_mce(struct kvm_vcpu *vcpu) --=20 2.52.0.rc1.455.g30608eb744-goog