From nobody Tue Dec 2 02:34:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7404C2E8E08; Tue, 18 Nov 2025 19:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763495018; cv=none; b=IAlJbqzGtHPH22rFWkHKhS2FO5bNeODBUDeObpdvljuG/hpFxtewwD1C6R0K/oDjNBINtsokq5Pe+ARZyju7sBTq3iZdzrsoacQvtOJep8fXXptwlnxbXGrJpNFo//EnKqMVpxYGUn57BtUNzLVNIaaBaFNt5mjk82AQ19gvEcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763495018; c=relaxed/simple; bh=BZKAUD2jI/0P2DXfhI1kWtAYI6dS9xMGH214FHWrl4k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M6Tx3WUtHuuwBNiLuiIKcWvqyCEI9A67lmSrqZgHWdeosFzgMRVzj//3Kd0VgUTH0OFOPNeAOj/aD/phcLzgF06fOmYcxeKYgc46vQtYpH4/2XiZvHr8POi9X8ik9miHsdLFzOsyjk0fcUCjucczye/a/PhmbR4n5Wppw7lZtVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y/xvceZz; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y/xvceZz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763495016; x=1795031016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BZKAUD2jI/0P2DXfhI1kWtAYI6dS9xMGH214FHWrl4k=; b=Y/xvceZzhqfSzlpU/4tXSk2VDhskf6P1MmHGkzmxgE0dAc+14bXntv+j g/0nLObI/r3Kp89YJM/vY92v/hFdYWVu8aNJvssNMsmysP8GBgdBQhVuF PfE/LFbiM9IcDnHHZDVRCDwsAUCq0uhKDWbY2YoXiqGFRT4THOhs2qPHr u4QWfv5pC/XmUfe7D4P1FjVYEWzh0Nq0uvGCHAzow9qqg2jl31ulce6N+ TTQ8PCUqeQD7ab74ttAtCTZVq1mouimsgNyurZaf898irx6ZV+cEiSDzY VPA5ELNxWClb15c7ODswi7UdkKBEyiJhCXgLvdaq4/DmqUczNftqZOeqf Q==; X-CSE-ConnectionGUID: HWVmaeuISIaL1YpK3cWLhg== X-CSE-MsgGUID: 0u2kfoluTJi+xDhFTYbL9w== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76138688" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76138688" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:36 -0800 X-CSE-ConnectionGUID: QZQLcLFfTka0h/lTc4v4iA== X-CSE-MsgGUID: PzsnsNtiSN+KoU+hJkPyNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="228188890" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.246.148]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:32 -0800 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M . De Francesco" Subject: [PATCH 1/4 v6] cxl/core: Change match_*_by_range() signatures Date: Tue, 18 Nov 2025 20:43:03 +0100 Message-ID: <20251118194321.1773484-2-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> References: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace struct range parameter with struct cxl_endpoint_decoder of which range is a member in the match_*_by_range() functions and rename them according to their semantics. This is in preparation for expanding these helpers to perform arch specific Root Decoders and Region matching with Switch and Endpoint Decoders. Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Reviewed-by: Dave Jiang Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Signed-off-by: Fabio M. De Francesco --- drivers/cxl/core/region.c | 62 ++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 2cf5b29cefd2..315481444eb0 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1808,27 +1808,29 @@ static int cmp_interleave_pos(const void *a, const = void *b) return cxled_a->pos - cxled_b->pos; } =20 -static int match_switch_decoder_by_range(struct device *dev, - const void *data) +static int match_cxlsd_to_cxled_by_range(struct device *dev, const void *d= ata) { + const struct cxl_endpoint_decoder *cxled =3D data; struct cxl_switch_decoder *cxlsd; - const struct range *r1, *r2 =3D data; - + const struct range *r1, *r2; =20 if (!is_switch_decoder(dev)) return 0; =20 cxlsd =3D to_cxl_switch_decoder(dev); r1 =3D &cxlsd->cxld.hpa_range; + r2 =3D &cxled->cxld.hpa_range; =20 if (is_root_decoder(dev)) return range_contains(r1, r2); return (r1->start =3D=3D r2->start && r1->end =3D=3D r2->end); } =20 -static int find_pos_and_ways(struct cxl_port *port, struct range *range, - int *pos, int *ways) +static int find_pos_and_ways(struct cxl_port *port, + struct cxl_endpoint_decoder *cxled, int *pos, + int *ways) { + struct range *range =3D &cxled->cxld.hpa_range; struct cxl_switch_decoder *cxlsd; struct cxl_port *parent; struct device *dev; @@ -1838,8 +1840,8 @@ static int find_pos_and_ways(struct cxl_port *port, s= truct range *range, if (!parent) return rc; =20 - dev =3D device_find_child(&parent->dev, range, - match_switch_decoder_by_range); + dev =3D device_find_child(&parent->dev, cxled, + match_cxlsd_to_cxled_by_range); if (!dev) { dev_err(port->uport_dev, "failed to find decoder mapping %#llx-%#llx\n", @@ -1925,7 +1927,7 @@ static int cxl_calc_interleave_pos(struct cxl_endpoin= t_decoder *cxled) if (is_cxl_root(iter)) break; =20 - rc =3D find_pos_and_ways(iter, range, &parent_pos, &parent_ways); + rc =3D find_pos_and_ways(iter, cxled, &parent_pos, &parent_ways); if (rc) return rc; =20 @@ -3457,24 +3459,30 @@ static int devm_cxl_add_dax_region(struct cxl_regio= n *cxlr) return rc; } =20 -static int match_decoder_by_range(struct device *dev, const void *data) +static int match_cxlrd_to_cxled_by_range(struct device *dev, const void *d= ata) { - const struct range *r1, *r2 =3D data; - struct cxl_decoder *cxld; + const struct cxl_endpoint_decoder *cxled =3D data; + struct cxl_root_decoder *cxlrd; + const struct range *r1, *r2; =20 - if (!is_switch_decoder(dev)) + if (!is_root_decoder(dev)) return 0; =20 - cxld =3D to_cxl_decoder(dev); - r1 =3D &cxld->hpa_range; + cxlrd =3D to_cxl_root_decoder(dev); + r1 =3D &cxlrd->cxlsd.cxld.hpa_range; + r2 =3D &cxled->cxld.hpa_range; + return range_contains(r1, r2); } =20 static struct cxl_decoder * -cxl_port_find_switch_decoder(struct cxl_port *port, struct range *hpa) +cxl_port_find_root_decoder(struct cxl_port *port, + struct cxl_endpoint_decoder *cxled) { - struct device *cxld_dev =3D device_find_child(&port->dev, hpa, - match_decoder_by_range); + struct device *cxld_dev; + + cxld_dev =3D device_find_child(&port->dev, cxled, + match_cxlrd_to_cxled_by_range); =20 return cxld_dev ? to_cxl_decoder(cxld_dev) : NULL; } @@ -3486,9 +3494,8 @@ cxl_find_root_decoder(struct cxl_endpoint_decoder *cx= led) struct cxl_port *port =3D cxled_to_port(cxled); struct cxl_root *cxl_root __free(put_cxl_root) =3D find_cxl_root(port); struct cxl_decoder *root, *cxld =3D &cxled->cxld; - struct range *hpa =3D &cxld->hpa_range; =20 - root =3D cxl_port_find_switch_decoder(&cxl_root->port, hpa); + root =3D cxl_port_find_root_decoder(&cxl_root->port, cxled); if (!root) { dev_err(cxlmd->dev.parent, "%s:%s no CXL window for range %#llx:%#llx\n", @@ -3500,11 +3507,12 @@ cxl_find_root_decoder(struct cxl_endpoint_decoder *= cxled) return to_cxl_root_decoder(&root->dev); } =20 -static int match_region_by_range(struct device *dev, const void *data) +static int match_region_to_cxled_by_range(struct device *dev, const void *= data) { + const struct cxl_endpoint_decoder *cxled =3D data; + const struct range *r =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; struct cxl_region *cxlr; - const struct range *r =3D data; =20 if (!is_cxl_region(dev)) return 0; @@ -3663,12 +3671,13 @@ static struct cxl_region *construct_region(struct c= xl_root_decoder *cxlrd, } =20 static struct cxl_region * -cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *hpa) +cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder *cxled) { struct device *region_dev; =20 - region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, hpa, - match_region_by_range); + region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, cxled, + match_region_to_cxled_by_range); if (!region_dev) return NULL; =20 @@ -3677,7 +3686,6 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxl= rd, struct range *hpa) =20 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) { - struct range *hpa =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; bool attach =3D false; int rc; @@ -3693,7 +3701,7 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *cx= led) */ mutex_lock(&cxlrd->range_lock); struct cxl_region *cxlr __free(put_cxl_region) =3D - cxl_find_region_by_range(cxlrd, hpa); + cxl_find_region_by_range(cxlrd, cxled); if (!cxlr) cxlr =3D construct_region(cxlrd, cxled); mutex_unlock(&cxlrd->range_lock); --=20 2.51.1 From nobody Tue Dec 2 02:34:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91902EDD6F; Tue, 18 Nov 2025 19:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763495023; cv=none; b=nEL6BhIQbO+5qYJxTrnXr+qku/sYGpTUCnCazZd3Bm3Tkp2xP9aC64Lf7XHJ2jyFaSyqpNFeYpuBgO2otNNIIpYTqCQZTNvB2LPj4gUoGir7XmfW1knfsvVhFURlW0ANE7d35kgGKwslBTo6RAiQpqs1T9KAPBLrgznJl5yyejQ= ARC-Message-Signature: i=1; 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d="scan'208";a="228188893" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.246.148]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:36 -0800 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M . De Francesco" Subject: [PATCH 2/4 v6] cxl/core: Add helpers to detect Low Memory Holes on x86 Date: Tue, 18 Nov 2025 20:43:04 +0100 Message-ID: <20251118194321.1773484-3-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> References: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On a x86 platform with a low memory hole (LMH), the BIOS may publish CFMWS that describes a system physical address (SPA) range that typically is only a subset of the corresponding CXL intermediate switch and endpoint decoder's host physical address (HPA) ranges. The CFMWS range never intersects the LHM and so the driver instantiates a root decoder whose HPA range size doesn't fully contain the matching switch and endpoint decoders' HPA ranges.[1] To construct regions and attach decoders, the driver needs to match root decoders and regions with endpoint decoders. The process fails and returns errors because the driver is not designed to deal with SPA ranges which are smaller than the corresponding hardware decoders HPA ranges. Introduce two functions that indirectly detect the presence of x86 LMH and allow the matching between a root decoder or an already constructed region with a corresponding intermediate switch or endpoint decoder to enable the construction of a region and the subsequent attachment of the same decoders to that region. These functions return true when SPA/HPA misalignments due to LMH's are detected under specific conditions: - Both the SPA and HPA ranges must start at LMH_CFMWS_RANGE_START (i.e., 0x0 on x86 with LMH's). - The SPA range's size is less than HPA's. - The SPA range's size is less than 4G. - The HPA range's size is aligned to the NIW * 256M rule. Also introduce a function that adjusts the range end of a region to be constructed and the DPA range's end of the endpoint decoders that will be later attached to that region. [1] commit c5dca38633da ("cxl: Documentation/driver-api/cxl: Describe the x= 86 Low Memory Hole solution") Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Reviewed-by: Gregory Price Signed-off-by: Fabio M. De Francesco Reviewed-by: Dave Jiang --- drivers/cxl/Kconfig | 11 +++ drivers/cxl/core/Makefile | 1 + drivers/cxl/core/platform_quirks.c | 103 +++++++++++++++++++++++++++++ drivers/cxl/core/platform_quirks.h | 36 ++++++++++ 4 files changed, 151 insertions(+) create mode 100644 drivers/cxl/core/platform_quirks.c create mode 100644 drivers/cxl/core/platform_quirks.h diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..5ab8d5c23187 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -211,6 +211,17 @@ config CXL_REGION =20 If unsure say 'y' =20 +config CXL_PLATFORM_QUIRKS + bool "CXL: Region Platform Quirks" + depends on CXL_REGION + help + Enable support for the following platform quirks: + + - Region creation / Endpoint Decoders attach in x86 with Low + Memory Holes (Documentation/driver-api/cxl/conventions.rst). + + If unsure say 'y' + config CXL_REGION_INVALIDATION_TEST bool "CXL: Region Cache Management Bypass (TEST)" depends on CXL_REGION diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..1684e46b8709 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -17,6 +17,7 @@ cxl_core-y +=3D cdat.o cxl_core-y +=3D ras.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o +cxl_core-$(CONFIG_CXL_PLATFORM_QUIRKS) +=3D platform_quirks.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o diff --git a/drivers/cxl/core/platform_quirks.c b/drivers/cxl/core/platform= _quirks.c new file mode 100644 index 000000000000..be57b9666c9b --- /dev/null +++ b/drivers/cxl/core/platform_quirks.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2025 Intel Corporation + +#include +#include "platform_quirks.h" +#include "cxlmem.h" +#include "core.h" + +/* Start of CFMWS range that end before x86 Low Memory Holes */ +#define LMH_CFMWS_RANGE_START 0x0ULL + +/** + * platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and + * Endpoint Decoders. It allows matching on platforms with LMH's. + * @cxlrd: The Root Decoder against which @cxled is tested for matching. + * @cxled: The Endpoint Decoder to be tested for matching @cxlrd. + * + * platform_cxlrd_matches_cxled() is typically called from the + * match_*_by_range() functions in region.c. It checks if an endpoint deco= der + * matches a given root decoder and returns true to allow the driver to su= cceed + * in the construction of regions where it would otherwise fail for the pr= esence + * of a Low Memory Hole (see Documentation/driver-api/cxl/conventions.rst). + * + * In x86 platforms with LMH's, the CFMWS ranges never intersect the LMH, = the + * endpoint decoder's HPA range size is always guaranteed aligned to NIW*2= 56MB + * and also typically larger than the matching root decoder's, and the root + * decoder's range end is at an address that is necessarily less than SZ_4G + * (i.e., the Hole is in Low Memory - this function doesn't deal with other + * kinds of holes). + * + * Return: true if an endpoint matches a root decoder, else false. + */ +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + const struct range *rd_r, *sd_r; + int align; + + rd_r =3D &cxlrd->cxlsd.cxld.hpa_range; + sd_r =3D &cxled->cxld.hpa_range; + align =3D cxled->cxld.interleave_ways * SZ_256M; + + return rd_r->start =3D=3D LMH_CFMWS_RANGE_START && + rd_r->start =3D=3D sd_r->start && + rd_r->end < sd_r->end && + rd_r->end < (LMH_CFMWS_RANGE_START + SZ_4G) && + IS_ALIGNED(range_len(sd_r), align); +} + +/** + * platform_region_matches_cxld() - Platform quirk to match a CXL Region a= nd a + * Switch or Endpoint Decoder. It allows matching on platforms with LMH's. + * @p: Region Params against which @cxled is matched. + * @cxld: Switch or Endpoint Decoder to be tested for matching @p. + * + * Similar to platform_cxlrd_matches_cxled(), it matches regions and + * decoders on platforms with LMH's. + * + * Return: true if a Decoder matches a Region, else false. + */ +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + const struct range *r =3D &cxld->hpa_range; + const struct resource *res =3D p->res; + int align =3D cxld->interleave_ways * SZ_256M; + + return res->start =3D=3D LMH_CFMWS_RANGE_START && + res->start =3D=3D r->start && + res->end < r->end && + res->end < (LMH_CFMWS_RANGE_START + SZ_4G) && + IS_ALIGNED(range_len(r), align); +} + +void platform_adjust_resources(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd, + const struct device *region_dev) +{ + struct resource dpa_res_orig =3D *cxled->dpa_res; + u64 slice; + + if (!platform_cxlrd_matches_cxled(cxlrd, cxled)) + return; + + guard(rwsem_write)(&cxl_rwsem.dpa); + + /* Region resource will need a trim at first endpoint attach only */ + if (res && res->end !=3D cxlrd->res->end) { + dev_info(region_dev, + "LMH Low memory hole trims region resource %pr to %pr)\n", + res, cxlrd->res); + res->end =3D cxlrd->res->end; + } + + /* Adjust the endpoint decoder DPA resource end */ + slice =3D div_u64(resource_size(cxlrd->res), cxled->cxld.interleave_ways); + cxled->dpa_res->end =3D cxled->dpa_res->start + slice - 1; + + dev_info(&cxled->cxld.dev, + "LMH Low memory hole trims DPA resource %pr to %pr)\n", + &dpa_res_orig, cxled->dpa_res); +} diff --git a/drivers/cxl/core/platform_quirks.h b/drivers/cxl/core/platform= _quirks.h new file mode 100644 index 000000000000..fce376232c16 --- /dev/null +++ b/drivers/cxl/core/platform_quirks.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2025 Intel Corporation */ + +#include "cxl.h" + +#ifdef CONFIG_CXL_PLATFORM_QUIRKS +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); +void platform_adjust_resources(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd, + const struct device *region_dev); +#else +static inline bool +platform_root_decoder_contains(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + return false; +} + +static inline bool +platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + return false; +} + +static inline void +platform_adjust_resources(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd, + const struct device *region_dev) +{ } +#endif /* CONFIG_CXL_PLATFORM_QUIRKS */ --=20 2.51.1 From nobody Tue Dec 2 02:34:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CCC12F0C6D; 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X-CSE-ConnectionGUID: oP9pWCziQ9+vz9xOVovF0g== X-CSE-MsgGUID: HLmzqjlXT8+GTKnLaEk7Hw== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76138715" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76138715" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:46 -0800 X-CSE-ConnectionGUID: P04xAaMKSTuzRLFd2Vqt3Q== X-CSE-MsgGUID: fwhgMEtGTqSkCH0c0j6VBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="228188911" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.246.148]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:41 -0800 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M . De Francesco" Subject: [PATCH 3/4 v6] cxl/core: Enable Region creation on x86 with LMH Date: Tue, 18 Nov 2025 20:43:05 +0100 Message-ID: <20251118194321.1773484-4-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> References: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host Physical Address (HPA) windows that are associated with each CXL Host Bridge. Each window represents a contiguous HPA that may be interleaved with one or more targets (CXL v3.2 - 9.18.1.3). The Low Memory Hole (LMH) of x86 is a range of addresses of physical low memory to which systems cannot send transactions. In some case the size of that hole is not compatible with the constraint that the CFMWS size shall be multiple of Interleave Ways * 256 MB. (CXL v3.2 - Table 9-22). On those systems, the BIOS publishes CFMWS which communicate the active System Physical Address (SPA) ranges that map to a subset of the Host Physical Address (HPA) ranges. The SPA range trims out the hole, and the capacity in the endpoint is lost with no SPA to map to CXL HPA in that hole. In the early stages of CXL regions construction and attach on platforms that have Low Memory Holes, cxl_add_to_region() fails and returns an error for it can't find any CFMWS range that matches a given endpoint decoder. Detect an LMH by comparing root decoder and endpoint decoder range. Match root decoders HPA range and constructed region with the corresponding endpoint decoders. Construct CXL region with the end of its HPA ranges end adjusted to the matching SPA and adjust the DPA resource end of the hardware decoders to fit the region. Allow the attach target process to complete by allowing regions and decoders to bypass the constraints that don't hold when an LMH is present.[1] [1] commit c5dca38633da ("cxl: Documentation/driver-api/cxl: Describe the x= 86 Low Memory Hole solution") Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Reviewed-by: Gregory Price Signed-off-by: Fabio M. De Francesco --- drivers/cxl/core/region.c | 43 ++++++++++++++++++++++++++++++++------- tools/testing/cxl/Kbuild | 1 + 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 315481444eb0..173a4b2d4baa 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -14,6 +14,7 @@ #include #include #include +#include "platform_quirks.h" #include "core.h" =20 /** @@ -872,6 +873,8 @@ static int match_free_decoder(struct device *dev, const= void *data) static bool spa_maps_hpa(const struct cxl_region_params *p, const struct range *range) { + struct cxl_decoder *cxld; + if (!p->res) return false; =20 @@ -880,8 +883,13 @@ static bool spa_maps_hpa(const struct cxl_region_param= s *p, * where the SPA maps equal amounts of DRAM and CXL HPA capacity with * CXL decoders at the high end of the SPA range. */ - return p->res->start + p->cache_size =3D=3D range->start && - p->res->end =3D=3D range->end; + if (p->res->start + p->cache_size =3D=3D range->start && + p->res->end =3D=3D range->end) + return true; + + cxld =3D container_of(range, struct cxl_decoder, hpa_range); + + return platform_region_matches_cxld(p, cxld); } =20 static int match_auto_decoder(struct device *dev, const void *data) @@ -1812,6 +1820,7 @@ static int match_cxlsd_to_cxled_by_range(struct devic= e *dev, const void *data) { const struct cxl_endpoint_decoder *cxled =3D data; struct cxl_switch_decoder *cxlsd; + struct cxl_root_decoder *cxlrd; const struct range *r1, *r2; =20 if (!is_switch_decoder(dev)) @@ -1821,8 +1830,13 @@ static int match_cxlsd_to_cxled_by_range(struct devi= ce *dev, const void *data) r1 =3D &cxlsd->cxld.hpa_range; r2 =3D &cxled->cxld.hpa_range; =20 - if (is_root_decoder(dev)) - return range_contains(r1, r2); + if (is_root_decoder(dev)) { + if (range_contains(r1, r2)) + return 1; + cxlrd =3D to_cxl_root_decoder(dev); + if (platform_cxlrd_matches_cxled(cxlrd, cxled)) + return 1; + } return (r1->start =3D=3D r2->start && r1->end =3D=3D r2->end); } =20 @@ -2039,7 +2053,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, } =20 if (resource_size(cxled->dpa_res) * p->interleave_ways + p->cache_size != =3D - resource_size(p->res)) { + resource_size(p->res) && !platform_cxlrd_matches_cxled(cxlrd, cxled))= { dev_dbg(&cxlr->dev, "%s:%s-size-%#llx * ways-%d + cache-%#llx !=3D region-size-%#llx\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), @@ -3472,7 +3486,8 @@ static int match_cxlrd_to_cxled_by_range(struct devic= e *dev, const void *data) r1 =3D &cxlrd->cxlsd.cxld.hpa_range; r2 =3D &cxled->cxld.hpa_range; =20 - return range_contains(r1, r2); + return (range_contains(r1, r2)) || + (platform_cxlrd_matches_cxled(cxlrd, cxled)); } =20 static struct cxl_decoder * @@ -3591,6 +3606,12 @@ static int __construct_region(struct cxl_region *cxl= r, *res =3D DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), dev_name(&cxlr->dev)); =20 + /* + * Trim the HPA retrieved from hardware to fit the SPA mapped by the + * platform + */ + platform_adjust_resources(res, cxled, cxlrd, &cxlr->dev); + rc =3D cxl_extended_linear_cache_resize(cxlr, res); if (rc && rc !=3D -EOPNOTSUPP) { /* @@ -3702,8 +3723,16 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *c= xled) mutex_lock(&cxlrd->range_lock); struct cxl_region *cxlr __free(put_cxl_region) =3D cxl_find_region_by_range(cxlrd, cxled); - if (!cxlr) + if (!cxlr) { cxlr =3D construct_region(cxlrd, cxled); + } else { + /* + * Platform adjustments are done in construct_region() + * for first target, and here for additional targets. + */ + p =3D &cxlr->params; + platform_adjust_resources(p->res, cxled, cxlrd, &cxlr->dev); + } mutex_unlock(&cxlrd->range_lock); =20 rc =3D PTR_ERR_OR_ZERO(cxlr); diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 68b38863605b..2241abbac91f 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -61,6 +61,7 @@ cxl_core-y +=3D $(CXL_CORE_SRC)/cdat.o cxl_core-y +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_TRACING) +=3D $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D $(CXL_CORE_SRC)/region.o +cxl_core-$(CONFIG_CXL_PLATFORM_QUIRKS) +=3D $(CXL_CORE_SRC)/platform_quirk= s.o cxl_core-$(CONFIG_CXL_MCE) +=3D $(CXL_CORE_SRC)/mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o --=20 2.51.1 From nobody Tue Dec 2 02:34:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADAEE2F2903; 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X-CSE-ConnectionGUID: t9hWFjnCQvGjQ6IJtNjkFg== X-CSE-MsgGUID: hNpwUKmfQbublR2wtaTWWw== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76138729" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76138729" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:51 -0800 X-CSE-ConnectionGUID: QZDmcBgjQaSE7emtNQz1WA== X-CSE-MsgGUID: uil6DXNXSI+YusXk1qd2cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="228188920" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.246.148]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 11:43:46 -0800 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M . De Francesco" Subject: [PATCH 4/4 v6] cxl/test: Simulate an x86 Low Memory Hole for tests Date: Tue, 18 Nov 2025 20:43:06 +0100 Message-ID: <20251118194321.1773484-5-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> References: <20251118194321.1773484-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simulate an x86 Low Memory Hole for the CXL tests by changing the first mock CFMWS range size to 768MB and the CXL Endpoint Decoder HPA range sizes to 1GB. The auto-created region of cxl-test uses mock_cfmws[0], therefore the LMH path in the CXL Driver will be exercised every time the cxl-test module is loaded. Since mock_cfmws[0] range base address is typically different from the one published by the BIOS on real hardware, the driver would fail to create and attach CXL Regions when it's run on the mock environment created by cxl-tests. To make the above-mentioned tests succeed again, add two "mock" versions of platform_*() that check the HPA range start of mock_cfmws[0] instead of LMH_CFMWS_RANGE_START. When cxl_core calls a cxl_core exported function and that function is mocked by cxl_test, the call chain causes a circular dependency issue. Then add also two "redirect" versions of platform_*() to work out the circular dependency issue. The LMH simulation for cxl_test.ko is enabled at module insertion time with 'low_memory_hole=3D1'. Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Signed-off-by: Fabio M. De Francesco --- drivers/cxl/core/platform_quirks.c | 31 +++++++++--- drivers/cxl/core/platform_quirks.h | 19 ++++++- tools/testing/cxl/cxl_core_exports.c | 23 +++++++++ tools/testing/cxl/exports.h | 7 +++ tools/testing/cxl/test/cxl.c | 75 ++++++++++++++++++++++++++++ tools/testing/cxl/test/mock.c | 48 ++++++++++++++++++ tools/testing/cxl/test/mock.h | 4 ++ 7 files changed, 197 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/platform_quirks.c b/drivers/cxl/core/platform= _quirks.c index be57b9666c9b..1d44a8e255c6 100644 --- a/drivers/cxl/core/platform_quirks.c +++ b/drivers/cxl/core/platform_quirks.c @@ -2,20 +2,22 @@ // Copyright(c) 2025 Intel Corporation =20 #include +#include +#include + #include "platform_quirks.h" -#include "cxlmem.h" #include "core.h" =20 /* Start of CFMWS range that end before x86 Low Memory Holes */ #define LMH_CFMWS_RANGE_START 0x0ULL =20 /** - * platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and + * __platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and * Endpoint Decoders. It allows matching on platforms with LMH's. * @cxlrd: The Root Decoder against which @cxled is tested for matching. * @cxled: The Endpoint Decoder to be tested for matching @cxlrd. * - * platform_cxlrd_matches_cxled() is typically called from the + * __platform_cxlrd_matches_cxled() is typically called from the * match_*_by_range() functions in region.c. It checks if an endpoint deco= der * matches a given root decoder and returns true to allow the driver to su= cceed * in the construction of regions where it would otherwise fail for the pr= esence @@ -30,8 +32,8 @@ * * Return: true if an endpoint matches a root decoder, else false. */ -bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, - const struct cxl_endpoint_decoder *cxled) +bool __platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) { const struct range *rd_r, *sd_r; int align; @@ -46,9 +48,10 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_= decoder *cxlrd, rd_r->end < (LMH_CFMWS_RANGE_START + SZ_4G) && IS_ALIGNED(range_len(sd_r), align); } +EXPORT_SYMBOL_NS_GPL(__platform_cxlrd_matches_cxled, "CXL"); =20 /** - * platform_region_matches_cxld() - Platform quirk to match a CXL Region a= nd a + * __platform_region_matches_cxld() - Platform quirk to match a CXL Region= and a * Switch or Endpoint Decoder. It allows matching on platforms with LMH's. * @p: Region Params against which @cxled is matched. * @cxld: Switch or Endpoint Decoder to be tested for matching @p. @@ -58,8 +61,8 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_d= ecoder *cxlrd, * * Return: true if a Decoder matches a Region, else false. */ -bool platform_region_matches_cxld(const struct cxl_region_params *p, - const struct cxl_decoder *cxld) +bool __platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) { const struct range *r =3D &cxld->hpa_range; const struct resource *res =3D p->res; @@ -71,7 +74,19 @@ bool platform_region_matches_cxld(const struct cxl_regio= n_params *p, res->end < (LMH_CFMWS_RANGE_START + SZ_4G) && IS_ALIGNED(range_len(r), align); } +EXPORT_SYMBOL_NS_GPL(__platform_region_matches_cxld, "CXL"); =20 +/** + * platform_adjust_resources() - Platform quirk that adjusts Region and En= dpoint + * Decoder DPA resources to be equal to the Root Decoder's resource end. + * @res: Resource parameters for Region construction + * @cxled: Endpoint Decoder whose DPA needs adjustment + * @cxlrd: Root Decoder whose HPA range is needed to adjust @res->end + * @region_dev: Region device for printing Region name + * + * Adjusts the Region and Endpoint Decoder DPA resource end to be equal to= the + * Root Decoder's resource end. It's needed when SPA < HPA + */ void platform_adjust_resources(struct resource *res, struct cxl_endpoint_decoder *cxled, const struct cxl_root_decoder *cxlrd, diff --git a/drivers/cxl/core/platform_quirks.h b/drivers/cxl/core/platform= _quirks.h index fce376232c16..7c2f459bb29a 100644 --- a/drivers/cxl/core/platform_quirks.h +++ b/drivers/cxl/core/platform_quirks.h @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2025 Intel Corporation */ =20 +#ifndef __PLATFORM_QUIRKS_H__ +#define __PLATFORM_QUIRKS_H__ + #include "cxl.h" =20 #ifdef CONFIG_CXL_PLATFORM_QUIRKS @@ -8,14 +11,18 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_= decoder *cxlrd, const struct cxl_endpoint_decoder *cxled); bool platform_region_matches_cxld(const struct cxl_region_params *p, const struct cxl_decoder *cxld); +bool __platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +bool __platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); void platform_adjust_resources(struct resource *res, struct cxl_endpoint_decoder *cxled, const struct cxl_root_decoder *cxlrd, const struct device *region_dev); #else static inline bool -platform_root_decoder_contains(const struct cxl_root_decoder *cxlrd, - const struct cxl_endpoint_decoder *cxled) +platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) { return false; } @@ -34,3 +41,11 @@ platform_adjust_resources(struct resource *res, const struct device *region_dev) { } #endif /* CONFIG_CXL_PLATFORM_QUIRKS */ + +#ifndef CXL_TEST_ENABLE +#define DECLARE_TESTABLE(x) __##x +#define platform_cxlrd_matches_cxled DECLARE_TESTABLE(platform_cxlrd_match= es_cxled) +#define platform_region_matches_cxld DECLARE_TESTABLE(platform_region_matc= hes_cxld) +#endif + +#endif /* __PLATFORM_QUIRKS_H__ */ diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_c= ore_exports.c index 6754de35598d..a9e37156d126 100644 --- a/tools/testing/cxl/cxl_core_exports.c +++ b/tools/testing/cxl/cxl_core_exports.c @@ -3,6 +3,7 @@ =20 #include "cxl.h" #include "exports.h" +#include "platform_quirks.h" =20 /* Exporting of cxl_core symbols that are only used by cxl_test */ EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, "CXL"); @@ -27,3 +28,25 @@ int devm_cxl_switch_port_decoders_setup(struct cxl_port = *port) return _devm_cxl_switch_port_decoders_setup(port); } EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL"); + +platform_cxlrd_matches_cxled_fn _platform_cxlrd_matches_cxled =3D + __platform_cxlrd_matches_cxled; +EXPORT_SYMBOL_NS_GPL(_platform_cxlrd_matches_cxled, "CXL"); + +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + return _platform_cxlrd_matches_cxled(cxlrd, cxled); +} +EXPORT_SYMBOL_NS_GPL(platform_cxlrd_matches_cxled, "CXL"); + +platform_region_matches_cxld_fn _platform_region_matches_cxld =3D + __platform_region_matches_cxld; +EXPORT_SYMBOL_NS_GPL(_platform_region_matches_cxld, "CXL"); + +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + return _platform_region_matches_cxld(p, cxld); +} +EXPORT_SYMBOL_NS_GPL(platform_region_matches_cxld, "CXL"); diff --git a/tools/testing/cxl/exports.h b/tools/testing/cxl/exports.h index 7ebee7c0bd67..e0e4c58dadf2 100644 --- a/tools/testing/cxl/exports.h +++ b/tools/testing/cxl/exports.h @@ -10,4 +10,11 @@ extern cxl_add_dport_by_dev_fn _devm_cxl_add_dport_by_de= v; typedef int(*cxl_switch_decoders_setup_fn)(struct cxl_port *port); extern cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup; =20 +typedef bool(*platform_cxlrd_matches_cxled_fn)(const struct cxl_root_decod= er *cxlrd, + const struct cxl_endpoint_decoder *cxled); +extern platform_cxlrd_matches_cxled_fn _platform_cxlrd_matches_cxled; + +typedef bool(*platform_region_matches_cxld_fn)(const struct cxl_region_par= ams *p, + const struct cxl_decoder *cxld); +extern platform_region_matches_cxld_fn _platform_region_matches_cxld; #endif diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 81e2aef3627a..2081b79cb354 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -9,6 +9,8 @@ #include #include #include + +#include #include =20 #include "../watermark.h" @@ -16,6 +18,7 @@ =20 static int interleave_arithmetic; static bool extended_linear_cache; +static int low_memory_hole; =20 #define FAKE_QTG_ID 42 =20 @@ -446,6 +449,35 @@ static void cfmws_elc_update(struct acpi_cedt_cfmws *w= indow, int index) window->window_size =3D mock_auto_region_size * 2; } =20 +/* + * Set the CFMWS[0] size to 768M and the endpoint decoders HPA range size = to 1G + * to simulate a low memory hole that trims the window and results in SPA = < HPA + */ +static void lmh_range_size_update(struct acpi_cedt_cfmws *window, int inde= x) +{ + if (!low_memory_hole) + return; + + if (index !=3D 0) + return; + + window->window_size =3D mock_auto_region_size * 2 - SZ_256M; + mock_auto_region_size =3D mock_auto_region_size * 2; +} + +static u64 mock_cfmws0_range_start; + +static void set_mock_cfmws0_range_start(u64 start, int index) +{ + if (!low_memory_hole) + return; + + if (index !=3D 0) + return; + + mock_cfmws0_range_start =3D start; +} + static int populate_cedt(void) { struct cxl_mock_res *res; @@ -471,10 +503,12 @@ static int populate_cedt(void) struct acpi_cedt_cfmws *window =3D mock_cfmws[i]; =20 cfmws_elc_update(window, i); + lmh_range_size_update(window, i); res =3D alloc_mock_res(window->window_size, SZ_256M); if (!res) return -ENOMEM; window->base_hpa =3D res->range.start; + set_mock_cfmws0_range_start(res->range.start, i); } =20 return 0; @@ -1114,6 +1148,39 @@ static void mock_cxl_endpoint_parse_cdat(struct cxl_= port *port) cxl_endpoint_get_perf_coordinates(port, ep_c); } =20 +static bool +mock_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + const struct range *rd_r, *ed_r; + int align; + + rd_r =3D &cxlrd->cxlsd.cxld.hpa_range; + ed_r =3D &cxled->cxld.hpa_range; + align =3D cxled->cxld.interleave_ways * SZ_256M; + + return rd_r->start =3D=3D mock_cfmws0_range_start && + rd_r->start =3D=3D ed_r->start && + rd_r->end < (mock_cfmws0_range_start + SZ_4G) && + rd_r->end < ed_r->end && + IS_ALIGNED(range_len(ed_r), align); +} + +static bool +mock_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + const struct range *r =3D &cxld->hpa_range; + const struct resource *res =3D p->res; + int align =3D cxld->interleave_ways * SZ_256M; + + return res->start =3D=3D mock_cfmws0_range_start && + res->start =3D=3D r->start && + res->end < (mock_cfmws0_range_start + SZ_4G) && + res->end < r->end && + IS_ALIGNED(range_len(r), align); +} + static struct cxl_mock_ops cxl_mock_ops =3D { .is_mock_adev =3D is_mock_adev, .is_mock_bridge =3D is_mock_bridge, @@ -1129,6 +1196,8 @@ static struct cxl_mock_ops cxl_mock_ops =3D { .devm_cxl_add_dport_by_dev =3D mock_cxl_add_dport_by_dev, .hmat_get_extended_linear_cache_size =3D mock_hmat_get_extended_linear_cache_size, + .platform_cxlrd_matches_cxled =3D mock_platform_cxlrd_matches_cxled, + .platform_region_matches_cxld =3D mock_platform_region_matches_cxld, .list =3D LIST_HEAD_INIT(cxl_mock_ops.list), }; =20 @@ -1426,6 +1495,10 @@ static __init int cxl_test_init(void) cxl_pmem_test(); cxl_port_test(); =20 + /* LMH and ELC tests are nutually exclusive */ + if (low_memory_hole && extended_linear_cache) + return -EINVAL; + register_cxl_mock_ops(&cxl_mock_ops); =20 cxl_mock_pool =3D gen_pool_create(ilog2(SZ_2M), NUMA_NO_NODE); @@ -1620,6 +1693,8 @@ module_param(interleave_arithmetic, int, 0444); MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1"); module_param(extended_linear_cache, bool, 0444); MODULE_PARM_DESC(extended_linear_cache, "Enable extended linear cache supp= ort"); +module_param(low_memory_hole, int, 0444); +MODULE_PARM_DESC(low_memory_hole, "Enable Low Memory Hole simulation"); module_init(cxl_test_init); module_exit(cxl_test_exit); MODULE_LICENSE("GPL v2"); diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 6eb15991a414..0cf4d7a8c4c4 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -7,6 +7,8 @@ #include #include #include + +#include #include #include #include "mock.h" @@ -18,6 +20,12 @@ static struct cxl_dport * redirect_devm_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev); static int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *p= ort); +static bool +redirect_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +static bool +redirect_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); =20 void register_cxl_mock_ops(struct cxl_mock_ops *ops) { @@ -25,6 +33,8 @@ void register_cxl_mock_ops(struct cxl_mock_ops *ops) _devm_cxl_add_dport_by_dev =3D redirect_devm_cxl_add_dport_by_dev; _devm_cxl_switch_port_decoders_setup =3D redirect_devm_cxl_switch_port_decoders_setup; + _platform_cxlrd_matches_cxled =3D redirect_platform_cxlrd_matches_cxled; + _platform_region_matches_cxld =3D redirect_platform_region_matches_cxld; } EXPORT_SYMBOL_GPL(register_cxl_mock_ops); =20 @@ -35,6 +45,8 @@ void unregister_cxl_mock_ops(struct cxl_mock_ops *ops) _devm_cxl_switch_port_decoders_setup =3D __devm_cxl_switch_port_decoders_setup; _devm_cxl_add_dport_by_dev =3D __devm_cxl_add_dport_by_dev; + _platform_cxlrd_matches_cxled =3D __platform_cxlrd_matches_cxled; + _platform_region_matches_cxld =3D __platform_region_matches_cxld; list_del_rcu(&ops->list); synchronize_srcu(&cxl_mock_srcu); } @@ -290,6 +302,42 @@ struct cxl_dport *redirect_devm_cxl_add_dport_by_dev(s= truct cxl_port *port, return dport; } =20 +static bool +redirect_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + int index; + bool match; + struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); + struct cxl_port *port =3D to_cxl_port(cxled->cxld.dev.parent); + + if (ops && ops->is_mock_port(port->uport_dev)) + match =3D ops->platform_cxlrd_matches_cxled(cxlrd, cxled); + else + match =3D __platform_cxlrd_matches_cxled(cxlrd, cxled); + put_cxl_mock_ops(index); + + return match; +} + +static bool +redirect_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + int index; + bool match; + struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); + struct cxl_port *port =3D to_cxl_port(cxld->dev.parent); + + if (ops && ops->is_mock_port(port->uport_dev)) + match =3D ops->platform_region_matches_cxld(p, cxld); + else + match =3D __platform_region_matches_cxld(p, cxld); + put_cxl_mock_ops(index); + + return match; +} + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("cxl_test: emulation module"); MODULE_IMPORT_NS("ACPI"); diff --git a/tools/testing/cxl/test/mock.h b/tools/testing/cxl/test/mock.h index 2684b89c8aa2..ac66cf171834 100644 --- a/tools/testing/cxl/test/mock.h +++ b/tools/testing/cxl/test/mock.h @@ -27,6 +27,10 @@ struct cxl_mock_ops { int (*hmat_get_extended_linear_cache_size)(struct resource *backing_res, int nid, resource_size_t *cache_size); + bool (*platform_cxlrd_matches_cxled)(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); + bool (*platform_region_matches_cxld)(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); }; =20 void register_cxl_mock_ops(struct cxl_mock_ops *ops); --=20 2.51.1