From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E657A2D0C8C; Tue, 18 Nov 2025 18:34:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490878; cv=none; b=pElx7iD2W8/59Mdn24iN5JdE5CQVPMlEBYhoze5Gjfo3WWLQxJLMxUcn3Pn9RelPoBM/1S6Es8Hl8Xl1v+PuPoudIYi6yCZNb92OtBP/ec/cdnt0sq9ePeUP6jYk8x9iJpCou1c6sB9Bi/iocxTVnmf2XJmyS1Lv191FJmlMI/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490878; c=relaxed/simple; bh=iGj4Bp38cIMAdXi3xTm5k9nWPfso400Ax3LsO+5Bkt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d4n7og5HyV8ZkhPmctjms18yEAEbBo6bG1QQWh9XmIkNEJnboHVw0SlaZ7bAaEdEwwQ1QHs8ly6H22jsJxvSvaiKa5Id1MudOhtiRkhbSNrtR7Q3LdSE1iYTXnZv3au8ahM8xEglvffCLhOx1SqC9ugaskGxoFqljILm7bj+7nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U7qFcisJ; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U7qFcisJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490876; x=1795026876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iGj4Bp38cIMAdXi3xTm5k9nWPfso400Ax3LsO+5Bkt0=; b=U7qFcisJeIwu91aBKI7R1PNno/IsatKtc/rW5S15qBKlgYWtp3IKVUT0 hhr/Gq+cG3IFSrYgvCidjEy/d444V7IvnjgjFMbsGH2Zf5uTOuUWSn4n4 Y4CjGMziESYmjxHnNmOo1T06we3V/R6gmrrsERUP+lDRnmv2xW4AMPxPj ZftH8JSi4Zr3bgQbBTLWYcDyqZaeHD3fg+/6YtcR8YhkUO3RmjeUpj2RL Pr2PQC1sOlph8HwoQN1M3SnBmlvT2BAEcd+ahjBi4HTWctHDAnegHry2u Q8YrIRdJR99eX+wRnZl1lRB4BKhNhionfn9BUdi9VHs+voeOXbrUA6zC5 g==; X-CSE-ConnectionGUID: hEyDRlszQxG987VsHHZ6Fw== X-CSE-MsgGUID: /1AOiV/7S1G/yGhOFcFerQ== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979746" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979746" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:53 -0800 X-CSE-ConnectionGUID: hVx6DjoAT9yVvXDevDSM3Q== X-CSE-MsgGUID: LpR3wT3CRr2c4t6SBwtqXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088916" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:52 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 1/8] x86/cpufeatures: Enumerate the LASS feature bits Date: Tue, 18 Nov 2025 10:29:03 -0800 Message-ID: <20251118182911.2983253-2-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Linear Address Space Separation (LASS) is a security feature that mitigates a class of side-channel attacks relying on speculative access across the user/kernel boundary. Privilege mode based access protection already exists today with paging and features such as SMEP and SMAP. However, to enforce these protections, the processor must traverse the paging structures in memory. An attacker can use timing information resulting from this traversal to determine details about the paging structures, and to determine the layout of the kernel memory. LASS provides the same mode-based protections as paging but without traversing the paging structures. Because the protections are enforced prior to page-walks, an attacker will not be able to derive paging-based timing information from the various caching structures such as the TLBs, mid-level caches, page walker, data caches, etc. LASS enforcement relies on the kernel implementation to divide the 64-bit virtual address space into two halves: Addr[63]=3D0 -> User address space Addr[63]=3D1 -> Kernel address space Any data access or code execution across address spaces typically results in a #GP fault, with an #SS generated in some rare cases. The LASS enforcement for kernel data accesses is dependent on CR4.SMAP being set. The enforcement can be disabled by toggling the RFLAGS.AC bit similar to SMAP. Define the CPU feature bits to enumerate LASS. Also, disable the feature at compile time on 32-bit kernels. Use a direct dependency on X86_32 (instead of !X86_64) to make it easier to combine with similar 32-bit specific dependencies in the future. LASS mitigates a class of side-channel speculative attacks, such as Spectre LAM, described in the paper, "Leaky Address Masking: Exploiting Unmasked Spectre Gadgets with Noncanonical Address Translation". Add the "lass" flag to /proc/cpuinfo to indicate that the feature is supported by hardware and enabled by the kernel. This allows userspace to determine if the system is secure against such attacks. Signed-off-by: Sohil Mehta Reviewed-by: Borislav Petkov (AMD) Reviewed-by: Xin Li (Intel) Reviewed-by: Dave Hansen --- v12: - Pick up review tag. v11: - Split the SMAP dependency hunk into a separate patch (patch 2). - Improve commit message. --- arch/x86/Kconfig.cpufeatures | 4 ++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/uapi/asm/processor-flags.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures index 250c10627ab3..733d5aff2456 100644 --- a/arch/x86/Kconfig.cpufeatures +++ b/arch/x86/Kconfig.cpufeatures @@ -124,6 +124,10 @@ config X86_DISABLED_FEATURE_PCID def_bool y depends on !X86_64 =20 +config X86_DISABLED_FEATURE_LASS + def_bool y + depends on X86_32 + config X86_DISABLED_FEATURE_PKU def_bool y depends on !X86_INTEL_MEMORY_PROTECTION_KEYS diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 4091a776e37a..8d872eb08c16 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -314,6 +314,7 @@ #define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructio= ns */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT= 16 instructions */ +#define X86_FEATURE_LASS (12*32+ 6) /* "lass" Linear Address Space Separa= tion */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructio= ns */ #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural Per= fMon Extension */ #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */ diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include= /uapi/asm/processor-flags.h index f1a4adc78272..81d0c8bf1137 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -136,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology = */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LASS_BIT 27 /* enable Linear Address Space Separation supp= ort */ +#define X86_CR4_LASS _BITUL(X86_CR4_LASS_BIT) #define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ #define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) =20 --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAF112BD582; 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a="76979781" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979781" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:53 -0800 X-CSE-ConnectionGUID: SF+xF0xrRi2E4PnlOTD3mQ== X-CSE-MsgGUID: Oa01vVCPTa6am3bGN5J5yw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088925" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:53 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 2/8] x86/cpu: Add an LASS dependency on SMAP Date: Tue, 18 Nov 2025 10:29:04 -0800 Message-ID: <20251118182911.2983253-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With LASS enabled, any kernel data access to userspace typically results in a #GP, or a #SS in some stack-related cases. When the kernel needs to access user memory, it can suspend LASS enforcement by toggling the RFLAGS.AC bit. Most of these cases are already covered by the stac()/clac() pairs used to avoid SMAP violations. Even though LASS could potentially be enabled independently, it would be very painful without SMAP and the related stac()/clac() calls. There is no reason to support such a configuration because all future hardware with LASS is expected to have SMAP as well. Also, the STAC/CLAC instructions are architected to: #UD - If CPUID.(EAX=3D07H, ECX=3D0H):EBX.SMAP[bit 20] =3D 0. So, make LASS depend on SMAP to conveniently reuse the existing AC bit toggling already in place. Note: Additional STAC/CLAC would still be needed for accesses such as text poking which are not flagged by SMAP. This is because such mappings are in the lower half but do not have the _PAGE_USER bit set which SMAP uses for enforcement. Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v12: - Pick up review tag. v11: - New patch (split from patch 1). --- arch/x86/kernel/cpu/cpuid-deps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..98d0cdd82574 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -89,6 +89,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, { X86_FEATURE_FRED, X86_FEATURE_LKGS }, { X86_FEATURE_SPEC_CTRL_SSBD, X86_FEATURE_SPEC_CTRL }, + { X86_FEATURE_LASS, X86_FEATURE_SMAP }, {} }; =20 --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 837C22DE1FA; Tue, 18 Nov 2025 18:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490887; cv=none; b=ObGbs196rp5iC7BMT0Uvq1/vWkuYghmfFO9wJfs5IAQxD5Chx9z8l9qbcNGI/LSWhhCobcARzF63gX7M5YQdzzgIbGNJygboqtVBM6Y5zfDizVNaK9LGtflBLSERcWfXQos4zk7Lmbfk7EubMw8u8DAoLYIGfZtS6h8IjBHBdio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490887; c=relaxed/simple; bh=3v51fqgW7yBK6B/AFGSul1SUT9hseHQhv6m1LfAlgx4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dwbMffl90ymfaWfp0Gr9rWvEwmg/mZiFwDKSqoasiDSfzp1ykjZJl0z/9cJBpuUWDO6HcLX0DlImrknn2PgjXkPMsLwYpvD5MT9rL5tYYZWtSaw8/E2mbIvupmGWYd2MfbwN2afJRNJr6o0jLHz3B5eWba9XPh4XA/Usbod0jPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a708jOUq; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a708jOUq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490885; x=1795026885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3v51fqgW7yBK6B/AFGSul1SUT9hseHQhv6m1LfAlgx4=; b=a708jOUq2CpTcX1A7BWJe4oD0yirKxuZwWS6AtWRiTYnlslqtTsm+Dw1 oQr/aARc4+yaugjCaAjwYv6a2NaZ/S4a1W33jXjGrZlROv7hh0IUqVzn2 0Hy2VuHofZ59RPmgM5ZJBj/EaN36c18+/jH3LABIIb0Mod5KfIW+4R9i0 qJGyCTi81T67ySWYH6lSz6jylwBZvPldEvk2wd8b8kxX4ZPI4TtfI7oiB 5VarpLXziVnE2W/ja7ODipIN3lySZJbIOA3hqfih1lwhqemnF8My5c+ZF ForkaPm8Deedohg/ofevSDdxyLAS/RVSED4iQvkzTCRfuFnMg2uMYG/AF Q==; X-CSE-ConnectionGUID: IWdLTQLsQ+ODMyeqY39y6Q== X-CSE-MsgGUID: K10pPS3tQEqpYKdhAxX+xA== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979817" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979817" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:54 -0800 X-CSE-ConnectionGUID: lBEF+gJKSU+pN+oCz5Jmaw== X-CSE-MsgGUID: 48Mpb1TdTMyk889mUiPyKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088931" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:54 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 3/8] x86/asm: Introduce inline memcpy and memset Date: Tue, 18 Nov 2025 10:29:05 -0800 Message-ID: <20251118182911.2983253-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Peter Zijlstra (Intel)" Provide inline memcpy and memset functions that can be used instead of the GCC builtins when necessary. The immediate use case is for the text poking functions to avoid the standard memcpy()/memset() calls because objtool complains about such dynamic calls within an AC=3D1 region. See tools/objtool/Documentation/objtool.txt, warning #9, regarding function calls with UACCESS enabled. Some user copy functions such as copy_user_generic() and __clear_user() have similar rep_{movs,stos} usages. But, those are highly specialized and hard to combine or reuse for other things. Define these new helpers for all other usages that need a completely unoptimized, strictly inline version of memcpy() or memset(). Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v12: - Pick up review tag. v11: - Improve commit log. --- arch/x86/include/asm/string.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index c3c2c1914d65..9cb5aae7fba9 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -1,6 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_STRING_H +#define _ASM_X86_STRING_H + #ifdef CONFIG_X86_32 # include #else # include #endif + +static __always_inline void *__inline_memcpy(void *to, const void *from, s= ize_t len) +{ + void *ret =3D to; + + asm volatile("rep movsb" + : "+D" (to), "+S" (from), "+c" (len) + : : "memory"); + return ret; +} + +static __always_inline void *__inline_memset(void *s, int v, size_t n) +{ + void *ret =3D s; + + asm volatile("rep stosb" + : "+D" (s), "+c" (n) + : "a" ((uint8_t)v) + : "memory"); + return ret; +} + +#endif /* _ASM_X86_STRING_H */ --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D38742DCC17; Tue, 18 Nov 2025 18:34:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490891; cv=none; b=HRjj2MXgO/TRwBMDCAmGwCa3ooNKK6VEwYlycSLzIp+pyLHshQzuhI9XmNlbmpq18aRXRCTxfnL5rzOe7bGMCNNvUhTZBmqobhVq/LzqNLGs30j9sT+VRtNTz5yDm3Wcj3B2Ke5+rYEB3wRXXRwGXbj9ukqBFyxG7w7oup6LGlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490891; c=relaxed/simple; bh=gvbT3BHteEQ6s+AC0t6voXLmJ8qwMJg0xNxsHAAJFeg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vCpeVkf7NV3DyH1+1O2lzrR+rB8fBpTxgYmZD3phsNBL3/bDWFhaDnSuVKMCn9lFOuYAWlcNAht7ww5Cc4fHR6XxtsjLip5o4p0K1K+oWaVffB2XRwpcIn7amPhpBZdFWsXUYMwt/xS40qx0+H/tPYE7hwgNkkQhT8nOw9rw2nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c1aBKYNa; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c1aBKYNa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490890; x=1795026890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gvbT3BHteEQ6s+AC0t6voXLmJ8qwMJg0xNxsHAAJFeg=; b=c1aBKYNavZdDPenWu5J+g/k0sBxG+FekaBK41VJAYzb9U9nqpUSWFHqu KBHSKrWfdKBRKnW4t5OJSybfDCTUr0q0uM8Tpwmr+FTzI721z5jQVvO4c LVM4gGKg1fJWVF45/xoJJX3TuCf4pVEfvYJrqTQtNs9/qyc1X//ttf+ca 5uI6jsO6SH0Fv97We/l4tXxRG9WKqSNawQ4/GIT3MRBNRl90m6cPSWzdD WBe2z4avm4sHMCkJMy4MaPbMPKq5tKueQY423mjLCbB916NeHuYsOjDA4 CNFR5X90rk3ugE8M5MzfBqLCgjATnCZsJBnTle08jDZqbe3D79LEi4k7u Q==; X-CSE-ConnectionGUID: K4G/hnmpQH+FmNm/D+mQRw== X-CSE-MsgGUID: D903zdJhR8+VnZMWL/QuzA== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979850" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979850" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:55 -0800 X-CSE-ConnectionGUID: h4zZqVOjTHaDXwYP7IjTew== X-CSE-MsgGUID: oeCQcbbeS6mDepUjiJd/OQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088940" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:55 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 4/8] x86/alternatives: Disable LASS when patching kernel code Date: Tue, 18 Nov 2025 10:29:06 -0800 Message-ID: <20251118182911.2983253-5-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For patching, the kernel initializes a temporary mm area in the lower half of the address range. LASS blocks these accesses because its enforcement relies on bit 63 of the virtual address as opposed to SMAP which depends on the _PAGE_BIT_USER bit in the page table. Disable LASS enforcement by toggling the RFLAGS.AC bit during patching to avoid triggering a #GP fault. Introduce LASS-specific STAC/CLAC helpers to set the AC bit only on platforms that need it. Name the wrappers as lass_stac()/_clac() instead of lass_disable()/_enable() because they only control the kernel data access enforcement. The entire LASS mechanism (including instruction fetch enforcement) is controlled by the CR4.LASS bit. Describe the usage of the new helpers in comparison to the ones used for SMAP. Also, add comments to explain when the existing stac()/clac() should be used. While at it, move the duplicated "barrier" comment to the same block. The Text poking functions use standard memcpy()/memset() while patching kernel code. However, objtool complains about calling such dynamic functions within an AC=3D1 region. See warning #9, regarding function calls with UACCESS enabled, in tools/objtool/Documentation/objtool.txt. To pacify objtool, one option is to add memcpy() and memset() to the list of allowed-functions. However, that would provide a blanket exemption for all usages of memcpy() and memset(). Instead, replace the standard calls in the text poking functions with their unoptimized, always-inlined versions. Considering that patching is usually small, there is no performance impact expected. Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v12: - Revert to lass_clac()/lass_stac() naming. - Pick up review tag. v11: - Use lass_enable()/lass_disable() naming. - Improve commit log and code comments. --- arch/x86/include/asm/smap.h | 41 +++++++++++++++++++++++++++++++++-- arch/x86/kernel/alternative.c | 18 +++++++++++++-- 2 files changed, 55 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/smap.h b/arch/x86/include/asm/smap.h index 4f84d421d1cf..20a3baae9568 100644 --- a/arch/x86/include/asm/smap.h +++ b/arch/x86/include/asm/smap.h @@ -23,18 +23,55 @@ =20 #else /* __ASSEMBLER__ */ =20 +/* + * The CLAC/STAC instructions toggle the enforcement of + * X86_FEATURE_SMAP along with X86_FEATURE_LASS. + * + * SMAP enforcement is based on the _PAGE_BIT_USER bit in the page + * tables. The kernel is not allowed to touch pages with that bit set + * unless the AC bit is set. + * + * Use stac()/clac() when accessing userspace (_PAGE_USER) mappings, + * regardless of location. + * + * Note: a barrier is implicit in alternative(). + */ + static __always_inline void clac(void) { - /* Note: a barrier is implicit in alternative() */ alternative("", "clac", X86_FEATURE_SMAP); } =20 static __always_inline void stac(void) { - /* Note: a barrier is implicit in alternative() */ alternative("", "stac", X86_FEATURE_SMAP); } =20 +/* + * LASS enforcement is based on bit 63 of the virtual address. The + * kernel is not allowed to touch memory in the lower half of the + * virtual address space. + * + * Use lass_stac()/lass_clac() to toggle the AC bit for kernel data + * accesses (!_PAGE_USER) that are blocked by LASS, but not by SMAP. + * + * Even with the AC bit set, LASS will continue to block instruction + * fetches from the user half of the address space. To allow those, + * clear CR4.LASS to disable the LASS mechanism entirely. + * + * Note: a barrier is implicit in alternative(). + */ + +static __always_inline void lass_clac(void) +{ + alternative("", "clac", X86_FEATURE_LASS); +} + +static __always_inline void lass_stac(void) +{ + alternative("", "stac", X86_FEATURE_LASS); +} + static __always_inline unsigned long smap_save(void) { unsigned long flags; diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 8ee5ff547357..5b09f89070f0 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -2469,16 +2469,30 @@ void __init_or_module text_poke_early(void *addr, c= onst void *opcode, __ro_after_init struct mm_struct *text_poke_mm; __ro_after_init unsigned long text_poke_mm_addr; =20 +/* + * Text poking creates and uses a mapping in the lower half of the + * address space. Relax LASS enforcement when accessing the poking + * address. + * + * objtool enforces a strict policy of "no function calls within AC=3D1 + * regions". Adhere to the policy by using inline versions of + * memcpy()/memset() that will never result in a function call. + */ + static void text_poke_memcpy(void *dst, const void *src, size_t len) { - memcpy(dst, src, len); + lass_stac(); + __inline_memcpy(dst, src, len); + lass_clac(); } =20 static void text_poke_memset(void *dst, const void *src, size_t len) { int c =3D *(const int *)src; =20 - memset(dst, c, len); + lass_stac(); + __inline_memset(dst, c, len); + lass_clac(); } =20 typedef void text_poke_f(void *dst, const void *src, size_t len); --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D3DF2DBF4B; Tue, 18 Nov 2025 18:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490895; cv=none; b=e+XajmXV/Kjs9g1z9RgKiW1lzaimQeVUwTx2Yt35UBd6YjocNMqaHh2G6Ha149CeCPu7vmeMzNjvRTh3aP3TzntBnOYB4xZh3+6c/n6JV9fi1vTn4iGkYbH171iOIPQHmFMVd40df4ynMPldJGnhBmDMBwtZOmF2+Z/AiDD0OMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490895; c=relaxed/simple; bh=8d3y0tuH+JUD4QfSiQiDm9n5LoaQCNgr1flLLNl4hIs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EVU8bBEXrE1dPKKR3wEOHFJx7uF9agxAwMUXlCZume2UGvQmcJleHKraWiKAkWuxUeYjB/d6PK8CD7hAfoq0u4WYFluexbFWMvMShYKFo5grqXgd3JJz9RyfLWWqJgTG9aRcH5Zvch7q2tMK25lTgqxGxSMaoZz2O1OLY+ZZwf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QoyV7cRw; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QoyV7cRw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490894; x=1795026894; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8d3y0tuH+JUD4QfSiQiDm9n5LoaQCNgr1flLLNl4hIs=; b=QoyV7cRwB73rjVeuTHZY6oIo0hju5HsfcMug/VbLnBaiojmNzm257V68 z2URUzseIVx3A4FozrTHb2c1DAnFBH9SwQjp8mElGRvURA0dJ8Dp/RiYb tK6GZuMu8HOB7U7KZ5Ewt1sSKzm/E6RaVIptxNqVOM4zpHdxpRJ9UfF7q OuEke+/fRJlH5o54slptsCJ3qubrV3GEOCVynC10CylaKjmuQGoh4223J ALlbbIdLuv2QOPdcqgQqo5Fj86cW4fPwpdGzGuEdMMqIHApVt/fZ2k4zf UvOWr4CXpsKnD0SA9tObSlj7388E7zAHEf/cY7i99JAIWA0NZRge6MlEu w==; X-CSE-ConnectionGUID: IZ272lcBQ72aqHVxGjnXsQ== X-CSE-MsgGUID: 7I7DHdf6QFy6SVYQaQjDpw== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979883" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979883" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:56 -0800 X-CSE-ConnectionGUID: PRQHp1SLT8+yYXwzNhEANg== X-CSE-MsgGUID: wG00PbBiQtq7a5pnFZwRcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088946" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:55 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 5/8] x86/kexec: Disable LASS during relocate kernel Date: Tue, 18 Nov 2025 10:29:07 -0800 Message-ID: <20251118182911.2983253-6-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The relocate kernel mechanism uses an identity mapping to copy the new kernel, which leads to a LASS violation when executing from a low address. LASS must be disabled after the original CR4 value is saved because kexec paths that preserve context need to restore CR4.LASS. But, disabling it along with CET during identity_mapped() is too late. So, disable LASS immediately after saving CR4, along with PGE, and before jumping to the identity-mapped page. Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v12: - Pick up review tag. v11: - Improve commit message. --- arch/x86/kernel/relocate_kernel_64.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocat= e_kernel_64.S index 11e20bb13aca..4ffba68dc57b 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -95,9 +95,12 @@ SYM_CODE_START_NOALIGN(relocate_kernel) /* Leave CR4 in %r13 to enable the right paging mode later. */ movq %cr4, %r13 =20 - /* Disable global pages immediately to ensure this mapping is RWX */ + /* + * Disable global pages immediately to ensure this mapping is RWX. + * Disable LASS before jumping to the identity mapped page. + */ movq %r13, %r12 - andq $~(X86_CR4_PGE), %r12 + andq $~(X86_CR4_PGE | X86_CR4_LASS), %r12 movq %r12, %cr4 =20 /* Save %rsp and CRs. */ --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E14592E06ED; Tue, 18 Nov 2025 18:34:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490899; cv=none; b=TyCtZNz/zKvyY0ZyBXD2hplO6bmcIv8OSXKzDC8X8ML9teA0jPPyf2ctNiwC8/QbfCJNdVwo/Qi5eo9MYwAX3d1OoB4QXx5ZZKE2xc5nCRqpW0rX9Haz8EDzQAtx5EMNCLBdHiUaXBHgpqxI1OtzOqV0aPqlQsQrw+BLqYRuNWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490899; c=relaxed/simple; bh=zghdUcfGJrBJt+l+cxe42GPOYm5btcUr2ZEKw1Z2Ojw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FV0dMXPKgVkbVf3p08KWLDYeL6zwdVhsSFtOCQjwPH+xThMOT7maGVM3mURHriTwNAHDv9SQ3vMAKoRi2AQwGjK5t4fAIzARK64/0L6EWhq8LbKk/aBjrAUel+OG98qJR/Ib5yJHtBy5QNvWUD2rj4z/Z0jOv2LDsd0xHWZojZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CpfC8mDi; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CpfC8mDi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490898; x=1795026898; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zghdUcfGJrBJt+l+cxe42GPOYm5btcUr2ZEKw1Z2Ojw=; b=CpfC8mDiFGW5wgDcoXXj6Z+Xsa3D9UioMtzVkU1PNK5eI2ZWFP6mKrTR vJfLqkMi1ArwtFAekgPB2T8iZ30mw1DwUbRWg086MOUp0mHTTrTSmU7HK EmXyz8NiXnWWH6Bc+PSOBEs5BQXxZKqlQHqwRN72IjGdKP/VNgejlQ2Cn y280EXWcIHXWHJqSw9I4a+RRUkfpoWORu2b+YGy+fKPH43QdeO2uCZY9L SxwPjWm04wDxvzr4gcJYmeF5xfjq6Y6OTPholqcmzS7rYMYVYqOik2oSC LM3UEcXwYcNVsrWs0589joBZy1na/Fxow2iS63BRQop/UNiueWScp1a8u g==; X-CSE-ConnectionGUID: tEwMwGs4Sq+VUpt8RdY3/g== X-CSE-MsgGUID: 16d/7rezTXOHcBQI/SWsPA== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979924" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979924" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:56 -0800 X-CSE-ConnectionGUID: XcL1OKMKS5W21CL6MjjVzg== X-CSE-MsgGUID: YnhCGqWPRbm7NO/nV66u1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088952" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:56 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 6/8] x86/traps: Communicate a LASS violation in #GP message Date: Tue, 18 Nov 2025 10:29:08 -0800 Message-ID: <20251118182911.2983253-7-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Shishkin A LASS violation typically results in a #GP. With LASS active, any invalid access to user memory (including the first page frame) would be reported as a #GP, instead of a #PF. Unfortunately, the #GP error messages provide limited information about the cause of the fault. This could be confusing for kernel developers and users who are accustomed to the friendly #PF messages. To make the transition easier, enhance the #GP Oops message to include a hint about LASS violations. Also, add a special hint for kernel NULL pointer dereferences to match with the existing #PF message. Signed-off-by: Alexander Shishkin Signed-off-by: Kirill A. Shutemov Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v13: - Update comment to clarify NULL pointer case. v12: - Pick up review tag. v11: - Improve commit log. --- arch/x86/kernel/traps.c | 46 ++++++++++++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 6b22611e69cc..1b9177b93433 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -635,13 +635,23 @@ DEFINE_IDTENTRY(exc_bounds) enum kernel_gp_hint { GP_NO_HINT, GP_NON_CANONICAL, - GP_CANONICAL + GP_CANONICAL, + GP_LASS_VIOLATION, + GP_NULL_POINTER, +}; + +static const char * const kernel_gp_hint_help[] =3D { + [GP_NON_CANONICAL] =3D "probably for non-canonical address", + [GP_CANONICAL] =3D "maybe for address", + [GP_LASS_VIOLATION] =3D "probably LASS violation for address", + [GP_NULL_POINTER] =3D "kernel NULL pointer dereference", }; =20 /* * When an uncaught #GP occurs, try to determine the memory address access= ed by * the instruction and return that address to the caller. Also, try to fig= ure - * out whether any part of the access to that address was non-canonical. + * out whether any part of the access to that address was non-canonical or + * across privilege levels. */ static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, unsigned long *addr) @@ -663,14 +673,28 @@ static enum kernel_gp_hint get_kernel_gp_address(stru= ct pt_regs *regs, return GP_NO_HINT; =20 #ifdef CONFIG_X86_64 - /* - * Check that: - * - the operand is not in the kernel half - * - the last byte of the operand is not in the user canonical half - */ - if (*addr < ~__VIRTUAL_MASK && - *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) + /* Operand is in the kernel half */ + if (*addr >=3D ~__VIRTUAL_MASK) + return GP_CANONICAL; + + /* The last byte of the operand is not in the user canonical half */ + if (*addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) return GP_NON_CANONICAL; + + /* + * A NULL pointer dereference usually causes a #PF. However, it + * can result in a #GP when LASS is active. Provide the same + * hint in the rare case that the condition is hit without LASS. + */ + if (*addr < PAGE_SIZE) + return GP_NULL_POINTER; + + /* + * Assume that LASS caused the exception, because the address is + * canonical and in the user half. + */ + if (cpu_feature_enabled(X86_FEATURE_LASS)) + return GP_LASS_VIOLATION; #endif =20 return GP_CANONICAL; @@ -833,9 +857,7 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) =20 if (hint !=3D GP_NO_HINT) snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", - (hint =3D=3D GP_NON_CANONICAL) ? "probably for non-canonical address" - : "maybe for address", - gp_addr); + kernel_gp_hint_help[hint], gp_addr); =20 /* * KASAN is interested only in the non-canonical case, clear it --=20 2.43.0 From nobody Tue Dec 2 02:33:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6222DC787; Tue, 18 Nov 2025 18:35:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490904; cv=none; b=uPpnKszPLOfBnEf4So1Zjmnr5FGMc+JMAXHsmh7poDXoRPobE2mZMa/6GF8c9P0A9Q3Is9EZOTPCkQTlnFo/v5CVAc2Hod6M4patvYUfh/8Y5h3MFsCFYrPsUyCjl9i0xdfS2xZGY9bKCL4A5VUs8D4ukgvrcseXa3ajVqSG/b8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763490904; c=relaxed/simple; bh=Of1UkDgA+A8BDxzkeo8tPZu02XdKsJjP//uVe66ASjQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hi/rk9OK8usXgDtMzF+RBxTg8fTN8l776kIA3h2TpMBsxMIZYVdtl2CjrzzvJUP1qDUolB9Z7sx8Or6kXcwdQQuhK9OOHEhoOs8aK2RotEdD3NoyqATeHPOxEzrChUB9dDw0j27PINtR56pMi6jRUenMjA2PPhvBxPKAj50L73E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H7zn8IpR; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H7zn8IpR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763490903; x=1795026903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Of1UkDgA+A8BDxzkeo8tPZu02XdKsJjP//uVe66ASjQ=; b=H7zn8IpR4em3o8GA6BJ8srEyI21UpHIoLfSdAH00I9fxb5+5pwZohVM+ 2mbKP+Dnq1NYx3oEr1jhn/Y+yMcDu5DiCWBY2BoYtJ8YdrQ4FhNDHfZjd /7M8f8vp+7MShjAi60xhDV900znP4oqZRK4CtaYK9KASrq8qo1Ejj9tUs QYNEl/NXNgBgj1lqlCVi5zSNjjl6/jngisQohwVXXXD1wDsdxeu2yx5Nj fn5PVsIK9QLSUnEz2S7jEplf6tAjAeWrnnM0cChcl/jZUcx2wXVO9eaSH nsm6t5AkcRaVLnWf27AiNpvr0OZu+hvu2CzhNmAU9o9gW8ZZdYteesKh9 Q==; X-CSE-ConnectionGUID: kmAlPHxDSWC3GPdIIz5c9Q== X-CSE-MsgGUID: +ri3xi97SJaiDkQmtwHB8Q== X-IronPort-AV: E=McAfee;i="6800,10657,11617"; a="76979955" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="76979955" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 10:31:57 -0800 X-CSE-ConnectionGUID: BReNKAusRMi3989MjLWa7A== X-CSE-MsgGUID: vqkSOBvNRnuhJ512RtbM3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190088959" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:57 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 7/8] selftests/x86: Update the negative vsyscall tests to expect a #GP Date: Tue, 18 Nov 2025 10:29:09 -0800 Message-ID: <20251118182911.2983253-8-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the vsyscall selftests expect a #PF when vsyscalls are disabled. However, with LASS enabled, an invalid access results in a SIGSEGV due to a #GP instead of a #PF. One such negative test fails because it is expecting X86_PF_INSTR to be set. Update the failing test to expect either a #GP or a #PF. Also, update the printed messages to show the trap number (denoting the type of fault) instead of assuming a #PF. Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- v12: - Pick up review tag. v11: - New patch (Fixes a vsyscall selftest failure) --- tools/testing/selftests/x86/test_vsyscall.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/x86/test_vsyscall.c b/tools/testing/se= lftests/x86/test_vsyscall.c index 05e1e6774fba..918eaec8bfbe 100644 --- a/tools/testing/selftests/x86/test_vsyscall.c +++ b/tools/testing/selftests/x86/test_vsyscall.c @@ -308,12 +308,13 @@ static void test_getcpu(int cpu) #ifdef __x86_64__ =20 static jmp_buf jmpbuf; -static volatile unsigned long segv_err; +static volatile unsigned long segv_err, segv_trapno; =20 static void sigsegv(int sig, siginfo_t *info, void *ctx_void) { ucontext_t *ctx =3D (ucontext_t *)ctx_void; =20 + segv_trapno =3D ctx->uc_mcontext.gregs[REG_TRAPNO]; segv_err =3D ctx->uc_mcontext.gregs[REG_ERR]; siglongjmp(jmpbuf, 1); } @@ -336,7 +337,8 @@ static void test_vsys_r(void) else if (can_read) ksft_test_result_pass("We have read access\n"); else - ksft_test_result_pass("We do not have read access: #PF(0x%lx)\n", segv_e= rr); + ksft_test_result_pass("We do not have read access (trap=3D%ld, error=3D0= x%lx)\n", + segv_trapno, segv_err); } =20 static void test_vsys_x(void) @@ -347,7 +349,7 @@ static void test_vsys_x(void) return; } =20 - ksft_print_msg("Make sure that vsyscalls really page fault\n"); + ksft_print_msg("Make sure that vsyscalls really cause a fault\n"); =20 bool can_exec; if (sigsetjmp(jmpbuf, 1) =3D=3D 0) { @@ -358,13 +360,14 @@ static void test_vsys_x(void) } =20 if (can_exec) - ksft_test_result_fail("Executing the vsyscall did not page fault\n"); - else if (segv_err & (1 << 4)) /* INSTR */ - ksft_test_result_pass("Executing the vsyscall page failed: #PF(0x%lx)\n", - segv_err); + ksft_test_result_fail("Executing the vsyscall did not fault\n"); + /* #GP or #PF (with X86_PF_INSTR) */ + else if ((segv_trapno =3D=3D 13) || ((segv_trapno =3D=3D 14) && (segv_err= & (1 << 4)))) + ksft_test_result_pass("Executing the vsyscall page failed (trap=3D%ld, e= rror=3D0x%lx)\n", + segv_trapno, segv_err); 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d="scan'208";a="190088965" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa006.jf.intel.com with ESMTP; 18 Nov 2025 10:31:58 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v13 8/8] x86/cpu: Enable LASS during CPU initialization Date: Tue, 18 Nov 2025 10:29:10 -0800 Message-ID: <20251118182911.2983253-9-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251118182911.2983253-1-sohil.mehta@intel.com> References: <20251118182911.2983253-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Linear Address Space Separation (LASS) mitigates a class of side-channel attacks that rely on speculative access across the user/kernel boundary. Enable LASS along with similar security features if the platform supports it. While at it, remove the comment above the SMAP/SMEP/UMIP/LASS setup instead of updating it, as the whole sequence is quite self-explanatory. Some EFI runtime and boot services may rely on 1:1 mappings in the lower half during early boot and even after SetVirtualAddressMap(). To avoid tripping LASS, the initial CR4 programming would need to be delayed until EFI has completely finished entering virtual mode (including efi_free_boot_services()). Also, LASS would need to be temporarily disabled while switching to efi_mm to avoid potential faults on stray runtime accesses. Similarly, legacy vsyscall page accesses are flagged by LASS resulting in a #GP (instead of a #PF). Without LASS, the #PF handler emulates the accesses and returns the appropriate values. Equivalent emulation support is required in the #GP handler with LASS enabled. In case of vsyscall XONLY (execute only) mode, the faulting address is readily available in the RIP which would make it easier to reuse the #PF emulation logic. For now, keep it simple and disable LASS if either of those are compiled in. Though not ideal, this makes it easier to start testing LASS support in some environments. In future, LASS support can easily be expanded to support EFI and legacy vsyscalls. Signed-off-by: Sohil Mehta Reviewed-by: Dave Hansen --- For reference, here are the relevant discussion links regarding EFI and legacy vsyscalls: https://lore.kernel.org/lkml/CAMj1kXGyTo=3D4Va1PevMQyCauEKSutfSPo6je0Ps09Ta= bhTe4zQ@mail.gmail.com/ https://lore.kernel.org/lkml/bbb68600-eea9-45d8-90d1-bc4619186a4d@intel.com/ https://lore.kernel.org/lkml/CAMj1kXFQaGaz37MNKXXjhUKy_mP-5teCDj80-hjUPHw4x= +TKrA@mail.gmail.com/ https://lore.kernel.org/lkml/d1b5698e-94ab-45a2-a472-4488895d55bb@intel.com/ v12: - Disable LASS when EFI support is compiled in. - Pick up review tag. v11: - Disable LASS if vsyscall emulation support is compiled in. - Drop Rick's review tag because of the new changes. --- arch/x86/kernel/cpu/common.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 02d97834a1d4..8afcbfd48a8a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -405,6 +405,28 @@ static __always_inline void setup_umip(struct cpuinfo_= x86 *c) cr4_clear_bits(X86_CR4_UMIP); } =20 +static __always_inline void setup_lass(struct cpuinfo_x86 *c) +{ + if (!cpu_feature_enabled(X86_FEATURE_LASS)) + return; + + /* + * Legacy vsyscall page access causes a #GP when LASS is active. + * Disable LASS because the #GP handler doesn't support vsyscall + * emulation. + * + * Also disable LASS when running under EFI, as some runtime and + * boot services rely on 1:1 mappings in the lower half. + */ + if (IS_ENABLED(CONFIG_X86_VSYSCALL_EMULATION) || + IS_ENABLED(CONFIG_EFI)) { + setup_clear_cpu_cap(X86_FEATURE_LASS); + return; + } + + cr4_set_bits(X86_CR4_LASS); +} + /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP= | X86_CR4_UMIP | X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; @@ -2015,10 +2037,10 @@ static void identify_cpu(struct cpuinfo_x86 *c) /* Disable the PN if appropriate */ squash_the_stupid_serial_number(c); =20 - /* Set up SMEP/SMAP/UMIP */ setup_smep(c); setup_smap(c); setup_umip(c); + setup_lass(c); =20 /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { --=20 2.43.0