From nobody Tue Dec 2 02:34:22 2025 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AADE35A94E; Tue, 18 Nov 2025 16:26:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763483172; cv=none; b=iJl7FAOMOnIVJQaoQnGfSDKj/eD7Cp1KEjSysPwZOkqTpoExOwPFcKZ90TFaoyWlYP/3MWLlwrZZ5gdLdDLRLIJuKu27jS9Rjv2afSTUULaxySoHGIcNsDaaoHhVRjTJutdA6RYYEHhbVMhwufl8aKYAmKmVTW2uTwiG/FKrRGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763483172; c=relaxed/simple; bh=QEA58ISPvgLYWLEqr1jJGitDS6An6AkVJmZcob3iw2c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M+0A3zlatfBq8rN8hGdYTq3ZytuAUxtlai2/KtAgeCx3HYKRIjVg6E0D3KBXUKsNLNahQDqeK0CvDEcIYEwiI98Er9zq1ss++w87pPIrJUU0ssldIoFTTJl3x4RrDAej/DnsRFRuBUnmSIoG7ExSFIM9HYfMJKpgevrlZu/AvBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from Mobilestation.localdomain (unknown [183.6.59.216]) by APP-03 (Coremail) with SMTP id rQCowAAXpdffnRxpmMQ0AQ--.31198S3; Wed, 19 Nov 2025 00:25:38 +0800 (CST) From: Yao Zihong To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ajones@ventanamicro.com, alexghiti@rivosinc.com, shuah@kernel.org, samuel.holland@sifive.com, evan@rivosinc.com, cleger@rivosinc.com, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, zhangyin2018@iscas.ac.cn, Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Cyan Yang , Inochi Amaoto , Nam Cao , Aleksa Paunovic , Jingwei Wang , Charlie Jenkins , Yunhui Cui , =?UTF-8?q?Miquel=20Sabat=C3=A9=20Sol=C3=A0?= , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , linux-doc@vger.kernel.org (open list:DOCUMENTATION) Subject: [PATCH v5 1/2] riscv: hwprobe: Expose Zicbop extension and its block size Date: Wed, 19 Nov 2025 00:23:24 +0800 Message-ID: <20251118162436.15485-2-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251118162436.15485-1-zihong.plct@isrc.iscas.ac.cn> References: <20251118162436.15485-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAAXpdffnRxpmMQ0AQ--.31198S3 X-Coremail-Antispam: 1UD129KBjvJXoWxGw1Utw1DGw17urW5Ar1DWrg_yoWrAw1kpF 4DZrsxWFs8Cw4xCFWxt3WkZrn5J3Z7Kw43KF1Uu3yUJFW7trWrXr9xtFsIyr1DtFyFva92 gF4agrZYya9rArDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUH2b7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r1j6r4UM28EF7xvwVC2z280aVCY 1x0267AKxVW8JVW8Jr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I 8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCF s4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFI xGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc7CjxVAKzI0EY4vE52x0 82I5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI 0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y 0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxV W8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1l IxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU07fHUUUUU U== X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" - Add `RISCV_HWPROBE_EXT_ZICBOP` to report the presence of the Zicbop extension. - Add `RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE` to expose the block size (in bytes) when Zicbop is supported. - Update hwprobe.rst to document the new extension bit and block size key, following the existing Zicbom/Zicboz style. Reviewed-by: Andrew Jones Signed-off-by: Yao Zihong --- Documentation/arch/riscv/hwprobe.rst | 8 +++++++- arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2f449c9b15bd..52f12af43b9d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -275,6 +275,9 @@ The following keys are defined: ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported= , as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar val= ues to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. @@ -369,4 +372,7 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Ac= cumulate - Instruction Extensions Specification. \ No newline at end of file + Instruction Extensions Specification. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicbop block in bytes. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 58f8dda73259..8c572a464719 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 14 +#define RISCV_HWPROBE_MAX_KEY 15 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 5d30a4fae37a..9cc508be54c5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -82,6 +82,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56) #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57) #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58) +#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 59) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -107,6 +108,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14 +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 199d13f86f31..6b33fd88bf3e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -122,6 +122,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCB); EXT_KEY(ZCMOP); EXT_KEY(ZICBOM); + EXT_KEY(ZICBOP); EXT_KEY(ZICBOZ); EXT_KEY(ZICNTR); EXT_KEY(ZICOND); @@ -302,6 +303,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM)) pair->value =3D riscv_cbom_block_size; break; + case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE: + pair->value =3D 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP)) + pair->value =3D riscv_cbop_block_size; + break; case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: pair->value =3D user_max_virt_addr(); break; --=20 2.47.2 From nobody Tue Dec 2 02:34:22 2025 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0335530F957; Tue, 18 Nov 2025 16:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 19 Nov 2025 00:25:47 +0800 (CST) From: Yao Zihong To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ajones@ventanamicro.com, alexghiti@rivosinc.com, shuah@kernel.org, samuel.holland@sifive.com, evan@rivosinc.com, cleger@rivosinc.com, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, zhangyin2018@iscas.ac.cn, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yunhui Cui , linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST FRAMEWORK) Subject: [PATCH v5 2/2] selftests/riscv: Add Zicbop prefetch test Date: Wed, 19 Nov 2025 00:23:25 +0800 Message-ID: <20251118162436.15485-3-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251118162436.15485-1-zihong.plct@isrc.iscas.ac.cn> References: <20251118162436.15485-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAAXpdffnRxpmMQ0AQ--.31198S4 X-Coremail-Antispam: 1UD129KBjvJXoW3JFWkZr47tFyUKry5uw4UArb_yoWfAFW8pF Zxur4IvF45ZF40qrWkJF1kCF1Fgrn2q3yUCrWrC345Zay7X3s8GFWkKay7AFyvkr97Zr1F vFn8AFWUCa1xGaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHab7Iv0xC_tr1lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUXwA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c 02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE 4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4 IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0En4kS14v26r4a6rW5MxkF7I0Ew4C26cxK6c8I j28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14 v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkG c2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8 JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTR89NsUU UUU X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Add selftests to cbo.c to verify Zicbop extension behavior, and split the previous `--sigill` mode into two options so they can be tested independently. The test checks: - That hwprobe correctly reports Zicbop presence and block size. - That prefetch instructions execute without exception on valid and NULL addresses when Zicbop is present. Signed-off-by: Yao Zihong Reviewed-by: Andrew Jones --- tools/testing/selftests/riscv/hwprobe/cbo.c | 165 ++++++++++++++++---- 1 file changed, 136 insertions(+), 29 deletions(-) diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/se= lftests/riscv/hwprobe/cbo.c index 5e96ef785d0d..6d99726aceac 100644 --- a/tools/testing/selftests/riscv/hwprobe/cbo.c +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c @@ -15,24 +15,31 @@ #include #include #include +#include =20 #include "hwprobe.h" #include "../../kselftest.h" =20 #define MK_CBO(fn) le32_bswap((uint32_t)(fn) << 20 | 10 << 15 | 2 << 12 | = 0 << 7 | 15) +#define MK_PREFETCH(fn) \ + le32_bswap(0 << 25 | (uint32_t)(fn) << 20 | 10 << 15 | 6 << 12 | 0 << 7 |= 19) =20 static char mem[4096] __aligned(4096) =3D { [0 ... 4095] =3D 0xa5 }; =20 -static bool illegal_insn; +static bool got_fault; =20 -static void sigill_handler(int sig, siginfo_t *info, void *context) +static void fault_handler(int sig, siginfo_t *info, void *context) { unsigned long *regs =3D (unsigned long *)&((ucontext_t *)context)->uc_mco= ntext; uint32_t insn =3D *(uint32_t *)regs[0]; =20 - assert(insn =3D=3D MK_CBO(regs[11])); + if (sig =3D=3D SIGILL) + assert(insn =3D=3D MK_CBO(regs[11])); =20 - illegal_insn =3D true; + if (sig =3D=3D SIGSEGV || sig =3D=3D SIGBUS) + assert(insn =3D=3D MK_PREFETCH(regs[11])); + + got_fault =3D true; regs[0] +=3D 4; } =20 @@ -45,39 +52,51 @@ static void sigill_handler(int sig, siginfo_t *info, vo= id *context) : : "r" (base), "i" (fn), "i" (MK_CBO(fn)) : "a0", "a1", "memory"); \ }) =20 +#define prefetch_insn(base, fn) \ +({ \ + asm volatile( \ + "mv a0, %0\n" \ + "li a1, %1\n" \ + ".4byte %2\n" \ + : : "r" (base), "i" (fn), "i" (MK_PREFETCH(fn)) : "a0", "a1"); \ +}) + static void cbo_inval(char *base) { cbo_insn(base, 0); } static void cbo_clean(char *base) { cbo_insn(base, 1); } static void cbo_flush(char *base) { cbo_insn(base, 2); } static void cbo_zero(char *base) { cbo_insn(base, 4); } +static void prefetch_i(char *base) { prefetch_insn(base, 0); } +static void prefetch_r(char *base) { prefetch_insn(base, 1); } +static void prefetch_w(char *base) { prefetch_insn(base, 3); } =20 static void test_no_cbo_inval(void *arg) { ksft_print_msg("Testing cbo.inval instruction remain privileged\n"); - illegal_insn =3D false; + got_fault =3D false; cbo_inval(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.inval\n"); + ksft_test_result(got_fault, "No cbo.inval\n"); } =20 static void test_no_zicbom(void *arg) { ksft_print_msg("Testing Zicbom instructions remain privileged\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_clean(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.clean\n"); + ksft_test_result(got_fault, "No cbo.clean\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_flush(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.flush\n"); + ksft_test_result(got_fault, "No cbo.flush\n"); } =20 static void test_no_zicboz(void *arg) { ksft_print_msg("No Zicboz, testing cbo.zero remains privileged\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_zero(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.zero\n"); + ksft_test_result(got_fault, "No cbo.zero\n"); } =20 static bool is_power_of_2(__u64 n) @@ -85,6 +104,51 @@ static bool is_power_of_2(__u64 n) return n !=3D 0 && (n & (n - 1)) =3D=3D 0; } =20 +static void test_zicbop(void *arg) +{ + struct riscv_hwprobe pair =3D { + .key =3D RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE, + }; + struct sigaction act =3D { + .sa_sigaction =3D &fault_handler, + .sa_flags =3D SA_SIGINFO + }; + struct sigaction dfl =3D { + .sa_handler =3D SIG_DFL + }; + cpu_set_t *cpus =3D (cpu_set_t *)arg; + __u64 block_size; + long rc; + + rc =3D sigaction(SIGSEGV, &act, NULL); + assert(rc =3D=3D 0); + rc =3D sigaction(SIGBUS, &act, NULL); + assert(rc =3D=3D 0); + + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, = 0); + block_size =3D pair.value; + ksft_test_result(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_ZICBOP_= BLOCK_SIZE && + is_power_of_2(block_size), "Zicbop block size\n"); + ksft_print_msg("Zicbop block size: %llu\n", block_size); + + got_fault =3D false; + prefetch_i(&mem[0]); + prefetch_r(&mem[0]); + prefetch_w(&mem[0]); + ksft_test_result(!got_fault, "Zicbop prefetch.* on valid address\n"); + + got_fault =3D false; + prefetch_i(NULL); + prefetch_r(NULL); + prefetch_w(NULL); + ksft_test_result(!got_fault, "Zicbop prefetch.* on NULL\n"); + + rc =3D sigaction(SIGBUS, &dfl, NULL); + assert(rc =3D=3D 0); + rc =3D sigaction(SIGSEGV, &dfl, NULL); + assert(rc =3D=3D 0); +} + static void test_zicbom(void *arg) { struct riscv_hwprobe pair =3D { @@ -100,13 +164,13 @@ static void test_zicbom(void *arg) is_power_of_2(block_size), "Zicbom block size\n"); ksft_print_msg("Zicbom block size: %llu\n", block_size); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_clean(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.clean\n"); + ksft_test_result(!got_fault, "cbo.clean\n"); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_flush(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.flush\n"); + ksft_test_result(!got_fault, "cbo.flush\n"); } =20 static void test_zicboz(void *arg) @@ -125,11 +189,11 @@ static void test_zicboz(void *arg) is_power_of_2(block_size), "Zicboz block size\n"); ksft_print_msg("Zicboz block size: %llu\n", block_size); =20 - illegal_insn =3D false; + got_fault =3D false; cbo_zero(&mem[block_size]); - ksft_test_result(!illegal_insn, "cbo.zero\n"); + ksft_test_result(!got_fault, "cbo.zero\n"); =20 - if (illegal_insn || !is_power_of_2(block_size)) { + if (got_fault || !is_power_of_2(block_size)) { ksft_test_result_skip("cbo.zero check\n"); return; } @@ -177,7 +241,19 @@ static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64= cbo) rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_= cpu, 0); assert(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_IMA_EXT_0); =20 - cbostr =3D cbo =3D=3D RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom"; + switch (cbo) { + case RISCV_HWPROBE_EXT_ZICBOZ: + cbostr =3D "Zicboz"; + break; + case RISCV_HWPROBE_EXT_ZICBOM: + cbostr =3D "Zicbom"; + break; + case RISCV_HWPROBE_EXT_ZICBOP: + cbostr =3D "Zicbop"; + break; + default: + ksft_exit_fail_msg("Internal error: invalid cbo %llu\n", cbo); + } =20 if (pair.value & cbo) ksft_exit_fail_msg("%s is only present on a subset of harts.\n" @@ -194,6 +270,7 @@ enum { TEST_ZICBOM, TEST_NO_ZICBOM, TEST_NO_CBO_INVAL, + TEST_ZICBOP, }; =20 static struct test_info { @@ -206,26 +283,51 @@ static struct test_info { [TEST_ZICBOM] =3D { .nr_tests =3D 3, test_zicbom }, [TEST_NO_ZICBOM] =3D { .nr_tests =3D 2, test_no_zicbom }, [TEST_NO_CBO_INVAL] =3D { .nr_tests =3D 1, test_no_cbo_inval }, + [TEST_ZICBOP] =3D { .nr_tests =3D 3, test_zicbop }, +}; + +static const struct option long_opts[] =3D { + {"zicbom-raises-sigill", no_argument, 0, 'm'}, + {"zicboz-raises-sigill", no_argument, 0, 'z'}, + {0, 0, 0, 0} }; =20 int main(int argc, char **argv) { struct sigaction act =3D { - .sa_sigaction =3D &sigill_handler, + .sa_sigaction =3D &fault_handler, .sa_flags =3D SA_SIGINFO, }; struct riscv_hwprobe pair; unsigned int plan =3D 0; cpu_set_t cpus; long rc; - int i; - - if (argc > 1 && !strcmp(argv[1], "--sigill")) { - rc =3D sigaction(SIGILL, &act, NULL); - assert(rc =3D=3D 0); - tests[TEST_NO_ZICBOZ].enabled =3D true; - tests[TEST_NO_ZICBOM].enabled =3D true; - tests[TEST_NO_CBO_INVAL].enabled =3D true; + int i, opt, long_index; + + long_index =3D 0; + + while ((opt =3D getopt_long(argc, argv, "mz", long_opts, &long_index)) != =3D -1) { + switch (opt) { + case 'm': + tests[TEST_NO_ZICBOM].enabled =3D true; + tests[TEST_NO_CBO_INVAL].enabled =3D true; + rc =3D sigaction(SIGILL, &act, NULL); + assert(rc =3D=3D 0); + break; + case 'z': + tests[TEST_NO_ZICBOZ].enabled =3D true; + tests[TEST_NO_CBO_INVAL].enabled =3D true; + rc =3D sigaction(SIGILL, &act, NULL); + assert(rc =3D=3D 0); + break; + case '?': + fprintf(stderr, + "Usage: %s [--zicbom-raises-sigill|-m] [--zicboz-raises-sigill|-z]\n", + argv[0]); + exit(1); + default: + break; + } } =20 rc =3D sched_getaffinity(0, sizeof(cpu_set_t), &cpus); @@ -253,6 +355,11 @@ int main(int argc, char **argv) check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM); } =20 + if (pair.value & RISCV_HWPROBE_EXT_ZICBOP) + tests[TEST_ZICBOP].enabled =3D true; + else + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOP); + for (i =3D 0; i < ARRAY_SIZE(tests); ++i) plan +=3D tests[i].enabled ? tests[i].nr_tests : 0; =20 --=20 2.47.2