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Tue, 18 Nov 2025 06:06:44 -0800 From: Akhil R To: , , , , , , , , CC: , , , Subject: [PATCH v13 2/6] i2c: tegra: Use separate variables for fast and fastplus Date: Tue, 18 Nov 2025 19:36:16 +0530 Message-ID: <20251118140620.549-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251118140620.549-1-akhilrajeev@nvidia.com> References: <20251118140620.549-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|SJ2PR12MB9210:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ec95162-a107-4de1-6417-08de26abc129 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?PRAhR7eWmaBRy0vtemzQpSQ27Dclf6xrCLOll6n29nLLRPjjKG/UG6TTIlAF?= =?us-ascii?Q?FsTqNn36a71DnNn/uo5AaiD+Kqvmkb1mt1CO70lfxlzwUWUlXOzL/O30Fwgx?= =?us-ascii?Q?GHge5Sp7yyj6qR3F+iNcwuUkUX/29lrT2dM36J2CkpyHdZamDU4a6cqs3ciL?= =?us-ascii?Q?I4vq/E2JWhNnT8//gEhVgByQBmfXJOAUAsv7Svoznojcl0B6ApM83gG3a5jS?= =?us-ascii?Q?PbI+R8DfJsbu4ngnA6UXmhG49lnd/w52TJfcVDSKDA4z7zO/PMDAHO995rHJ?= =?us-ascii?Q?HpgGZzL7H50kdTPk+lHxeDILdLrjvqKJ3mUWU8j8oP7LU3FA1VTdAVFCoCNB?= =?us-ascii?Q?hc7uzx04HGJojp82SK+F5ukVIWTWWvVZXMWTHKU5tPHMZgELRrBdkDWcZ6cz?= =?us-ascii?Q?wAugVoLXX0FQvc7sanIu5usisq9o0hGwEaRjtoY6Z73hoDyBkmqyy3mhH9Lz?= =?us-ascii?Q?YIhCC0LIzuseWgyqrAICGtQe93MmhWdBQD5D9sj6janLIqmZlmdTjB91rjJI?= =?us-ascii?Q?TwJ/zq9g5ehRng0cTDCcjGPTMVzaWyUnwaBi+CxfKeDnUNz+VYoE/2EFyE/+?= =?us-ascii?Q?sjPdV8uu5TVoFXJwBT+NzbAf1nTsNtfeVibU/ZRIBSnjHHDJPhBtQu7idIIg?= =?us-ascii?Q?wd5XziH/MxlBT4K/W1dCHEKfI+7ejA+myzFW08fV5xUxiSbrEJuydIzazK+a?= =?us-ascii?Q?+T0jN3Hw5K+bxZnPhG4Bq7X3uWo0IxvUu+CtORFcjdOBMGQlEvx1KU8ioM2A?= =?us-ascii?Q?NH4UXfDCJjuyQtk0LcZYeUTY4+v9tOLoH5tiKFV7UIvxyrrQB1nihGmY6gSm?= =?us-ascii?Q?wY6R5qG6+jJtit7uCUvFxM17bUmDBFXm76UpJ7mOttGH1mwU2ZahCdhfDWtK?= =?us-ascii?Q?hzHPbke9FiGaDX7wa/OgQu6YQdT9+lXhzOycjamlZBiecldSRRCpQaKSFahS?= =?us-ascii?Q?21gY4V1aQEzyrZDOsptKTLBDl0OOOI7239CXBjkbrNTWYNbjmFR9MoUFs9qJ?= =?us-ascii?Q?s+Y6I5NtIFMB7eWV+D51giqT9Fh4kUAlVQKPwx5E9WVSw/c6blZsjWKzYFP4?= =?us-ascii?Q?ID3BcBVMtWVu4dMW1ENo2YTI4SnS6RbVC1VL/9NaOo4uAhTtYYRVchRAxPmv?= =?us-ascii?Q?nfu0pXCKArhTbvQcWRFKiMJTV0STeajEKECBvCwyKBERK3FEMLuS7nKKW8Aw?= =?us-ascii?Q?XXhtZjxtLCxStMkcDc9YoQuBMwBOJiwl+YB6TdpkyzR4NaxXc3ecK847k4ud?= =?us-ascii?Q?2i2y6NumZ9LNFRoVx47wCiyX9gp6ZhMaPu/BAQoDrEWoaVPZmmK3boCWLw/q?= =?us-ascii?Q?cx8dxuynxGQ2i0370YzGGJXHfIyGhNMEp7LzDeSPXW24UPydh+Q+5oG+h1Dx?= =?us-ascii?Q?IZ7nhXQJV6RbXnsHOWCV4r7dTIUI7SrYGKKbekbnxUAcPjwcLHzxPVhnTkh1?= =?us-ascii?Q?ugbhNNbO5RqNfn1rXLJqjwWlBRxt91JhYWnWxoUL/k/Usbl+XbeYf2RJyyzS?= =?us-ascii?Q?cNGa0V7QKbbTf7k1fAiReYToTELW72TjsIg7RbQo/uNqCEZuSYPZNGwETS+I?= =?us-ascii?Q?kWnnn5tEvADen/ba0Mo=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 14:07:05.3999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ec95162-a107-4de1-6417-08de26abc129 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9210 Content-Type: text/plain; charset="utf-8" The current implementation uses a single value of THIGH, TLOW and setup hold time for both fast and fastplus. But these values can be different for each speed mode and should be using separate variables. Split the variables used for fast and fast plus mode. Signed-off-by: Akhil R Reviewed-by: Jon Hunter Acked-by: Thierry Reding --- drivers/i2c/busses/i2c-tegra.c | 119 ++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 46 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index bd26b232ffb3..c0382c9a0430 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -196,12 +196,16 @@ enum msg_end_type { * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. * @tlow_std_mode: Low period of the clock in standard mode. * @thigh_std_mode: High period of the clock in standard mode. - * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus mod= es. - * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus m= odes. + * @tlow_fast_mode: Low period of the clock in fast mode. + * @thigh_fast_mode: High period of the clock in fast mode. + * @tlow_fastplus_mode: Low period of the clock in fast-plus mode. + * @thigh_fastplus_mode: High period of the clock in fast-plus mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop condi= tions * in standard mode. - * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and= stop - * conditions in fast/fast-plus modes. + * @setup_hold_time_fast_mode: Setup and hold time for start and stop + * conditions in fast mode. + * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop + * conditions in fast-plus mode. * @setup_hold_time_hs_mode: Setup and hold time for start and stop condit= ions * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the= tuned @@ -224,10 +228,13 @@ struct tegra_i2c_hw_feature { bool has_apb_dma; u32 tlow_std_mode; u32 thigh_std_mode; - u32 tlow_fast_fastplus_mode; - u32 thigh_fast_fastplus_mode; + u32 tlow_fast_mode; + u32 thigh_fast_mode; + u32 tlow_fastplus_mode; + u32 thigh_fastplus_mode; u32 setup_hold_time_std_mode; - u32 setup_hold_time_fast_fast_plus_mode; + u32 setup_hold_time_fast_mode; + u32 setup_hold_time_fastplus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; }; @@ -677,25 +684,21 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_d= ev) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); =20 - switch (t->bus_freq_hz) { - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: - default: - tlow =3D i2c_dev->hw->tlow_fast_fastplus_mode; - thigh =3D i2c_dev->hw->thigh_fast_fastplus_mode; - tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) - non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_plus_mode; - else - non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; - break; - - case 0 ... I2C_MAX_STANDARD_MODE_FREQ: + if (t->bus_freq_hz <=3D I2C_MAX_STANDARD_MODE_FREQ) { tlow =3D i2c_dev->hw->tlow_std_mode; thigh =3D i2c_dev->hw->thigh_std_mode; tsu_thd =3D i2c_dev->hw->setup_hold_time_std_mode; non_hs_mode =3D i2c_dev->hw->clk_divisor_std_mode; - break; + } else if (t->bus_freq_hz <=3D I2C_MAX_FAST_MODE_FREQ) { + tlow =3D i2c_dev->hw->tlow_fast_mode; + thigh =3D i2c_dev->hw->thigh_fast_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_mode; + non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; + } else { + tlow =3D i2c_dev->hw->tlow_fastplus_mode; + thigh =3D i2c_dev->hw->thigh_fastplus_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_fastplus_mode; + non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_plus_mode; } =20 /* make sure clock divisor programmed correctly */ @@ -1496,10 +1499,13 @@ static const struct tegra_i2c_hw_feature tegra20_i2= c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1521,10 +1527,13 @@ static const struct tegra_i2c_hw_feature tegra30_i2= c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1546,10 +1555,13 @@ static const struct tegra_i2c_hw_feature tegra114_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1571,10 +1583,13 @@ static const struct tegra_i2c_hw_feature tegra124_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, }; @@ -1596,10 +1611,13 @@ static const struct tegra_i2c_hw_feature tegra210_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0, - .setup_hold_time_fast_fast_plus_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, }; @@ -1621,10 +1639,13 @@ static const struct tegra_i2c_hw_feature tegra186_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x3, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0, - .setup_hold_time_fast_fast_plus_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, }; @@ -1646,10 +1667,13 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x8, .thigh_std_mode =3D 0x7, - .tlow_fast_fastplus_mode =3D 0x2, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x08080808, - .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, }; @@ -1671,10 +1695,13 @@ static const struct tegra_i2c_hw_feature tegra256_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x8, .thigh_std_mode =3D 0x7, - .tlow_fast_fastplus_mode =3D 0x3, - .thigh_fast_fastplus_mode =3D 0x3, + .tlow_fast_mode =3D 0x3, + .thigh_fast_mode =3D 0x3, + .tlow_fastplus_mode =3D 0x3, + .thigh_fastplus_mode =3D 0x3, .setup_hold_time_std_mode =3D 0x08080808, - .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, }; --=20 2.50.1