From nobody Tue Dec 2 02:56:49 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BADD4258EE0; Tue, 18 Nov 2025 12:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470430; cv=none; b=khuPDPBAnf1RI5HxnH2yLXEwqQFG5y60mHvp3JdEVJ0xpGVVt69VTER3oMX81p2b6CE50pw/6sxcXdSx7SWvoa3elIOqLtOFGI6KNPJLAryWNXyKPu4y/uA+ml1L0CwH/ttRyW1vTcnktcbH244uSTNKNdVRkPcdG8urxCa+BFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470430; c=relaxed/simple; bh=Em8rtBBVZ5qZ660u1e4p+eLQpHkxThm7xuHiiM4rSPA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ddM8nN7g+G83A+uSZ2qdzTNNyAszHHwVW78/Gh1D+0+HqvFh7Ljw43ZDDFrbyDsKxTqUSZiDmlqWtH2AGCZYqZbCbjeGmv0vI2CErq0RCll2cUDqHO/5YluSrf+6D0H/Tc0x7WxmXnBSDaCrkkCOjnUeIF8VNIMi69CQPpo3X2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=VGMNlQYJ; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="VGMNlQYJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=JCRTY/2suQAMAMf nvyV08IOawQOtNTtJ61eRKrX/QPU=; b=VGMNlQYJ0ME2LYTvcM/sy5oAm3yLY0I isUQgQMdoe6fAQcJ6j94+K3mjpStlX61M8tyHmFGucGifpDw3BGbZWUa988pIZ5S S8xPjth98cBKJV+5TNJnPcxk6ZYLkzzf+NsFP6PypkKvV9PcmonorcXlPHkACmLb oXqK7QjpOz5g= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wD3E8H1axxpyxYsBA--.3548S8; Tue, 18 Nov 2025 20:52:17 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function. Date: Tue, 18 Nov 2025 07:51:46 -0500 Message-Id: <20251118125148.95603-7-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S8 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4DKrWUCr1fWF4kKr4xCrg_yoWxAw1rp3 yfCF1rtr17tr1Svrs2kFs5WFyfAryxW3y2vr9rK39ava1UGa4vgrykta1FyFy5CFn3ZFsr X3srZ3WUCanrJaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JjeWlgUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwAF8UGkcbAGt4gAA36 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 adds power, current, and limit registers. The ina3221_read_value function has been refactored to adapt to the new register data reading format. Each channel supports four new alert trigger modes, but only one trigger mode can be active at any given time. Alert values are stored in the same register. The sq52210_alert_limit_write function has been added to write alert threshold values and configure alert source type. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 1d589d402b52..9a25a1b40856 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -66,6 +66,14 @@ #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6)) +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5)) +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4)) + +#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13)) +#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10)) +#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7)) +#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4)) =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221= _data *ina) cvrf, cvrf, wait, wait * 2); } =20 +static const u32 alert_groups[] =3D { + SQ52210_MASK_ALERT_CHANNEL1, + SQ52210_MASK_ALERT_CHANNEL2, + SQ52210_MASK_ALERT_CHANNEL3, +}; + +static const u8 limit_regs[] =3D { + SQ52210_ALERT_LIMIT1, + SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, +}; + static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, int *val) { @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *in= a, unsigned int reg, =20 /* * Shunt Voltage Sum register has 14-bit value with 1-bit shift + * Current registers have 15-bit value + * Power registers have 16-bit value + * ALERT_LIMIT registers have 16-bit value with 3-bit shift * Other Shunt Voltage registers have 12 bits with 3-bit shift */ - if (reg =3D=3D INA3221_SHUNT_SUM || reg =3D=3D INA3221_CRIT_SUM) + switch (reg) { + case INA3221_SHUNT_SUM: + case INA3221_CRIT_SUM: *val =3D sign_extend32(regval >> 1, 14); - else + break; + case SQ52210_CURRENT1: + case SQ52210_CURRENT2: + case SQ52210_CURRENT3: + *val =3D sign_extend32(regval, 15); + break; + case SQ52210_POWER1: + case SQ52210_POWER2: + case SQ52210_POWER3: + *val =3D regval; + break; + case INA3221_BUS1: + case INA3221_BUS2: + case INA3221_BUS3: + case INA3221_SHUNT1: + case INA3221_SHUNT2: + case INA3221_SHUNT3: + case INA3221_WARN1: + case INA3221_WARN2: + case INA3221_WARN3: + case INA3221_CRIT1: + case INA3221_CRIT2: + case INA3221_CRIT3: *val =3D sign_extend32(regval >> 3, 12); - + break; + case SQ52210_ALERT_LIMIT1: + case SQ52210_ALERT_LIMIT2: + case SQ52210_ALERT_LIMIT3: + if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK) + *val =3D sign_extend32(regval, 15); + else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK + | SQ52210_ALERT_ALL_BUL_MASK)) + *val =3D regval >> 3; + else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK) + *val =3D regval; + break; + default: + *val =3D 0; + return -EOPNOTSUPP; + }; return 0; } =20 @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, i= nt channel, long val) +{ + struct regmap *regmap =3D ina->regmap; + int item =3D channel % INA3221_NUM_CHANNELS; + u8 limit_reg; + u32 alert_group, alert_mask =3D 0; + int regval =3D 0; + int ret; + + if (item >=3D ARRAY_SIZE(alert_groups) || val < 0) + return -EINVAL; + + alert_group =3D alert_groups[item]; + limit_reg =3D limit_regs[item]; + + /* Clear alerts for this channel group first */ + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0); + if (ret) + return ret; + + /* Determine alert type and calculate register value */ + switch (attr) { + /* + * The alert warning logic is implemented by comparing the limit register= values + * with the corresponding alert source register values. Since the current= register + * is a 15-bit signed register and the power register is a 16-bit unsigned + * register, but the lower 3 bits of the limit register default to 0, the= lower + * 3 bits will be forced to 0 when setting SUL and POL warning values. + * Formula to convert register value: + * bus_voltage: (regval / 8mV) << 3 + * current: (regval / current_lsb) & 0xfff8 + * power: (regval / current_lsb) & 0xfff8 + */ + case hwmon_curr_lcrit: + /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */ + alert_mask =3D BIT(15 - item); + /* Current Register, signed register, result in mA */ + regval =3D DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8; + regval =3D clamp_val(regval, -32760, 32760); + break; + case hwmon_in_crit: + /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */ + alert_mask =3D BIT(12 - item); + /* Bus Register, signed register, result in mV */ + regval =3D clamp_val(val, -32760, 32760); + break; + case hwmon_in_lcrit: + /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */ + alert_mask =3D BIT(9 - item); + /* Bus Register, signed register, result in mV */ + regval =3D clamp_val(val, -32760, 32760); + break; + case hwmon_power_crit: + /* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */ + alert_mask =3D BIT(6 - item); + /* Power Register, unsigned register, result in mW */ + regval =3D DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8; + regval =3D clamp_val(regval, 0, 65528); + break; + default: + /* For unsupported attributes, just clear the configuration */ + ina->alert_type_select &=3D ~alert_group; + return -EOPNOTSUPP; + } + + /* Write limit register value */ + ret =3D regmap_write(regmap, limit_reg, regval); + if (ret) + return ret; + + /* Update alert configuration if limit value is non-zero */ + if (regval) { + ina->alert_type_select =3D (ina->alert_type_select & ~alert_group) | ale= rt_mask; + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, + alert_group, alert_mask); + } else { + ina->alert_type_select &=3D ~alert_group; + } + + return ret; +} + static int ina3221_write_chip(struct device *dev, u32 attr, long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); --=20 2.17.1