From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20BF223EA84; Tue, 18 Nov 2025 12:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470384; cv=none; b=PnBnj9E4pen9aw3CKwru8tsKNaXMOxUDLT1PpHFPDPyYg2bkeHOUFYTtqgDjsYZCebUrBsvrBml8Fcvo2KUtC3qiPTqTDiiyQrXck7DkisRMlKofkKbWPuehIZ9ZGK9BDXt/ZlqPpQQp0LqJm1bkz+v8dx02XD2Iev21MGXu91I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470384; c=relaxed/simple; bh=3IwuF4EV9QHK3caWErWLq/KOYmN93yIt0Vkckezx/h0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=L7FTM7RDfb7ax6tJ3t8UBj6zzg+s48Cf3+bEFRMvlPR4d58zfFvSgPTIe0ztnaSR8fjg3Pyp4AMojooU7TsvfriSABXUsMWQqZYZQ4zm7UjrVe5JuW31pp3M1O16FgKwV+FhF4BOYiXilerP0XPtdVqtUsRqwtrwUeA4nMLag5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=orFJ0C/c; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="orFJ0C/c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=v+TEgHN9AHB2tSt vMr5GijsmfitBgxsTIsKMWoDx9Yg=; b=orFJ0C/cLZ4/Lc7fweOJIGWMr1FDyd0 NT8iYpwxhWEfENTLTq8moaumVslj4iCgDo91m4qw3AALdUv/7sS2/J0USRqaSiIw KPLtUquTOwYOLXo6CiinvmsBr72bWsm88qfnwDX124FRjamDibGZ0ntoRJtCBWMU mqm3pFZk3m1E= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wD3E8H1axxpyxYsBA--.3548S3; Tue, 18 Nov 2025 20:52:10 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Wenliang Yan , Jonathan Corbet , linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210 Date: Tue, 18 Nov 2025 07:51:41 -0500 Message-Id: <20251118125148.95603-2-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S3 X-Coremail-Antispam: 1Uf129KBjvdXoW7GrW5CF4rXrW7Gr4UWw15Jwb_yoWfWwc_CF s7Xr4rAFZ8JFWFgw1vy3yxJr1rta1SkFn7Aw10kFs8Cw1rZr909aykX3srAFy7uFW3uF1F vFs5GrZ5JanrGjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7VUbomh7UUUUU== X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwBp6Tmkca-qs8gAA3U Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a compatible string for sq52210. The sq52210 is forward compatible with INA3221 and incorporates alert registers to implement four additional alert functions, all of which require no board-level configuration. Signed-off-by: Wenliang Yan --- Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Docu= mentation/devicetree/bindings/hwmon/ti,ina3221.yaml index 5f10f1207d69..3bdd8dfb7a36 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml @@ -12,7 +12,9 @@ maintainers: =20 properties: compatible: - const: ti,ina3221 + enum: + - silergy,sq52210 + - ti,ina3221 =20 reg: maxItems: 1 --=20 2.17.1 From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A4E2580EE; Tue, 18 Nov 2025 12:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470431; cv=none; b=QOhGQpLUT2q41+mgxZ3vHmlpRusaN3YXgnf/ReOSWa0D556xo4UILe3z/WfCe3e8inf5U95noixcF4nKBcmG63VWK76mhwUQhtjlsfyrpcAlgms2jcRHhv11F/MKFJOAjPwkmKptubwcoI/tIEEk6X4Ay+a0y3xiyDxjHWZ95Rk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470431; c=relaxed/simple; bh=yyRpSRt2XpliHBt1AW/V4VfYQBqCxqaKqY7JEeIWjjs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=FvhrPpV1cE2OhjTkDDV8G1AEuUEaNxPtibNCDccv9l+/yd8/7s74GSvKXIQIaU8C8LYW2YorP0REjoONwqKdmAV1s0H/tEOmFQw6tA7UmO1A45SwCHTZszsp1K/QiDiiqTZ0Fu1Uy0M7ZKbgGV/FF13J4SZ2bRnfCQi71ry0y9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=cJrgzy20; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="cJrgzy20" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=IFaa8TjMQuUxKfS ecCtgY0np35W5UehqzhG+E4SNZcU=; b=cJrgzy20z3yFNfdliorTsYLkVWPce2v FMv8ElYxRcHsB+oceJRLp/6UYz7TSWY7WUaEAE2LEuAGg5fga8bkFWDGbYHyF2mb e85XD01kFKqKNvpl3TEC4cWl0NtjYMYWrlGNBKOfBOQCNFlT/ErGMK/aqyB0wjzb ZTQr7pZKXd8g= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wD3E8H1axxpyxYsBA--.3548S4; Tue, 18 Nov 2025 20:52:11 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] hwmon: (ina3221) Add support for SQ52210 Date: Tue, 18 Nov 2025 07:51:42 -0500 Message-Id: <20251118125148.95603-3-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFW8Xr1UJFWDXrW3AF1kXwb_yoW5Zw4rpa n5Aa4rtr45Xr4Ig3yfKFs5tF15tr4xG3yIvrnrK3yIva1DAry0gF1rKw4qyF98ZFyfZF47 X34Iy3y8uwnrJr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRbzV8UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCvxt6Tmkca-uGnQAA3u Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 is compatible with INA3221, but also includes current registers, power registers, and registers related to alerts. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 5ecc68dcf169..47ef4fe694ea 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -34,6 +34,17 @@ #define INA3221_SHUNT_SUM 0x0d #define INA3221_CRIT_SUM 0x0e #define INA3221_MASK_ENABLE 0x0f +#define SQ52210_ALERT_CONFIG 0x12 +#define SQ52210_CALIBRATION 0x14 +#define SQ52210_CURRENT1 0x15 +#define SQ52210_CURRENT2 0x16 +#define SQ52210_CURRENT3 0x17 +#define SQ52210_POWER1 0x18 +#define SQ52210_POWER2 0x19 +#define SQ52210_POWER3 0x1A +#define SQ52210_ALERT_LIMIT1 0x1B +#define SQ52210_ALERT_LIMIT2 0x1C +#define SQ52210_ALERT_LIMIT3 0x1D =20 #define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) #define INA3221_CONFIG_MODE_POWERDOWN 0 @@ -108,8 +119,11 @@ struct ina3221_input { bool summation_disable; }; =20 +enum ina3221_ids { ina3221, sq52210 }; + /** * struct ina3221_data - device specific information + * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device * @fields: Register fields of the device @@ -120,6 +134,8 @@ struct ina3221_input { * @single_shot: running in single-shot operating mode */ struct ina3221_data { + enum ina3221_ids chip; + struct device *pm_dev; struct regmap *regmap; struct regmap_field *fields[F_MAX_FIELDS]; @@ -734,6 +750,7 @@ static const struct regmap_range ina3221_yes_ranges[] = =3D { regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM), regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), + regmap_reg_range(SQ52210_ALERT_CONFIG, SQ52210_POWER3), }; =20 static const struct regmap_access_table ina3221_volatile_table =3D { @@ -818,13 +835,18 @@ static int ina3221_probe(struct i2c_client *client) struct device *dev =3D &client->dev; struct ina3221_data *ina; struct device *hwmon_dev; + enum ina3221_ids chip; char name[32]; int i, ret; =20 + chip =3D (uintptr_t)i2c_get_match_data(client); + ina =3D devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); if (!ina) return -ENOMEM; =20 + ina->chip =3D chip; + ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { dev_err(dev, "Unable to allocate register map\n"); @@ -996,13 +1018,21 @@ static DEFINE_RUNTIME_DEV_PM_OPS(ina3221_pm, ina3221= _suspend, ina3221_resume, NULL); =20 static const struct of_device_id ina3221_of_match_table[] =3D { - { .compatible =3D "ti,ina3221", }, + { + .compatible =3D "silergy,sq52210", + .data =3D (void *)sq52210 + }, + { + .compatible =3D "ti,ina3221", + .data =3D (void *)ina3221 + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, ina3221_of_match_table); =20 static const struct i2c_device_id ina3221_ids[] =3D { - { "ina3221" }, + { "ina3221", ina3221 }, + { "sq52210", sq52210 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, ina3221_ids); --=20 2.17.1 From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63914262D0B; Tue, 18 Nov 2025 12:53:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470394; 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dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ERTyD3hB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=WuEHeMrivFoEujO cr/xi2G/pphMy6vZiBBA1L4Xwt4w=; b=ERTyD3hB3IFnQZTWP6B2WI4SSa7YOjI 9DX5QQJTrHyyHLUGd91Fa4BpEDUvJCUiUN8jPMnpIV6DqAne1GTBizsNFrMHlbkK 6iBVDVElDoe4Xf5WjLaQcak+IsMWJ2d8IP3+F8Pt76kBVY+pjcPznbWjuVxjEKUW htsjYTqGhfSE= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wD3E8H1axxpyxYsBA--.3548S5; Tue, 18 Nov 2025 20:52:12 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] hwmon: (ina3221) Pre-calculate current and power LSB Date: Tue, 18 Nov 2025 07:51:43 -0500 Message-Id: <20251118125148.95603-4-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S5 X-Coremail-Antispam: 1Uf129KBjvJXoW3JryUAFy5JF4rtw4kAw13urg_yoW7Xry3pF 4fKryrta40qF1fKa9Ikw4xGF1rtr97Jr47KrZrGw1IqFsFkryqk3yrJFyDtFy5Ary5ZF17 X3y7tr4Duws2yaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRYLvtUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwBx7T2kca-ytLwAA3I Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The LSB for current and power can be pre-calculated for data read/write operations. The current LSB is determined by the calibration value and shunt resistor value, with the calibration value fixed within the driver. The power LSB can be derived from the current LSB. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 85 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 47ef4fe694ea..b5fa984a5a25 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -67,6 +67,7 @@ =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 +#define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ =20 enum ina3221_fields { /* Configuration */ @@ -121,8 +122,16 @@ struct ina3221_input { =20 enum ina3221_ids { ina3221, sq52210 }; =20 +struct ina3221_config { + bool has_current; /* chip has internal current reg */ + bool has_power; /* chip has internal power reg */ + int calibration_value; /* calculate current_lsb */ + int power_lsb_factor; +}; + /** * struct ina3221_data - device specific information + * @config: Used to store characteristics of different chips * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device @@ -131,9 +140,12 @@ enum ina3221_ids { ina3221, sq52210 }; * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster + * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode */ struct ina3221_data { + const struct ina3221_config *config; enum ina3221_ids chip; =20 struct device *pm_dev; @@ -143,10 +155,30 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + long current_lsb_uA; + long power_lsb_uW; =20 bool single_shot; }; =20 +static const struct ina3221_config ina3221_config[] =3D { + [ina3221] =3D { + .has_current =3D false, + .has_power =3D false, + }, + [sq52210] =3D { + .has_current =3D true, + .has_power =3D true, + /* + * With this default value configuration, + * the following formula can be obtained: + * Current_LSB =3D Shunt_LSB / Rshunt + */ + .calibration_value =3D 256, + .power_lsb_factor =3D 20, + }, +}; + static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channe= l) { /* Summation channel checks shunt resistor values */ @@ -697,6 +729,25 @@ static const struct hwmon_chip_info ina3221_chip_info = =3D { }; =20 /* Extra attribute groups */ + +/* + * Calculate the value corresponding to one LSB of the current and + * power registers. + * formula : Current_LSB =3D Shunt_LSB / Rshunt + * Power_LSB =3D power_lsb_factor * Current_LSB + */ +static int ina3221_set_shunt(struct ina3221_data *ina, unsigned long val) +{ + if (!val || val > SQ52210_SHUNT_LSB) + return -EINVAL; + + ina->current_lsb_uA =3D DIV_ROUND_CLOSEST(SQ52210_SHUNT_LSB, val); + ina->power_lsb_uW =3D ina->config->power_lsb_factor * + ina->current_lsb_uA; + + return 0; +} + static ssize_t ina3221_shunt_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -730,6 +781,17 @@ static ssize_t ina3221_shunt_store(struct device *dev, /* Update summation_shunt_resistor for summation channel */ ina->summation_shunt_resistor =3D ina3221_summation_shunt_resistor(ina); =20 + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + if (ina->config->has_current) { + ret =3D ina3221_set_shunt(ina, val); + if (ret < 0) + return ret; + } + } return count; } =20 @@ -846,6 +908,7 @@ static int ina3221_probe(struct i2c_client *client) return -ENOMEM; =20 ina->chip =3D chip; + ina->config =3D &ina3221_config[chip]; =20 ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { @@ -892,6 +955,16 @@ static int ina3221_probe(struct i2c_client *client) ina->summation_channel_control |=3D BIT(14 - i); } =20 + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + ret =3D ina3221_set_shunt(ina, ina->summation_shunt_resistor); + if (ret < 0) + return ret; + } + ina->pm_dev =3D dev; dev_set_drvdata(dev, ina); =20 @@ -1009,6 +1082,18 @@ static int ina3221_resume(struct device *dev) dev_err(dev, "Unable to control summation channel\n"); return ret; } + /* + * The calibration register can only be enabled when all + * shunt resistor values are identical. + */ + if (ina->config->has_current) { + ret =3D regmap_write(ina->regmap, SQ52210_CALIBRATION, + ina->config->calibration_value); + if (ret) { + dev_err(dev, "Unable to set calibration value\n"); + return ret; + } + } } =20 return 0; --=20 2.17.1 From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5987125485A; Tue, 18 Nov 2025 12:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470431; cv=none; b=kcJezdCOYbTRdDnV4P1YyH8LEZ6JYY1PVwb2tuy9Xm4A/5aMrPFmG4iUNGwOMtpoI0sZgCW3hrAicBJ69q4tf4y/JPc3FPK5DNX4EYYKYv/6La+JneZOsJksdLKTcD1ZER93y1e0S3I/BFYlL55+x5Qz6oloSoPbxmxugDqPUs4= ARC-Message-Signature: i=1; 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charset="utf-8" Add alert configuration during chip initialization. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index b5fa984a5a25..8ea75f407055 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -65,6 +65,8 @@ =20 #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 +#define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) + #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 #define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ @@ -123,6 +125,7 @@ struct ina3221_input { enum ina3221_ids { ina3221, sq52210 }; =20 struct ina3221_config { + bool has_alerts; /* chip supports alerts and limits */ bool has_current; /* chip has internal current reg */ bool has_power; /* chip has internal power reg */ int calibration_value; /* calculate current_lsb */ @@ -140,6 +143,7 @@ struct ina3221_config { * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @alert_type_select: Used to store the alert trigger type * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode @@ -155,6 +159,7 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + u32 alert_type_select; long current_lsb_uA; long power_lsb_uW; =20 @@ -163,10 +168,12 @@ struct ina3221_data { =20 static const struct ina3221_config ina3221_config[] =3D { [ina3221] =3D { + .has_alerts =3D false, .has_current =3D false, .has_power =3D false, }, [sq52210] =3D { + .has_alerts =3D true, .has_current =3D true, .has_power =3D true, /* @@ -780,7 +787,6 @@ static ssize_t ina3221_shunt_store(struct device *dev, =20 /* Update summation_shunt_resistor for summation channel */ ina->summation_shunt_resistor =3D ina3221_summation_shunt_resistor(ina); - /* * The current and power registers can only be used when * all enabled channels have identical shunt resistors @@ -1096,6 +1102,17 @@ static int ina3221_resume(struct device *dev) } } =20 + /* Restore alert config register value to hardware */ + if (ina->config->has_alerts) { + ret =3D regmap_update_bits(ina->regmap, SQ52210_ALERT_CONFIG, + SQ52210_ALERT_CONFIG_MASK, + ina->alert_type_select); + if (ret) { + dev_err(dev, "Unable to select alert type\n"); + return ret; + } + } + return 0; } =20 --=20 2.17.1 From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81569262D0B; Tue, 18 Nov 2025 12:53:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470402; cv=none; b=XK/RQXG1YmWmPPx77cDy0lftALvmNYd/nf3Edqzo3evTVr9nimmz8r5BoUuhaua/BGRoQ1HdJsp+xfp6x7nN8S6W9vUO85PHspvBuF9egUuc1WXIs/z9SiCKH74XdD5AONlvM1AUkGgzL1ZkwtzINF4pWQrGYzyZWIZuqeK2l7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470402; c=relaxed/simple; bh=UlOFnJ62G/a9v/ar/FV5xeOEhbvMQ8JVy2OS0VjEgKM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; 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Tue, 18 Nov 2025 20:52:14 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] hwmon: (ina3221) Introduce power attribute and alert characteristics Date: Tue, 18 Nov 2025 07:51:45 -0500 Message-Id: <20251118125148.95603-6-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxtryfCryfCF48WFW5WF47CFg_yoW7XFW5pa ykX3yfJr18Ar93Zw4xKF4UXFn8t3yxGay7Jr1Ig393J3ZrArnYqr48K3W0qF90kryfuF1F k34IqrWrGr13JrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JjBWlgUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbiGR8K02kcZIu7kwAAst Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 has built-in current and power sensors as well as multiple alert functions. Add power attributes and different critical characteristics in hwmon to report the corresponding data. Signed-off-by: Wenliang Yan --- Documentation/hwmon/ina3221.rst | 24 ++++++++++++++ drivers/hwmon/ina3221.c | 57 ++++++++++++++++++++++++++++++--- 2 files changed, 77 insertions(+), 4 deletions(-) diff --git a/Documentation/hwmon/ina3221.rst b/Documentation/hwmon/ina3221.= rst index 8c12c54d2c24..224c6cf735ed 100644 --- a/Documentation/hwmon/ina3221.rst +++ b/Documentation/hwmon/ina3221.rst @@ -13,6 +13,13 @@ Supported chips: =20 https://www.ti.com/ =20 + * Silergy SQ52210 + + Prefix: 'SQ52210' + + Addresses: I2C 0x40 - 0x43 + + Author: Andrew F. Davis =20 Description @@ -23,6 +30,9 @@ side of up to three D.C. power supplies. The INA3221 moni= tors both shunt drop and supply voltage, with programmable conversion times and averaging, curr= ent and power are calculated host-side from these. =20 +The SQ52210 is a mostly compatible chip from Silergy. It incorporates inte= rnal +current and power registers, and provides an extra configurable alert func= tion. + Sysfs entries ------------- =20 @@ -72,3 +82,17 @@ update_interval Data conversion time in millisec= ond, following: Note that setting update_interval to 0ms sets both= BC and SC to 140 us (minimum conversion time). =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Additional sysfs entries for sq52210 +------------------------------------- + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +in[123]_crit Critical high bus voltage +in[123]_crit_alarm Bus voltage critical high alarm +in[123]_lcrit Critical low bus voltage +in[123]_lcrit_alarm Bus voltage critical low alarm +curr[123]_lcrit Critical low current +curr[123]_lcrit_alarm Current critical low alarm +power[123]_input Current for channels 1, 2, and 3 respectively +power[123]_crit Critical high power +power[123]_crit_alarm Power critical high alarm diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 8ea75f407055..1d589d402b52 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -645,6 +645,8 @@ static umode_t ina3221_is_visible(const void *drvdata, { const struct ina3221_data *ina =3D drvdata; const struct ina3221_input *input =3D NULL; + bool has_alerts =3D ina->config->has_alerts; + bool has_power =3D ina->config->has_power; =20 switch (type) { case hwmon_chip: @@ -672,6 +674,16 @@ static umode_t ina3221_is_visible(const void *drvdata, return 0444; case hwmon_in_enable: return 0644; + case hwmon_in_crit: + case hwmon_in_lcrit: + if (has_alerts) + return 0644; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + if (has_alerts) + return 0444; + return 0; default: return 0; } @@ -684,6 +696,31 @@ static umode_t ina3221_is_visible(const void *drvdata, case hwmon_curr_crit: case hwmon_curr_max: return 0644; + case hwmon_curr_lcrit: + if (has_alerts) + return 0644; + return 0; + case hwmon_curr_lcrit_alarm: + if (has_alerts) + return 0444; + return 0; + default: + return 0; + } + case hwmon_power: + switch (attr) { + case hwmon_power_input: + if (has_power) + return 0444; + return 0; + case hwmon_power_crit_alarm: + if (has_alerts) + return 0444; + return 0; + case hwmon_power_crit: + if (has_alerts) + return 0644; + return 0; default: return 0; } @@ -694,7 +731,14 @@ static umode_t ina3221_is_visible(const void *drvdata, =20 #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ - HWMON_C_MAX | HWMON_C_MAX_ALARM) + HWMON_C_MAX | HWMON_C_MAX_ALARM | \ + HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM) +#define SQ52210_HWMON_POWER_CONFIG (HWMON_P_INPUT | \ + HWMON_P_CRIT | HWMON_P_CRIT_ALARM) +#define SQ52210_HWMON_BUS_CONFIG (HWMON_I_INPUT | \ + HWMON_I_ENABLE | HWMON_I_LABEL | \ + HWMON_I_LCRIT_ALARM | HWMON_I_LCRIT |\ + HWMON_I_CRIT_ALARM | HWMON_I_CRIT) =20 static const struct hwmon_channel_info * const ina3221_info[] =3D { HWMON_CHANNEL_INFO(chip, @@ -704,9 +748,9 @@ static const struct hwmon_channel_info * const ina3221_= info[] =3D { /* 0: dummy, skipped in is_visible */ HWMON_I_INPUT, /* 1-3: input voltage Channels */ - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, /* 4-6: shunt voltage Channels */ HWMON_I_INPUT, HWMON_I_INPUT, @@ -720,6 +764,11 @@ static const struct hwmon_channel_info * const ina3221= _info[] =3D { INA3221_HWMON_CURR_CONFIG, /* 4: summation of current channels */ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM), + HWMON_CHANNEL_INFO(power, + /* 1-3: power channels*/ + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG), NULL }; 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Tue, 18 Nov 2025 20:52:17 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function. Date: Tue, 18 Nov 2025 07:51:46 -0500 Message-Id: <20251118125148.95603-7-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S8 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4DKrWUCr1fWF4kKr4xCrg_yoWxAw1rp3 yfCF1rtr17tr1Svrs2kFs5WFyfAryxW3y2vr9rK39ava1UGa4vgrykta1FyFy5CFn3ZFsr X3srZ3WUCanrJaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JjeWlgUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwAF8UGkcbAGt4gAA36 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 adds power, current, and limit registers. The ina3221_read_value function has been refactored to adapt to the new register data reading format. Each channel supports four new alert trigger modes, but only one trigger mode can be active at any given time. Alert values are stored in the same register. The sq52210_alert_limit_write function has been added to write alert threshold values and configure alert source type. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 1d589d402b52..9a25a1b40856 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -66,6 +66,14 @@ #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6)) +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5)) +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4)) + +#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13)) +#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10)) +#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7)) +#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4)) =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221= _data *ina) cvrf, cvrf, wait, wait * 2); } =20 +static const u32 alert_groups[] =3D { + SQ52210_MASK_ALERT_CHANNEL1, + SQ52210_MASK_ALERT_CHANNEL2, + SQ52210_MASK_ALERT_CHANNEL3, +}; + +static const u8 limit_regs[] =3D { + SQ52210_ALERT_LIMIT1, + SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, +}; + static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, int *val) { @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *in= a, unsigned int reg, =20 /* * Shunt Voltage Sum register has 14-bit value with 1-bit shift + * Current registers have 15-bit value + * Power registers have 16-bit value + * ALERT_LIMIT registers have 16-bit value with 3-bit shift * Other Shunt Voltage registers have 12 bits with 3-bit shift */ - if (reg =3D=3D INA3221_SHUNT_SUM || reg =3D=3D INA3221_CRIT_SUM) + switch (reg) { + case INA3221_SHUNT_SUM: + case INA3221_CRIT_SUM: *val =3D sign_extend32(regval >> 1, 14); - else + break; + case SQ52210_CURRENT1: + case SQ52210_CURRENT2: + case SQ52210_CURRENT3: + *val =3D sign_extend32(regval, 15); + break; + case SQ52210_POWER1: + case SQ52210_POWER2: + case SQ52210_POWER3: + *val =3D regval; + break; + case INA3221_BUS1: + case INA3221_BUS2: + case INA3221_BUS3: + case INA3221_SHUNT1: + case INA3221_SHUNT2: + case INA3221_SHUNT3: + case INA3221_WARN1: + case INA3221_WARN2: + case INA3221_WARN3: + case INA3221_CRIT1: + case INA3221_CRIT2: + case INA3221_CRIT3: *val =3D sign_extend32(regval >> 3, 12); - + break; + case SQ52210_ALERT_LIMIT1: + case SQ52210_ALERT_LIMIT2: + case SQ52210_ALERT_LIMIT3: + if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK) + *val =3D sign_extend32(regval, 15); + else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK + | SQ52210_ALERT_ALL_BUL_MASK)) + *val =3D regval >> 3; + else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK) + *val =3D regval; + break; + default: + *val =3D 0; + return -EOPNOTSUPP; + }; return 0; } =20 @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, i= nt channel, long val) +{ + struct regmap *regmap =3D ina->regmap; + int item =3D channel % INA3221_NUM_CHANNELS; + u8 limit_reg; + u32 alert_group, alert_mask =3D 0; + int regval =3D 0; + int ret; + + if (item >=3D ARRAY_SIZE(alert_groups) || val < 0) + return -EINVAL; + + alert_group =3D alert_groups[item]; + limit_reg =3D limit_regs[item]; + + /* Clear alerts for this channel group first */ + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0); + if (ret) + return ret; + + /* Determine alert type and calculate register value */ + switch (attr) { + /* + * The alert warning logic is implemented by comparing the limit register= values + * with the corresponding alert source register values. Since the current= register + * is a 15-bit signed register and the power register is a 16-bit unsigned + * register, but the lower 3 bits of the limit register default to 0, the= lower + * 3 bits will be forced to 0 when setting SUL and POL warning values. + * Formula to convert register value: + * bus_voltage: (regval / 8mV) << 3 + * current: (regval / current_lsb) & 0xfff8 + * power: (regval / current_lsb) & 0xfff8 + */ + case hwmon_curr_lcrit: + /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */ + alert_mask =3D BIT(15 - item); + /* Current Register, signed register, result in mA */ + regval =3D DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8; + regval =3D clamp_val(regval, -32760, 32760); + break; + case hwmon_in_crit: + /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */ + alert_mask =3D BIT(12 - item); + /* Bus Register, signed register, result in mV */ + regval =3D clamp_val(val, -32760, 32760); + break; + case hwmon_in_lcrit: + /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */ + alert_mask =3D BIT(9 - item); + /* Bus Register, signed register, result in mV */ + regval =3D clamp_val(val, -32760, 32760); + break; + case hwmon_power_crit: + /* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */ + alert_mask =3D BIT(6 - item); + /* Power Register, unsigned register, result in mW */ + regval =3D DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8; + regval =3D clamp_val(regval, 0, 65528); + break; + default: + /* For unsupported attributes, just clear the configuration */ + ina->alert_type_select &=3D ~alert_group; + return -EOPNOTSUPP; + } + + /* Write limit register value */ + ret =3D regmap_write(regmap, limit_reg, regval); + if (ret) + return ret; + + /* Update alert configuration if limit value is non-zero */ + if (regval) { + ina->alert_type_select =3D (ina->alert_type_select & ~alert_group) | ale= rt_mask; + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, + alert_group, alert_mask); + } else { + ina->alert_type_select &=3D ~alert_group; + } + + return ret; +} + static int ina3221_write_chip(struct device *dev, u32 attr, long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); 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Tue, 18 Nov 2025 20:52:18 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] hwmon: (ina3221) Support write/read functions for 'power' attribute Date: Tue, 18 Nov 2025 07:51:47 -0500 Message-Id: <20251118125148.95603-8-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S9 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFy3tr48WFWxZr1DKrykXwb_yoWrWF47p3 y0kFWrtr4UtF1S9ws3KFs8Gw15tr4xX34Iyr9Fk3savF4UZr909Fyrt3Wqya4UAry3XF47 tayxAryru3ZrKrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUWRR_UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/1tbiGQoK02kcZIu7sQABsb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 adds power attributes to report power data and implements corresponding read/write functions for this purpose. This includes reading power values, reading alert thresholds, reading alert trigger status, and writing alert thresholds. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 79 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 9a25a1b40856..197fc3a468e4 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -92,6 +92,9 @@ enum ina3221_fields { /* Alert Flags: SF is the summation-alert flag */ F_SF, F_CF3, F_CF2, F_CF1, =20 + /* Alert Flags: AFF is the alert function flag */ + F_AFF3, F_AFF2, F_AFF1, + /* sentinel */ F_MAX_FIELDS }; @@ -107,6 +110,10 @@ static const struct reg_field ina3221_reg_fields[] =3D= { [F_CF3] =3D REG_FIELD(INA3221_MASK_ENABLE, 7, 7), [F_CF2] =3D REG_FIELD(INA3221_MASK_ENABLE, 8, 8), [F_CF1] =3D REG_FIELD(INA3221_MASK_ENABLE, 9, 9), + + [F_AFF3] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 1, 1), + [F_AFF2] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 2, 2), + [F_AFF1] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 3, 3), }; =20 enum ina3221_channels { @@ -505,6 +512,60 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, } } =20 +static const u8 ina3221_power_reg[][INA3221_NUM_CHANNELS] =3D { + [hwmon_power_input] =3D { SQ52210_POWER1, SQ52210_POWER2, SQ52210_POWER3 = }, + [hwmon_power_crit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3 }, + [hwmon_power_crit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3 }, +}; + +static int ina3221_read_power(struct device *dev, u32 attr, int channel, l= ong *val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + u8 reg =3D ina3221_power_reg[attr][channel]; + int regval, ret; + + switch (attr) { + case hwmon_power_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) { + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret =3D ina3221_wait_for_data(ina); + if (ret) + return ret; + } + + fallthrough; + case hwmon_power_crit: + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return power in mW */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->power_lsb_uW, 1000); + return 0; + case hwmon_power_crit_alarm: + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; + default: + return -EOPNOTSUPP; + } +} + static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, i= nt channel, long val) { struct regmap *regmap =3D ina->regmap; @@ -723,6 +784,18 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_power_crit: + return sq52210_alert_limit_write(ina, attr, channel, val); + default: + return 0; + } +} + static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -739,6 +812,9 @@ static int ina3221_read(struct device *dev, enum hwmon_= sensor_types type, case hwmon_curr: ret =3D ina3221_read_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_read_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; @@ -762,6 +838,9 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_write_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; --=20 2.17.1 From nobody Tue Dec 2 02:49:44 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2C11258EF0; Tue, 18 Nov 2025 12:53:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763470400; cv=none; b=O3wqIVP3A1SUqG92jNcxpM5kghR4eiDA0oY5b9SU0qNRMUXb6VQ3F29QZN0Rns4+m+F+bEx60xcQyYb8cMRAnk96W8met8mtEzNmE08XNjtczincUKsWX8GKXjh4NSoGfOLiBXt1t+gHATxT44tymf/Ac1t4Hl6c+wb7X0xxDyA= ARC-Message-Signature: i=1; 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s=s110527; h=From:To:Subject:Date:Message-Id; bh=ZRoqeIUCfF06GBM hp9pDfuud+73ZPkjSr7txCdSHIlo=; b=H7SNEnVTQN8PEScgHcV9TbtJl9z2W7c ywNDpMx9szCN7jhRnC8q6tanXPYUhwn+B6oIJ1zRcUaTtFP/GSUFw34DJB5TnoFw FvWRTyyweyBMOLRqt98y+17phzLGNKwFOhFPLUIbhwq0cjt4WLC5y3TYBBgwkbZ+ CCH4A2LIc0zY= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wD3E8H1axxpyxYsBA--.3548S10; Tue, 18 Nov 2025 20:52:19 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] hwmon: (ina3221) Modify write/read functions for 'in' and 'curr' attribute Date: Tue, 18 Nov 2025 07:51:48 -0500 Message-Id: <20251118125148.95603-9-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251118125148.95603-1-wenliang202407@163.com> References: <20251118125148.95603-1-wenliang202407@163.com> X-CM-TRANSID: _____wD3E8H1axxpyxYsBA--.3548S10 X-Coremail-Antispam: 1Uf129KBjvJXoWxurW5uFy5GFW7urWftF1DWrg_yoWrtFy5p3 yUGFWrtrWjq3WSgwsakF4DWrn8trWxX3y2yr9rK39Yva1UAryq9FyrG3Wq9345Gr93WF4x JayxtFWUua1qvr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUWRR_UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCwAN8UGkcbAOuEwAA3I Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modified the relevant read/write functions for 'in' and 'curr' attributes, adding support for crit, lcrit, crit_alarm, and lcrit_alarm features. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 96 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 92 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 197fc3a468e4..2f05ee6c72a9 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -373,6 +373,12 @@ static const u8 ina3221_in_reg[] =3D { INA3221_SHUNT_SUM, }; =20 +static const u8 alert_flag[] =3D { + F_AFF1, + F_AFF2, + F_AFF3, +}; + static int ina3221_read_chip(struct device *dev, u32 attr, long *val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -435,6 +441,38 @@ static int ina3221_read_in(struct device *dev, u32 att= r, int channel, long *val) case hwmon_in_enable: *val =3D ina3221_is_enabled(ina, channel); return 0; + case hwmon_in_crit: + case hwmon_in_lcrit: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + reg =3D limit_regs[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* + * Scale of bus voltage (mV): LSB is 8mV + */ + *val =3D regval * 8; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + reg =3D alert_flag[channel]; + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; default: return -EOPNOTSUPP; } @@ -494,6 +532,25 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, /* Return current in mA */ *val =3D DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); return 0; + case hwmon_curr_lcrit: + if (!resistance_uo) + return -ENODATA; + + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + reg =3D limit_regs[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + + /* Return current in mA */ + *val =3D DIV_ROUND_CLOSEST(regval * ina->current_lsb_uA, 1000); + return 0; + case hwmon_curr_lcrit_alarm: + reg =3D alert_flag[channel]; + + fallthrough; case hwmon_curr_crit_alarm: case hwmon_curr_max_alarm: /* No actual register read if channel is disabled */ @@ -690,10 +747,9 @@ static int ina3221_write_chip(struct device *dev, u32 = attr, long val) } } =20 -static int ina3221_write_curr(struct device *dev, u32 attr, - int channel, long val) +static int ina3221_write_curr_shunt(struct ina3221_data *ina, u32 attr, + int channel, long val) { - struct ina3221_data *ina =3D dev_get_drvdata(dev); struct ina3221_input *input =3D ina->inputs; u8 reg =3D ina3221_curr_reg[attr][channel]; int resistance_uo, current_ma, voltage_uv; @@ -736,6 +792,22 @@ static int ina3221_write_curr(struct device *dev, u32 = attr, return regmap_write(ina->regmap, reg, regval); } =20 +static int ina3221_write_curr(struct device *dev, u32 attr, + int channel, long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_curr_crit: + case hwmon_curr_max: + return ina3221_write_curr_shunt(ina, attr, channel, val); + case hwmon_curr_lcrit: + return sq52210_alert_limit_write(ina, attr, channel, val); + default: + return 0; + } +} + static int ina3221_write_enable(struct device *dev, int channel, bool enab= le) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -784,6 +856,22 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_in(struct device *dev, u32 attr, int channel, lon= g val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_in_lcrit: + return sq52210_alert_limit_write(ina, attr, channel, val); + case hwmon_in_crit: + return sq52210_alert_limit_write(ina, attr, channel, val); + case hwmon_in_enable: + return ina3221_write_enable(dev, channel, val); + default: + return 0; + } +} + static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -833,7 +921,7 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, break; case hwmon_in: /* 0-align channel ID */ - ret =3D ina3221_write_enable(dev, channel - 1, val); + ret =3D ina3221_write_in(dev, attr, channel - 1, val); break; case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); --=20 2.17.1