SQ52210 adds power, current, and limit registers. The ina3221_read_value
function has been refactored to adapt to the new register data reading
format.
Each channel supports four new alert trigger modes, but only one trigger
mode can be active at any given time. Alert values are stored in the same
register. The sq52210_alert_limit_write function has been added to write
alert threshold values and configure alert source type.
Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 147 insertions(+), 3 deletions(-)
diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 1d589d402b52..9a25a1b40856 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -66,6 +66,14 @@
#define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12)
#define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4)
+#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
+#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
+#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
+
+#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13))
+#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10))
+#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7))
+#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4))
#define INA3221_CONFIG_DEFAULT 0x7127
#define INA3221_RSHUNT_DEFAULT 10000
@@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
cvrf, cvrf, wait, wait * 2);
}
+static const u32 alert_groups[] = {
+ SQ52210_MASK_ALERT_CHANNEL1,
+ SQ52210_MASK_ALERT_CHANNEL2,
+ SQ52210_MASK_ALERT_CHANNEL3,
+};
+
+static const u8 limit_regs[] = {
+ SQ52210_ALERT_LIMIT1,
+ SQ52210_ALERT_LIMIT2,
+ SQ52210_ALERT_LIMIT3,
+};
+
static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
int *val)
{
@@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
/*
* Shunt Voltage Sum register has 14-bit value with 1-bit shift
+ * Current registers have 15-bit value
+ * Power registers have 16-bit value
+ * ALERT_LIMIT registers have 16-bit value with 3-bit shift
* Other Shunt Voltage registers have 12 bits with 3-bit shift
*/
- if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
+ switch (reg) {
+ case INA3221_SHUNT_SUM:
+ case INA3221_CRIT_SUM:
*val = sign_extend32(regval >> 1, 14);
- else
+ break;
+ case SQ52210_CURRENT1:
+ case SQ52210_CURRENT2:
+ case SQ52210_CURRENT3:
+ *val = sign_extend32(regval, 15);
+ break;
+ case SQ52210_POWER1:
+ case SQ52210_POWER2:
+ case SQ52210_POWER3:
+ *val = regval;
+ break;
+ case INA3221_BUS1:
+ case INA3221_BUS2:
+ case INA3221_BUS3:
+ case INA3221_SHUNT1:
+ case INA3221_SHUNT2:
+ case INA3221_SHUNT3:
+ case INA3221_WARN1:
+ case INA3221_WARN2:
+ case INA3221_WARN3:
+ case INA3221_CRIT1:
+ case INA3221_CRIT2:
+ case INA3221_CRIT3:
*val = sign_extend32(regval >> 3, 12);
-
+ break;
+ case SQ52210_ALERT_LIMIT1:
+ case SQ52210_ALERT_LIMIT2:
+ case SQ52210_ALERT_LIMIT3:
+ if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
+ *val = sign_extend32(regval, 15);
+ else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
+ | SQ52210_ALERT_ALL_BUL_MASK))
+ *val = regval >> 3;
+ else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
+ *val = regval;
+ break;
+ default:
+ *val = 0;
+ return -EOPNOTSUPP;
+ };
return 0;
}
@@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
}
}
+static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
+{
+ struct regmap *regmap = ina->regmap;
+ int item = channel % INA3221_NUM_CHANNELS;
+ u8 limit_reg;
+ u32 alert_group, alert_mask = 0;
+ int regval = 0;
+ int ret;
+
+ if (item >= ARRAY_SIZE(alert_groups) || val < 0)
+ return -EINVAL;
+
+ alert_group = alert_groups[item];
+ limit_reg = limit_regs[item];
+
+ /* Clear alerts for this channel group first */
+ ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
+ if (ret)
+ return ret;
+
+ /* Determine alert type and calculate register value */
+ switch (attr) {
+ /*
+ * The alert warning logic is implemented by comparing the limit register values
+ * with the corresponding alert source register values. Since the current register
+ * is a 15-bit signed register and the power register is a 16-bit unsigned
+ * register, but the lower 3 bits of the limit register default to 0, the lower
+ * 3 bits will be forced to 0 when setting SUL and POL warning values.
+ * Formula to convert register value:
+ * bus_voltage: (regval / 8mV) << 3
+ * current: (regval / current_lsb) & 0xfff8
+ * power: (regval / current_lsb) & 0xfff8
+ */
+ case hwmon_curr_lcrit:
+ /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
+ alert_mask = BIT(15 - item);
+ /* Current Register, signed register, result in mA */
+ regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
+ regval = clamp_val(regval, -32760, 32760);
+ break;
+ case hwmon_in_crit:
+ /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
+ alert_mask = BIT(12 - item);
+ /* Bus Register, signed register, result in mV */
+ regval = clamp_val(val, -32760, 32760);
+ break;
+ case hwmon_in_lcrit:
+ /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
+ alert_mask = BIT(9 - item);
+ /* Bus Register, signed register, result in mV */
+ regval = clamp_val(val, -32760, 32760);
+ break;
+ case hwmon_power_crit:
+ /* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */
+ alert_mask = BIT(6 - item);
+ /* Power Register, unsigned register, result in mW */
+ regval = DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8;
+ regval = clamp_val(regval, 0, 65528);
+ break;
+ default:
+ /* For unsupported attributes, just clear the configuration */
+ ina->alert_type_select &= ~alert_group;
+ return -EOPNOTSUPP;
+ }
+
+ /* Write limit register value */
+ ret = regmap_write(regmap, limit_reg, regval);
+ if (ret)
+ return ret;
+
+ /* Update alert configuration if limit value is non-zero */
+ if (regval) {
+ ina->alert_type_select = (ina->alert_type_select & ~alert_group) | alert_mask;
+ ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG,
+ alert_group, alert_mask);
+ } else {
+ ina->alert_type_select &= ~alert_group;
+ }
+
+ return ret;
+}
+
static int ina3221_write_chip(struct device *dev, u32 attr, long val)
{
struct ina3221_data *ina = dev_get_drvdata(dev);
--
2.17.1On 11/18/25 04:51, Wenliang Yan wrote:
> SQ52210 adds power, current, and limit registers. The ina3221_read_value
> function has been refactored to adapt to the new register data reading
> format.
>
> Each channel supports four new alert trigger modes, but only one trigger
> mode can be active at any given time. Alert values are stored in the same
> register. The sq52210_alert_limit_write function has been added to write
> alert threshold values and configure alert source type.
>
> Signed-off-by: Wenliang Yan <wenliang202407@163.com>
> ---
> drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 147 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
> index 1d589d402b52..9a25a1b40856 100644
> --- a/drivers/hwmon/ina3221.c
> +++ b/drivers/hwmon/ina3221.c
> @@ -66,6 +66,14 @@
> #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12)
>
> #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4)
> +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
> +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
> +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
> +
> +#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13))
> +#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10))
> +#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7))
> +#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4))
>
> #define INA3221_CONFIG_DEFAULT 0x7127
> #define INA3221_RSHUNT_DEFAULT 10000
> @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
> cvrf, cvrf, wait, wait * 2);
> }
>
> +static const u32 alert_groups[] = {
> + SQ52210_MASK_ALERT_CHANNEL1,
> + SQ52210_MASK_ALERT_CHANNEL2,
> + SQ52210_MASK_ALERT_CHANNEL3,
> +};
> +
> +static const u8 limit_regs[] = {
> + SQ52210_ALERT_LIMIT1,
> + SQ52210_ALERT_LIMIT2,
> + SQ52210_ALERT_LIMIT3,
> +};
> +
> static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
> int *val)
> {
> @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>
> /*
> * Shunt Voltage Sum register has 14-bit value with 1-bit shift
> + * Current registers have 15-bit value
> + * Power registers have 16-bit value
> + * ALERT_LIMIT registers have 16-bit value with 3-bit shift
> * Other Shunt Voltage registers have 12 bits with 3-bit shift
> */
> - if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
> + switch (reg) {
> + case INA3221_SHUNT_SUM:
> + case INA3221_CRIT_SUM:
> *val = sign_extend32(regval >> 1, 14);
> - else
> + break;
> + case SQ52210_CURRENT1:
> + case SQ52210_CURRENT2:
> + case SQ52210_CURRENT3:
> + *val = sign_extend32(regval, 15);
> + break;
> + case SQ52210_POWER1:
> + case SQ52210_POWER2:
> + case SQ52210_POWER3:
> + *val = regval;
> + break;
> + case INA3221_BUS1:
> + case INA3221_BUS2:
> + case INA3221_BUS3:
> + case INA3221_SHUNT1:
> + case INA3221_SHUNT2:
> + case INA3221_SHUNT3:
> + case INA3221_WARN1:
> + case INA3221_WARN2:
> + case INA3221_WARN3:
> + case INA3221_CRIT1:
> + case INA3221_CRIT2:
> + case INA3221_CRIT3:
> *val = sign_extend32(regval >> 3, 12);
> -
> + break;
> + case SQ52210_ALERT_LIMIT1:
> + case SQ52210_ALERT_LIMIT2:
> + case SQ52210_ALERT_LIMIT3:
> + if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
> + *val = sign_extend32(regval, 15);
> + else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
> + | SQ52210_ALERT_ALL_BUL_MASK))
> + *val = regval >> 3;
> + else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
> + *val = regval;
> + break;
> + default:
> + *val = 0;
> + return -EOPNOTSUPP;
> + };
> return 0;
> }
>
> @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
> }
> }
>
> +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
> +{
> + struct regmap *regmap = ina->regmap;
> + int item = channel % INA3221_NUM_CHANNELS;
> + u8 limit_reg;
> + u32 alert_group, alert_mask = 0;
> + int regval = 0;
> + int ret;
> +
> + if (item >= ARRAY_SIZE(alert_groups) || val < 0)
> + return -EINVAL;
> +
> + alert_group = alert_groups[item];
> + limit_reg = limit_regs[item];
> +
> + /* Clear alerts for this channel group first */
> + ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
> + if (ret)
> + return ret;
> +
> + /* Determine alert type and calculate register value */
> + switch (attr) {
> + /*
> + * The alert warning logic is implemented by comparing the limit register values
> + * with the corresponding alert source register values. Since the current register
> + * is a 15-bit signed register and the power register is a 16-bit unsigned
> + * register, but the lower 3 bits of the limit register default to 0, the lower
> + * 3 bits will be forced to 0 when setting SUL and POL warning values.
> + * Formula to convert register value:
> + * bus_voltage: (regval / 8mV) << 3
> + * current: (regval / current_lsb) & 0xfff8
> + * power: (regval / current_lsb) & 0xfff8
> + */
> + case hwmon_curr_lcrit:
> + /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
> + alert_mask = BIT(15 - item);
> + /* Current Register, signed register, result in mA */
> + regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
> + regval = clamp_val(regval, -32760, 32760);
> + break;
> + case hwmon_in_crit:
> + /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
> + alert_mask = BIT(12 - item);
> + /* Bus Register, signed register, result in mV */
> + regval = clamp_val(val, -32760, 32760);
> + break;
> + case hwmon_in_lcrit:
> + /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
> + alert_mask = BIT(9 - item);
> + /* Bus Register, signed register, result in mV */
> + regval = clamp_val(val, -32760, 32760);
> + break;
> + case hwmon_power_crit:
Didn't I say this before ? The number space for each sensor type overlaps.
Sensor attributes for different types can not be used in the same case statement.
Did you even compile this ? I would be quite surprised if there is a compiler
that would accept this code.
Guenter
At 2025-11-19 12:20:34, "Guenter Roeck" <linux@roeck-us.net> wrote:
>On 11/18/25 04:51, Wenliang Yan wrote:
>> SQ52210 adds power, current, and limit registers. The ina3221_read_value
>> function has been refactored to adapt to the new register data reading
>> format.
>>
>> Each channel supports four new alert trigger modes, but only one trigger
>> mode can be active at any given time. Alert values are stored in the same
>> register. The sq52210_alert_limit_write function has been added to write
>> alert threshold values and configure alert source type.
>>
>> Signed-off-by: Wenliang Yan <wenliang202407@163.com>
>> ---
>> drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 147 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
>> index 1d589d402b52..9a25a1b40856 100644
>> --- a/drivers/hwmon/ina3221.c
>> +++ b/drivers/hwmon/ina3221.c
>> @@ -66,6 +66,14 @@
>> #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12)
>>
>> #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4)
>> +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
>> +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
>> +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
>> +
>> +#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13))
>> +#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10))
>> +#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7))
>> +#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4))
>>
>> #define INA3221_CONFIG_DEFAULT 0x7127
>> #define INA3221_RSHUNT_DEFAULT 10000
>> @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
>> cvrf, cvrf, wait, wait * 2);
>> }
>>
>> +static const u32 alert_groups[] = {
>> + SQ52210_MASK_ALERT_CHANNEL1,
>> + SQ52210_MASK_ALERT_CHANNEL2,
>> + SQ52210_MASK_ALERT_CHANNEL3,
>> +};
>> +
>> +static const u8 limit_regs[] = {
>> + SQ52210_ALERT_LIMIT1,
>> + SQ52210_ALERT_LIMIT2,
>> + SQ52210_ALERT_LIMIT3,
>> +};
>> +
>> static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>> int *val)
>> {
>> @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>>
>> /*
>> * Shunt Voltage Sum register has 14-bit value with 1-bit shift
>> + * Current registers have 15-bit value
>> + * Power registers have 16-bit value
>> + * ALERT_LIMIT registers have 16-bit value with 3-bit shift
>> * Other Shunt Voltage registers have 12 bits with 3-bit shift
>> */
>> - if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
>> + switch (reg) {
>> + case INA3221_SHUNT_SUM:
>> + case INA3221_CRIT_SUM:
>> *val = sign_extend32(regval >> 1, 14);
>> - else
>> + break;
>> + case SQ52210_CURRENT1:
>> + case SQ52210_CURRENT2:
>> + case SQ52210_CURRENT3:
>> + *val = sign_extend32(regval, 15);
>> + break;
>> + case SQ52210_POWER1:
>> + case SQ52210_POWER2:
>> + case SQ52210_POWER3:
>> + *val = regval;
>> + break;
>> + case INA3221_BUS1:
>> + case INA3221_BUS2:
>> + case INA3221_BUS3:
>> + case INA3221_SHUNT1:
>> + case INA3221_SHUNT2:
>> + case INA3221_SHUNT3:
>> + case INA3221_WARN1:
>> + case INA3221_WARN2:
>> + case INA3221_WARN3:
>> + case INA3221_CRIT1:
>> + case INA3221_CRIT2:
>> + case INA3221_CRIT3:
>> *val = sign_extend32(regval >> 3, 12);
>> -
>> + break;
>> + case SQ52210_ALERT_LIMIT1:
>> + case SQ52210_ALERT_LIMIT2:
>> + case SQ52210_ALERT_LIMIT3:
>> + if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
>> + *val = sign_extend32(regval, 15);
>> + else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
>> + | SQ52210_ALERT_ALL_BUL_MASK))
>> + *val = regval >> 3;
>> + else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
>> + *val = regval;
>> + break;
>> + default:
>> + *val = 0;
>> + return -EOPNOTSUPP;
>> + };
>> return 0;
>> }
>>
>> @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
>> }
>> }
>>
>> +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
>> +{
>> + struct regmap *regmap = ina->regmap;
>> + int item = channel % INA3221_NUM_CHANNELS;
>> + u8 limit_reg;
>> + u32 alert_group, alert_mask = 0;
>> + int regval = 0;
>> + int ret;
>> +
>> + if (item >= ARRAY_SIZE(alert_groups) || val < 0)
>> + return -EINVAL;
>> +
>> + alert_group = alert_groups[item];
>> + limit_reg = limit_regs[item];
>> +
>> + /* Clear alerts for this channel group first */
>> + ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
>> + if (ret)
>> + return ret;
>> +
>> + /* Determine alert type and calculate register value */
>> + switch (attr) {
>> + /*
>> + * The alert warning logic is implemented by comparing the limit register values
>> + * with the corresponding alert source register values. Since the current register
>> + * is a 15-bit signed register and the power register is a 16-bit unsigned
>> + * register, but the lower 3 bits of the limit register default to 0, the lower
>> + * 3 bits will be forced to 0 when setting SUL and POL warning values.
>> + * Formula to convert register value:
>> + * bus_voltage: (regval / 8mV) << 3
>> + * current: (regval / current_lsb) & 0xfff8
>> + * power: (regval / current_lsb) & 0xfff8
>> + */
>> + case hwmon_curr_lcrit:
>> + /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
>> + alert_mask = BIT(15 - item);
>> + /* Current Register, signed register, result in mA */
>> + regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
>> + regval = clamp_val(regval, -32760, 32760);
>> + break;
>> + case hwmon_in_crit:
>> + /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
>> + alert_mask = BIT(12 - item);
>> + /* Bus Register, signed register, result in mV */
>> + regval = clamp_val(val, -32760, 32760);
>> + break;
>> + case hwmon_in_lcrit:
>> + /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
>> + alert_mask = BIT(9 - item);
>> + /* Bus Register, signed register, result in mV */
>> + regval = clamp_val(val, -32760, 32760);
>> + break;
>> + case hwmon_power_crit:
>
>Didn't I say this before ? The number space for each sensor type overlaps.
>Sensor attributes for different types can not be used in the same case statement.
>
>Did you even compile this ? I would be quite surprised if there is a compiler
>that would accept this code.
>
>Guenter
This was due to an oversight during the preparation of the patch series:
I inadvertently uploaded an incorrect patch version. Specifically, I submitted
code from an earlier modification phase instead of the final thoroughly tested
version. The updated release introduces new enum variables to address this problem,
and I will promptly prepare and submit a corrected v3 version containing the
proper code.
My sincere apologies for any inconvenience this may have caused.
Thank you for your understanding and patience.
Thanks,
Wenlaing Yan
Hi Wenliang,
kernel test robot noticed the following build errors:
[auto build test ERROR on groeck-staging/hwmon-next]
[also build test ERROR on robh/for-next linus/master v6.18-rc6 next-20251118]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
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url: https://github.com/intel-lab-lkp/linux/commits/Wenliang-Yan/dt-bindings-hwmon-ti-ina3221-Add-SQ52210/20251118-205717
base: https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-next
patch link: https://lore.kernel.org/r/20251118125148.95603-7-wenliang202407%40163.com
patch subject: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.
config: arm-randconfig-002-20251119 (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511191138.FRi6Ldng-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/hwmon/ina3221.c:554:7: error: duplicate case value: 'hwmon_curr_lcrit' and 'hwmon_in_lcrit' both equal '4'
case hwmon_in_lcrit:
^
drivers/hwmon/ina3221.c:541:7: note: previous case defined here
case hwmon_curr_lcrit:
^
1 error generated.
vim +554 drivers/hwmon/ina3221.c
507
508 static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
509 {
510 struct regmap *regmap = ina->regmap;
511 int item = channel % INA3221_NUM_CHANNELS;
512 u8 limit_reg;
513 u32 alert_group, alert_mask = 0;
514 int regval = 0;
515 int ret;
516
517 if (item >= ARRAY_SIZE(alert_groups) || val < 0)
518 return -EINVAL;
519
520 alert_group = alert_groups[item];
521 limit_reg = limit_regs[item];
522
523 /* Clear alerts for this channel group first */
524 ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
525 if (ret)
526 return ret;
527
528 /* Determine alert type and calculate register value */
529 switch (attr) {
530 /*
531 * The alert warning logic is implemented by comparing the limit register values
532 * with the corresponding alert source register values. Since the current register
533 * is a 15-bit signed register and the power register is a 16-bit unsigned
534 * register, but the lower 3 bits of the limit register default to 0, the lower
535 * 3 bits will be forced to 0 when setting SUL and POL warning values.
536 * Formula to convert register value:
537 * bus_voltage: (regval / 8mV) << 3
538 * current: (regval / current_lsb) & 0xfff8
539 * power: (regval / current_lsb) & 0xfff8
540 */
541 case hwmon_curr_lcrit:
542 /* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
543 alert_mask = BIT(15 - item);
544 /* Current Register, signed register, result in mA */
545 regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
546 regval = clamp_val(regval, -32760, 32760);
547 break;
548 case hwmon_in_crit:
549 /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
550 alert_mask = BIT(12 - item);
551 /* Bus Register, signed register, result in mV */
552 regval = clamp_val(val, -32760, 32760);
553 break;
> 554 case hwmon_in_lcrit:
555 /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
556 alert_mask = BIT(9 - item);
557 /* Bus Register, signed register, result in mV */
558 regval = clamp_val(val, -32760, 32760);
559 break;
560 case hwmon_power_crit:
561 /* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */
562 alert_mask = BIT(6 - item);
563 /* Power Register, unsigned register, result in mW */
564 regval = DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8;
565 regval = clamp_val(regval, 0, 65528);
566 break;
567 default:
568 /* For unsupported attributes, just clear the configuration */
569 ina->alert_type_select &= ~alert_group;
570 return -EOPNOTSUPP;
571 }
572
573 /* Write limit register value */
574 ret = regmap_write(regmap, limit_reg, regval);
575 if (ret)
576 return ret;
577
578 /* Update alert configuration if limit value is non-zero */
579 if (regval) {
580 ina->alert_type_select = (ina->alert_type_select & ~alert_group) | alert_mask;
581 ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG,
582 alert_group, alert_mask);
583 } else {
584 ina->alert_type_select &= ~alert_group;
585 }
586
587 return ret;
588 }
589
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