From nobody Tue Dec 2 02:43:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 427E52D4B66; Tue, 18 Nov 2025 12:34:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763469292; cv=none; b=FM1Pq9AEs9+aBnmLQsTJ/+XDqTEcv7XIx/9uRhKZoQR/Ttth5z52mywR35onszULUbl4cq59B26DqkDktzOBFjd5Mx6sQnv9Ta6DZSkLip8owfB8f+Pgw6ScTscD36WqLb5g8inR8kTc1sdZeQStrMoVgUfgJpx0Mjnap6PT6Og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763469292; c=relaxed/simple; bh=JHXZO90DwjmwUsYLD66MEd19r4Z4m05X0McdsCrGPWA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Up47BUZCv+YYNSEVJ0zT7gGscNj+B0cK2OSo5Y7qhoNK/JxS3m0r+DwAcG3nWiEKggjkJfonMwZbCLPgWEFEyyC0wzJHTDO2brWIzzRlRv1GkHtWoojfqujkf39244nO7Nn9eomQDnSz+YW90YYSzsPrGX6tWRio/v/Cq2Kc2m0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mTS6GESK; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mTS6GESK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763469291; x=1795005291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JHXZO90DwjmwUsYLD66MEd19r4Z4m05X0McdsCrGPWA=; b=mTS6GESK+NBJ7nRr4xKitUt4o7l7TodYsWxRPWjaWXCIq7UMyyXUj/iI Kto22ppBCAnQtAiPm2ihxHjBegCs4G+mJ0tbrJxoVnGhPd9Esbt2Z4KDu gYVLSVjJHriR0tlBhuIFUCJkd1crLBRWfRzHwFV2Yfz7moAtwSaff5iMK ol/q5Ncv063JO8seijPqOVEorCBZFSaQ/ubIuh841TiZE09C/vyETH8p6 OuYeJNMPya/HcD1L5G7sAvG1DVPziFAGTYN9f3M8p6KKNdDmS7xKjIvD8 g1Eu6EOZWlhzzwmSKNso66JnHw88t9gw+nEVAXDk8aOoksO+xoxKLxr6z w==; X-CSE-ConnectionGUID: /HsxULTeSr6mW+D/C6G+2g== X-CSE-MsgGUID: ZVmQWLiVQB6GJX+Mh04ung== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="65193282" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="65193282" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 04:34:50 -0800 X-CSE-ConnectionGUID: 0qj9ic3dQyeJZ5kS6m1Wxg== X-CSE-MsgGUID: 46IGWRheQg+gYCQvPiRgGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="190032765" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Nov 2025 04:34:49 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id C1EFC99; Tue, 18 Nov 2025 13:34:47 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v2 1/2] pinctrl: intel: Export intel_gpio_add_pin_ranges() Date: Tue, 18 Nov 2025 13:34:01 +0100 Message-ID: <20251118123444.1217863-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251118123444.1217863-1-andriy.shevchenko@linux.intel.com> References: <20251118123444.1217863-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Export intel_gpio_add_pin_ranges() for reuse in other drivers. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 12 +++++++++++- drivers/pinctrl/intel/pinctrl-intel.h | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index 8e067aaf3399..10e8f82e4543 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1345,7 +1345,16 @@ static int intel_gpio_irq_init_hw(struct gpio_chip *= gc) return 0; } =20 -static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) +/** + * intel_gpio_add_pin_ranges - add GPIO pin ranges for all groups in all c= ommunities + * @gc: GPIO chip structure + * + * This function iterates over all communities and all groups and adds the= respective + * GPIO pin ranges, so the GPIO library will correctly map a GPIO offset t= o a pin number. + * + * Return: 0, or negative error code if range can't be added. + */ +int intel_gpio_add_pin_ranges(struct gpio_chip *gc) { struct intel_pinctrl *pctrl =3D gpiochip_get_data(gc); const struct intel_community *community; @@ -1362,6 +1371,7 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip= *gc) =20 return 0; } +EXPORT_SYMBOL_NS_GPL(intel_gpio_add_pin_ranges, "PINCTRL_INTEL"); =20 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/= pinctrl-intel.h index 654af5977603..c1520797f895 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -276,6 +276,8 @@ extern const struct dev_pm_ops intel_pinctrl_pm_ops; const struct intel_community *intel_get_community(const struct intel_pinct= rl *pctrl, unsigned int pin); =20 +int intel_gpio_add_pin_ranges(struct gpio_chip *gc); + int intel_get_groups_count(struct pinctrl_dev *pctldev); const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int= group); int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, --=20 2.50.1 From nobody Tue Dec 2 02:43:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A4A0303CA8; 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arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bjOYhETl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763469291; x=1795005291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XUMQb8dzE3Z0DHQDItyXJu/Lfou2F5O8AUqKyQvr6MU=; b=bjOYhETlphZJH4FSUb4OVrjIS8ECgETZweT4+t0ucsvtgNlVvkCpVmvx LdS2Q1FvgzEwn5p+b/klniLkTMn5DMH3AgszvXEsngV2d1zDFqnEFtr1M fibqzGvSC6MtblfxcdOefyn6iAQMLByosEoDM488De2nqbTvhXWSxoIHy OoYbpDUTJxuq5ipu1g64Lkltx3aFKSwJDrdDkDG9wJ2MNnqXowehiQM8F /A9RkBtvQDDwBD8T7m8C1DYl1/Q3vstQ7G0U5SuS0q5QGGHsVe5XrqDJK fx0wEZxdo/Ph65Oxj3vwptqf9A96Ih1pqm6fc6VggAM+cL3rTw3sosIV3 A==; X-CSE-ConnectionGUID: aTHWnELsQ7OUNZ2wWWOKPA== X-CSE-MsgGUID: P8pNQzwkTLW9PFk7VXS3VQ== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="65369104" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="65369104" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2025 04:34:51 -0800 X-CSE-ConnectionGUID: rQ+mSJDJTkGMBhD0EQKK+g== X-CSE-MsgGUID: kkdiTCj0TealLXPFFPe8Tw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="191186716" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa009.fm.intel.com with ESMTP; 18 Nov 2025 04:34:49 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 5B23D9A; Tue, 18 Nov 2025 13:34:48 +0100 (CET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v2 2/2] pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges() Date: Tue, 18 Nov 2025 13:34:02 +0100 Message-ID: <20251118123444.1217863-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251118123444.1217863-1-andriy.shevchenko@linux.intel.com> References: <20251118123444.1217863-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Driver is ready to use intel_gpio_add_pin_ranges() directly instead of custom approach. Convert it now. Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/i= ntel/pinctrl-cherryview.c index 9c353e1ebe4a..d72e50486370 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1511,24 +1511,6 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *ch= ip) return 0; } =20 -static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) -{ - struct intel_pinctrl *pctrl =3D gpiochip_get_data(chip); - struct device *dev =3D pctrl->dev; - const struct intel_community *community =3D &pctrl->communities[0]; - const struct intel_padgroup *gpp; - int ret, i; - - for (i =3D 0; i < community->ngpps; i++) { - gpp =3D &community->gpps[i]; - ret =3D gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base= , gpp->size); - if (ret) - return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); - } - - return 0; -} - static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) { const struct intel_community *community =3D &pctrl->communities[0]; @@ -1542,7 +1524,7 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl= , int irq) =20 chip->ngpio =3D pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; chip->label =3D dev_name(dev); - chip->add_pin_ranges =3D chv_gpio_add_pin_ranges; + chip->add_pin_ranges =3D intel_gpio_add_pin_ranges; chip->parent =3D dev; chip->base =3D -1; =20 --=20 2.50.1