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Mon, 17 Nov 2025 18:50:37 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 1/8] drivers: firmware: riscv: add SSE NMI support Date: Tue, 18 Nov 2025 10:50:08 +0800 Message-Id: <20251118025015.42491-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for handling Non-Maskable Interrupts (NMIs) through the RISC-V Supervisor Software Events (SSE) framework. Add basic NMI functionality via SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED registration and enabling. Signed-off-by: Yunhui Cui --- MAINTAINERS | 8 +++ drivers/firmware/riscv/Kconfig | 10 +++ drivers/firmware/riscv/Makefile | 1 + drivers/firmware/riscv/riscv_sse_nmi.c | 89 ++++++++++++++++++++++++++ include/linux/riscv_sse_nmi.h | 26 ++++++++ 5 files changed, 134 insertions(+) create mode 100644 drivers/firmware/riscv/riscv_sse_nmi.c create mode 100644 include/linux/riscv_sse_nmi.h diff --git a/MAINTAINERS b/MAINTAINERS index 8bf5416953f45..c06658da8af96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22057,6 +22057,14 @@ S: Maintained F: drivers/firmware/riscv/riscv_sse.c F: include/linux/riscv_sse.h =20 +RISC-V SSE NMI SUPPORT +M: Yunhui Cui +R: Xu Lu +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/firmware/riscv/riscv_sse_nmi.c +F: include/linux/riscv_sse_nmi.h + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig index ed5b663ac5f91..6c77c7823571a 100644 --- a/drivers/firmware/riscv/Kconfig +++ b/drivers/firmware/riscv/Kconfig @@ -12,4 +12,14 @@ config RISCV_SBI_SSE this option provides support to register callbacks on specific SSE events. =20 +config RISCV_SSE_NMI + bool "Enable SBI Supervisor Software Events NMI support" + depends on RISCV_SBI_SSE && SMP + default y + help + This option enables support for delivering Non-Maskable Interrupt + (NMI) notifications through the Supervisor Software Events (SSE) + framework. When enabled, the system can deliver local, unknown and + other types of NMIs. + endmenu diff --git a/drivers/firmware/riscv/Makefile b/drivers/firmware/riscv/Makef= ile index c8795d4bbb2ea..fbc182b53ae53 100644 --- a/drivers/firmware/riscv/Makefile +++ b/drivers/firmware/riscv/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_RISCV_SBI_SSE) +=3D riscv_sbi_sse.o +obj-$(CONFIG_RISCV_SSE_NMI) +=3D riscv_sse_nmi.o diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c new file mode 100644 index 0000000000000..1763f43961ab6 --- /dev/null +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define pr_fmt(fmt) "SSE NMI: " fmt + +#include +#include +#include + +#include +#include +#include + +bool nmi_available; +static struct sse_event *local_nmi_evt; +static atomic_t local_nmi_arg =3D ATOMIC_INIT(LOCAL_NMI_NONE); + +bool nmi_support(void) +{ + return READ_ONCE(nmi_available); +} + +static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0, + unsigned long arg1) +{ + return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0); +} + +void send_nmi_single(unsigned int cpu, enum local_nmi_type type) +{ + unsigned int hart_id =3D cpuid_to_hartid_map(cpu); + u32 evt =3D SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED; + struct sbiret ret; + + atomic_or(type, &local_nmi_arg); + ret =3D sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id); + if (ret.error) + pr_err("Failed to signal event %x to hartid %d, error %ld\n", + evt, hart_id, ret.error); +} + +void send_nmi_mask(cpumask_t *mask, enum local_nmi_type type) +{ + unsigned int cpu; + + for_each_cpu(cpu, mask) + send_nmi_single(cpu, type); +} + +static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) +{ + return 0; +} + +static int __init local_nmi_init(void) +{ + int ret; + + local_nmi_evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTE= D, 0, + local_nmi_handler, &local_nmi_arg); + if (IS_ERR(local_nmi_evt)) + return PTR_ERR(local_nmi_evt); + + ret =3D sse_event_enable(local_nmi_evt); + if (ret) { + sse_event_unregister(local_nmi_evt); + return ret; + } + + pr_info("Using SSE for Local NMI event delivery\n"); + + return 0; +} + +static int __init sse_nmi_init(void) +{ + int ret; + + ret =3D local_nmi_init(); + if (ret) { + pr_err("Local_nmi_init failed with error %d\n", ret); + return ret; + } + + WRITE_ONCE(nmi_available, true); + + return 0; +} + +late_initcall(sse_nmi_init); diff --git a/include/linux/riscv_sse_nmi.h b/include/linux/riscv_sse_nmi.h new file mode 100644 index 0000000000000..16db85c5162f5 --- /dev/null +++ b/include/linux/riscv_sse_nmi.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __LINUX_RISCV_SSE_NMI_H +#define __LINUX_RISCV_SSE_NMI_H + +#include + +enum local_nmi_type { + LOCAL_NMI_NONE =3D 0U, + LOCAL_NMI_STOP =3D BIT(0), + LOCAL_NMI_CRASH =3D BIT(1), + LOCAL_NMI_BACKTRACE =3D BIT(2), + LOCAL_NMI_KGDB =3D BIT(3), +}; + +#ifdef CONFIG_RISCV_SSE_NMI +bool nmi_support(void); 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Mon, 17 Nov 2025 18:50:46 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.241]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c234809sm156022065ad.19.2025.11.17.18.50.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 17 Nov 2025 18:50:46 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 2/8] riscv: smp: move ipi_cpu_crash_stop() declaration to smp.h Date: Tue, 18 Nov 2025 10:50:09 +0800 Message-Id: <20251118025015.42491-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move ipi_cpu_crash_stop() declaration from smp.c to smp.h to enable external reference, and rename it to cpu_crash_stop(). Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/smp.h | 9 +++++++++ arch/riscv/kernel/smp.c | 9 ++------- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 7ac80e9f22889..f53f1f0e7aa9e 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -54,6 +54,15 @@ void riscv_ipi_set_virq_range(int virq, int nr); /* Check other CPUs stop or not */ bool smp_crash_stop_failed(void); =20 +#ifdef CONFIG_KEXEC_CORE +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs); +#else +static inline void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) +{ + unreachable(); +} +#endif + /* Secondary hart entry */ asmlinkage void smp_callin(void); =20 diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index e650dec448176..9dbcb9a06a96d 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -78,7 +78,7 @@ static void ipi_stop(void) #ifdef CONFIG_KEXEC_CORE static atomic_t waiting_for_crash_ipi =3D ATOMIC_INIT(0); =20 -static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) { crash_save_cpu(regs, cpu); =20 @@ -94,11 +94,6 @@ static inline void ipi_cpu_crash_stop(unsigned int cpu, = struct pt_regs *regs) for(;;) wait_for_interrupt(); } -#else -static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) -{ - unreachable(); -} #endif =20 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_typ= e op) @@ -134,7 +129,7 @@ static irqreturn_t handle_IPI(int irq, void *data) ipi_stop(); break; case IPI_CPU_CRASH_STOP: - ipi_cpu_crash_stop(cpu, get_irq_regs()); + cpu_crash_stop(cpu, get_irq_regs()); break; case IPI_IRQ_WORK: irq_work_run(); --=20 2.39.5 From nobody Tue Dec 2 02:44:10 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00DE7328619 for ; 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Mon, 17 Nov 2025 18:50:55 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.241]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c234809sm156022065ad.19.2025.11.17.18.50.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 17 Nov 2025 18:50:54 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 3/8] smp: move num_other_online_cpus() into smp.h Date: Tue, 18 Nov 2025 10:50:10 +0800 Message-Id: <20251118025015.42491-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove duplicate definitions from arm64/riscv, add unified implementation in smp.h. Signed-off-by: Yunhui Cui --- arch/arm64/kernel/smp.c | 11 ----------- arch/riscv/kernel/smp.c | 11 ----------- include/linux/smp.h | 11 +++++++++++ 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 68cea3a4a35ca..2d1e7839dc9b0 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -1171,17 +1171,6 @@ void tick_broadcast(const struct cpumask *mask) } #endif =20 -/* - * The number of CPUs online, not counting this CPU (which may not be - * fully online and so not counted in num_online_cpus()). - */ -static inline unsigned int num_other_online_cpus(void) -{ - unsigned int this_cpu_online =3D cpu_online(smp_processor_id()); - - return num_online_cpus() - this_cpu_online; -} - void smp_send_stop(void) { static unsigned long stop_in_progress; diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 9dbcb9a06a96d..669325e68a21a 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -272,17 +272,6 @@ void smp_send_stop(void) } =20 #ifdef CONFIG_KEXEC_CORE -/* - * The number of CPUs online, not counting this CPU (which may not be - * fully online and so not counted in num_online_cpus()). - */ -static inline unsigned int num_other_online_cpus(void) -{ - unsigned int this_cpu_online =3D cpu_online(smp_processor_id()); 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charset="utf-8" Use NMI instead of IPI for crash stop if RISC-V SSE NMI is supported. Signed-off-by: Yunhui Cui --- arch/riscv/kernel/smp.c | 14 +++++++++++++- drivers/firmware/riscv/riscv_sse_nmi.c | 10 ++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 669325e68a21a..07ccc28f52172 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -300,7 +301,18 @@ void crash_smp_send_stop(void) atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); =20 pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + + /* + * IPI performs better than NMI, but attempting IPI first and + * falling back to NMI on failure requires recording CPUs that failed + * to stop. This adds complexity to cpu_crash_stop(). Since this operation + * is rare and typically in the final phase, directly replace IPI + * with NMI. + */ + if (!nmi_support()) + send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + else + send_nmi_mask(&mask, LOCAL_NMI_CRASH); =20 /* Wait up to one second for other CPUs to stop */ timeout =3D USEC_PER_SEC; diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index 1763f43961ab6..e4c20dce40f9a 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -10,6 +10,9 @@ #include #include =20 +#define NMI_HANDLE(mask, func, ...) \ + do { if (type & (mask)) func(__VA_ARGS__); } while (0) + bool nmi_available; static struct sse_event *local_nmi_evt; static atomic_t local_nmi_arg =3D ATOMIC_INIT(LOCAL_NMI_NONE); @@ -48,6 +51,13 @@ void send_nmi_mask(cpumask_t *mask, enum local_nmi_type = type) =20 static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) { + enum local_nmi_type type =3D atomic_read((atomic_t *)arg); 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Mon, 17 Nov 2025 18:51:12 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 5/8] riscv: smp: retry CPU stop with NMI if IPI fails Date: Tue, 18 Nov 2025 10:50:12 +0800 Message-Id: <20251118025015.42491-6-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Retry CPU stop with NMI when IPI fails and RISC-V SSE NMI is supported, borrowed the code implementation from arm64. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/smp.h | 2 ++ arch/riscv/kernel/smp.c | 23 +++++++++++++++++++---- drivers/firmware/riscv/riscv_sse_nmi.c | 1 + 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index f53f1f0e7aa9e..e01ea962adfc4 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -63,6 +63,8 @@ static inline void cpu_crash_stop(unsigned int cpu, struc= t pt_regs *regs) } #endif =20 +void cpu_stop(void); + /* Secondary hart entry */ asmlinkage void smp_callin(void); =20 diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 07ccc28f52172..aa1cfc344a2c6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -69,7 +69,7 @@ int riscv_hartid_to_cpuid(unsigned long hartid) return -ENOENT; } =20 -static void ipi_stop(void) +void cpu_stop(void) { set_cpu_online(smp_processor_id(), false); while (1) @@ -127,7 +127,7 @@ static irqreturn_t handle_IPI(int irq, void *data) generic_smp_call_function_interrupt(); break; case IPI_CPU_STOP: - ipi_stop(); + cpu_stop(); break; case IPI_CPU_CRASH_STOP: cpu_crash_stop(cpu, get_irq_regs()); @@ -250,10 +250,9 @@ void tick_broadcast(const struct cpumask *mask) void smp_send_stop(void) { unsigned long timeout; + cpumask_t mask; =20 if (num_online_cpus() > 1) { - cpumask_t mask; - cpumask_copy(&mask, cpu_online_mask); cpumask_clear_cpu(smp_processor_id(), &mask); =20 @@ -267,6 +266,22 @@ void smp_send_stop(void) while (num_online_cpus() > 1 && timeout--) udelay(1); =20 + /* + * If CPUs are still online, try an NMI. There's no excuse for this to + * be slow, so we only give them an extra 10 ms to respond. + */ + if (num_other_online_cpus()) { + smp_rmb(); + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); + pr_info("SMP: retry stop with NMI for CPUs %*pbl\n", + cpumask_pr_args(&mask)); + send_nmi_mask(&mask, LOCAL_NMI_STOP); + timeout =3D USEC_PER_MSEC * 10; + while (num_other_online_cpus() && timeout--) + udelay(1); + } + if (num_online_cpus() > 1) pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", cpumask_pr_args(cpu_online_mask)); diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index e4c20dce40f9a..0ff0bda53608a 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -55,6 +55,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct p= t_regs *regs) unsigned int cpu =3D smp_processor_id(); =20 NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); + NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop); 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Mon, 17 Nov 2025 18:51:21 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 6/8] riscv: smp: use NMI for backtrace Date: Tue, 18 Nov 2025 10:50:13 +0800 Message-Id: <20251118025015.42491-7-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use NMI instead of IPI for backtrace if RISC-V SSE NMI is supported. Signed-off-by: Yunhui Cui --- arch/riscv/kernel/smp.c | 12 +++++++++++- drivers/firmware/riscv/riscv_sse_nmi.c | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index aa1cfc344a2c6..26083fe0a5df6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -356,9 +356,19 @@ static void riscv_backtrace_ipi(cpumask_t *mask) send_ipi_mask(mask, IPI_CPU_BACKTRACE); } =20 +static void riscv_backtrace_nmi(cpumask_t *mask) +{ + send_nmi_mask(mask, LOCAL_NMI_BACKTRACE); +} + void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) { - nmi_trigger_cpumask_backtrace(mask, exclude_cpu, riscv_backtrace_ipi); + if (!nmi_support()) + nmi_trigger_cpumask_backtrace(mask, exclude_cpu, + riscv_backtrace_ipi); + else + nmi_trigger_cpumask_backtrace(mask, exclude_cpu, + riscv_backtrace_nmi); } =20 #ifdef CONFIG_KGDB diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index 0ff0bda53608a..cac940b7e8773 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -3,6 +3,7 @@ #define pr_fmt(fmt) "SSE NMI: " fmt =20 #include +#include #include #include =20 @@ -56,6 +57,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct p= t_regs *regs) =20 NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); 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Mon, 17 Nov 2025 18:51:29 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 7/8] riscv: smp: kgdb: Use NMI for CPU roundup Date: Tue, 18 Nov 2025 10:50:14 +0800 Message-Id: <20251118025015.42491-8-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use NMI for kgdb CPU roundup if RISC-V SSE NMI is available. Signed-off-by: Yunhui Cui --- arch/riscv/kernel/smp.c | 5 ++++- drivers/firmware/riscv/riscv_sse_nmi.c | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 26083fe0a5df6..b1cefb2b0b8c2 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -382,7 +382,10 @@ void kgdb_roundup_cpus(void) if (cpu =3D=3D this_cpu) continue; =20 - send_ipi_single(cpu, IPI_KGDB_ROUNDUP); + if (!nmi_support()) + send_ipi_single(cpu, IPI_KGDB_ROUNDUP); + else + send_nmi_single(cpu, LOCAL_NMI_KGDB); } } #endif diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index cac940b7e8773..5035d4ec485f6 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -3,6 +3,7 @@ #define pr_fmt(fmt) "SSE NMI: " fmt =20 #include +#include #include #include #include @@ -58,6 +59,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct p= t_regs *regs) NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); 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Mon, 17 Nov 2025 18:51:39 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.241]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c234809sm156022065ad.19.2025.11.17.18.51.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 17 Nov 2025 18:51:38 -0800 (PST) From: Yunhui Cui To: conor@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, jassisinghbrar@gmail.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, arnd@arndb.de, kees@kernel.org, tglx@linutronix.de, viresh.kumar@linaro.org, boqun.feng@gmail.com, linux-arm-kernel@lists.infradead.org, cleger@rivosinc.com, atishp@rivosinc.com, ajones@ventanamicro.com Subject: [PATCH v2 8/8] drivers: firmware: riscv: add unknown nmi support Date: Tue, 18 Nov 2025 10:50:15 +0800 Message-Id: <20251118025015.42491-9-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251118025015.42491-1-cuiyunhui@bytedance.com> References: <20251118025015.42491-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register unknown_nmi_handler() as the handler for the UNKNOWN_NMI event. When the system becomes unresponsive, unknown_nmi_handler() can be manually triggered, which in turn invokes nmi_panic() to collect vmcore for root cause analysis. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/sbi.h | 1 + drivers/firmware/riscv/riscv_sse_nmi.c | 68 ++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 874cc1d7603a5..52d3fdf2d4cc1 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -486,6 +486,7 @@ enum sbi_sse_attr_id { #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS 0x00100000 #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS 0x00108000 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED 0xffff0000 +#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI 0xffff0001 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED 0xffff8000 =20 #define SBI_SSE_EVENT_PLATFORM BIT(14) diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/risc= v/riscv_sse_nmi.c index 5035d4ec485f6..e895abf583bd5 100644 --- a/drivers/firmware/riscv/riscv_sse_nmi.c +++ b/drivers/firmware/riscv/riscv_sse_nmi.c @@ -7,6 +7,7 @@ #include #include #include +#include =20 #include #include @@ -16,7 +17,10 @@ do { if (type & (mask)) func(__VA_ARGS__); } while (0) =20 bool nmi_available; +static int unknown_nmi_panic; static struct sse_event *local_nmi_evt; +static struct sse_event *unknown_nmi_evt; +static struct ctl_table_header *unknown_nmi_sysctl_header; static atomic_t local_nmi_arg =3D ATOMIC_INIT(LOCAL_NMI_NONE); =20 bool nmi_support(void) @@ -51,6 +55,35 @@ void send_nmi_mask(cpumask_t *mask, enum local_nmi_type = type) send_nmi_single(cpu, type); } =20 +static int __init setup_unknown_nmi_panic(char *str) +{ + unknown_nmi_panic =3D 1; + return 1; +} +__setup("unknown_nmi_panic", setup_unknown_nmi_panic); + +static const struct ctl_table unknown_nmi_table[] =3D { + { + .procname =3D "unknown_nmi_panic", + .data =3D &unknown_nmi_panic, + .maxlen =3D sizeof(bool), + .mode =3D 0644, + .proc_handler =3D proc_dobool, + }, +}; + +static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) +{ + pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id()); + + if (unknown_nmi_panic) + nmi_panic(regs, "NMI: Not continuing"); + + pr_emerg("Dazed and confused, but trying to continue\n"); + + return 0; +} + static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) { enum local_nmi_type type =3D atomic_read((atomic_t *)arg); @@ -66,6 +99,35 @@ static int local_nmi_handler(u32 evt, void *arg, struct = pt_regs *regs) return 0; } =20 +static int unknown_nmi_init(void) +{ + int ret; + + unknown_nmi_evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI, 0, + unknown_nmi_handler, NULL); + if (IS_ERR(unknown_nmi_evt)) + return PTR_ERR(unknown_nmi_evt); + + ret =3D sse_event_enable(unknown_nmi_evt); + if (ret) + goto err_unregister; + + unknown_nmi_sysctl_header =3D register_sysctl("kernel", unknown_nmi_table= ); + if (!unknown_nmi_sysctl_header) { + ret =3D -ENOMEM; + goto err_disable; + } + + pr_info("Using SSE for unknown NMI event delivery\n"); + return 0; + +err_disable: + sse_event_disable(unknown_nmi_evt); +err_unregister: + sse_event_unregister(unknown_nmi_evt); + return ret; +} + static int __init local_nmi_init(void) { int ret; @@ -98,6 +160,12 @@ static int __init sse_nmi_init(void) =20 WRITE_ONCE(nmi_available, true); =20 + ret =3D unknown_nmi_init(); + if (ret) { + pr_err("Unknown_nmi_init failed with error %d\n", ret); + return ret; + } + return 0; } =20 --=20 2.39.5