From nobody Tue Dec 2 02:57:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71DDE302175 for ; Tue, 18 Nov 2025 07:17:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763450261; cv=none; b=PzaqMKCyj5jiDemVfnqdC9sPjawzrVXCn79PxFGuRBtmCyP+ABjUx6+auKLNfFaft+AeQ8P6ZLc0KEsy+Xv7lmbyjKv9drMeH8sSS9e8iOOAxJ17qKs3TRdIlor70hdw3FZeGVE7nclkRSeKqyKp++KcWju0q4rFGqau2rgVnCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763450261; c=relaxed/simple; bh=TGLkXxO2JG2AYEoAIVewlDsW32+17NCrfzYjXohe2Ks=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hXG4+Pl3v+YOdLv0cavk7s0Fobn6Ykx1nR79R4fQEw5x2Ug36FizE8O1qt/L81Bi6nd3IBfnUYogusu5AXpAl7W5VuO0z2NL4h6Ke1M8YLQuey3cwZO7cn7GrBz9S8cWplK5Uykjgnjc3B/luL1ruXAeo6lTL6UpZH/jpECcZqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=AiSJxmkS; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=HHUgRXIA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="AiSJxmkS"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="HHUgRXIA" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AI0tPmv4166689 for ; Tue, 18 Nov 2025 07:17:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 0ex/dwTsOBdc0Oabutv/KMv+YQVe5juRm25Xb1v7EFo=; b=AiSJxmkSQn7Et3VG xaI12/SSzF/fp8QW4R2m1EsTdTbI0bozKKv0v1SVvDRgjnT1przNg/Q5KHkHCxdk bMoVN3gQ43/32qchuwPVbZNkr5vIKzkWFzeVCexmAajhHdmz7yq4PbSYbLnjVPLT yxeVKT/HGeL8O3WHaO1cifKa6smHVIjj1AQu7JaaqypSDypnRND9JJrG1OHZmfOu eAUEhM0uz9YgTCt6+lL48x0IudqDA+OLCL381KUZOpB16aAHG9SBua/cP3AD42Vo lZ1JaFsGsLsx/SEJRqJqqoo3sjKTK8xytRnpPMGy/g1zveeHtgrqo8EW5OobrzmO NhcNeA== Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ag593tkk1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 18 Nov 2025 07:17:38 +0000 (GMT) Received: by mail-pj1-f70.google.com with SMTP id 98e67ed59e1d1-340c07119bfso14327963a91.2 for ; Mon, 17 Nov 2025 23:17:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763450257; x=1764055057; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0ex/dwTsOBdc0Oabutv/KMv+YQVe5juRm25Xb1v7EFo=; b=HHUgRXIA59SLg6o4DFnWhq4MuriKESgwNfR84KGq1QOhKyhL6UcI+Dg/AkmF0IPYdC Xro7Vr6a6pRY+w1q6EWe3IZkm/PHf9xRZWVCp8Ps6xBjii+ENdiwrxpNSL7axLO47U0F pL7qy+D/mYOzdUG8M5o1OfmC+/c6QMW6Qjr+aQS3IRKb7+rP+qx1BNzZEGVEUn3QM2UV rsCrL7U3gzkpKsA2Vj8i68FxkH6/IezSd6F4nd9G0DH1ns5oyodXysAqdL6h+Ye+riYX hsbBKEfBU9lZ2/k8dRcqK1AaE3J+rX2eGim5/57cVFRNZ+b/vBe9Ki+WakQHwujy6kra Amig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763450257; x=1764055057; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=0ex/dwTsOBdc0Oabutv/KMv+YQVe5juRm25Xb1v7EFo=; b=LvF0bW+tisUPSUIir3Mt1bYfiCNhHlBphVAt/kjOb11Hd8YMhZvJlurPQvV9CveLWe ffEOd9yj2Atx1OQ80/UYYLdSoW5gLNUvoNRqPRJ7RZIYs45Hf3vEYnvkqxCX1o7F2kIT 32EaRQPKV0v8xYrQYp1SRMGubKvMW3itVyPwJeUUoEmlcQRv9uGssjc4MWBGiyc2Sf/s 5LSOEwnIUh1Yk59ECDZS44Ry9W81SUDZcl8AWaA9efvW4Mza7x8eExhnkh3PvTGsTMpX CgCGtV2KmKLvG432SD/k7/RY+NVKVD0WpxDiaY5ppyrw4LvDMNuX4wTTDb770j5zhSxu 4nRw== X-Forwarded-Encrypted: i=1; AJvYcCUQkMbQOUL4v7zzVshVT488iV+escTUtdRJSVtK/M30hjCcT+ogvegpKPvum5c0pP/OPwf6WJQuFY7iBZU=@vger.kernel.org X-Gm-Message-State: AOJu0Yymc4xm2CoNIWgB0n+jLbtGEWbAAVC75Ck+flzBblfF2lmM/y+X pMbMyMNnFEYYF4s39mBqLaXhrdjxsOOWOlRqn6gJouEmcR8ONRziECatHcvshaEiF62dOWtXK8x yfdsgkvS4Gh4LWyYFdbMaVPAqRGb+0daDyN2rwdzxVXAfx/LWXEqImWDzhn1ZsC6Zpqg= X-Gm-Gg: ASbGncs7a+zMHsOPpKhq1/X6/aLYBofT/w1OEkCn6l+ttgkMFoNYUsi7WjCq7bwZdTT WezM+km459SXo4iPKETMh4mWToridn1XHmAyonaBAuMyuw82rbJ7x6Qgy+m8eDqeYIvLbB8+w5p mpuDkObiwPU/L43TyHQVQqHnImtnZ0YI4Fzizv+bAhFderO+vtmrkSGZGHypxDJuCtMUDjemMuH H/T/mlK6Jlj7zKXafTgUQOvRicXEpJ1hXPc+Q92qIHOIdboV3+jkZL7Nceh/+TzGtvPrjhbB/7B m9aJCBpZmG0cIXeNxhQLAVZJr6yms9TjeRS3QhBtBEytizgHo809/9z4fMR4WKDAx83Hhus3o+Y +ToYhmOyPy86O1g1Dr/lIK0+n0OOIwV6N7g== X-Received: by 2002:a17:902:ef06:b0:298:595d:3d3a with SMTP id d9443c01a7336-2986a7566edmr160902755ad.50.1763450257370; Mon, 17 Nov 2025 23:17:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IHNe6X33EUjIJ9RH4k/tw/wo5j2bb0naJDZpb6jxguUoR6oC+zL3ECu1zXuNCf1fQMWVg5kxA== X-Received: by 2002:a17:902:ef06:b0:298:595d:3d3a with SMTP id d9443c01a7336-2986a7566edmr160902335ad.50.1763450256827; Mon, 17 Nov 2025 23:17:36 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2986a60b116sm129955285ad.79.2025.11.17.23.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 23:17:36 -0800 (PST) From: Taniya Das Date: Tue, 18 Nov 2025 12:47:09 +0530 Subject: [PATCH v4 5/5] clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-sm8750-videocc-v2-v4-5-049882a70c9f@oss.qualcomm.com> References: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> In-Reply-To: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Jagadeesh Kona , Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=AKSYvs3t c=1 sm=1 tr=0 ts=691c1d92 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=2N9sESmJbKjiMZoAsBIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA1NiBTYWx0ZWRfX8C5DufRhV9c3 1qaCW8xj97Lx+vrr5jNtgA/BgwiIrNtbgwKpYpqeKL0eiib2dfOnSvS4jeYoClaQcWPW9oiJJnD i6AOAZ7UGseEtd/roGpygD02r8A4LIQ5oa5BckBdAhV/7BBHaz19FUcEinD57bPrETfF766t+wo VXkj1fg0icXaoXMPP3y/91NH2TREWLYrdkEU9Q/wnrNY9+tSKaudvcLNCUwPBVQ95KVIq/g2gnx f+/1cLAQr9Ailu954O4cN9t2RFNCoHtGP1ILEw5RNyP7RRcXh53HJ+bRdukK68RiNMpTmfnBa0e h/+Jg1qOoyvvZLWzmrC1N1SXRrl8adDSMxJMJcZEsn+esgHwOvQhS384fHlVwOdIv4cgV7oNCk/ hRK3iHjpLjbFVRtB1Pd+IoPja0iMqg== X-Proofpoint-ORIG-GUID: MASpRRyWexezMlK8SlFkOvW1UwP-8nmf X-Proofpoint-GUID: MASpRRyWexezMlK8SlFkOvW1UwP-8nmf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180056 Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8750 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8750.c | 463 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 475 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index aeb6197d7c902098459c9b2cba75072bd519b0f3..2c5a0c86e01f0bf2518e5b78a9f= 50835fac3d019 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1489,6 +1489,17 @@ config SM_VIDEOCC_8550 Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config SM_VIDEOCC_8750 + tristate "SM8750 Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + select QCOM_GDSC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + SM8750 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 98de55eb64026a12d89587db295f8a6ac59ee2f7..fccb7eb5135dc4df3ccadf711f2= c7b9ce0459a83 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -181,6 +181,7 @@ obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o obj-$(CONFIG_SM_VIDEOCC_8350) +=3D videocc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8450) +=3D videocc-sm8450.o obj-$(CONFIG_SM_VIDEOCC_8550) +=3D videocc-sm8550.o +obj-$(CONFIG_SM_VIDEOCC_8750) +=3D videocc-sm8750.o obj-$(CONFIG_SM_VIDEOCC_MILOS) +=3D videocc-milos.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) +=3D kpss-xcc.o diff --git a/drivers/clk/qcom/videocc-sm8750.c b/drivers/clk/qcom/videocc-s= m8750.c new file mode 100644 index 0000000000000000000000000000000000000000..0acf3104d702b69eae8fe961c7f= 85f93715fd271 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8750.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1710000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1890000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x80e0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_2_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x80bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0x809c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x8060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x807c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch video_cc_mvs0_freerun_clk =3D { + .mem_enable_reg =3D 0x8090, + .mem_ack_reg =3D 0x8090, + .mem_enable_mask =3D BIT(3), + .mem_enable_ack_mask =3D GENMASK(11, 10), + .mem_enable_invert =3D true, + .branch =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x80dc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80dc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x8034, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x8068, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct clk_regmap *video_cc_sm8750_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.branch.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_sm8750_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_sm8750_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x80a0 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x8064 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x804c, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8030 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x808c, 2 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x805c, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x80d4, 2 }, +}; + +static const struct regmap_config video_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f4c, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *video_cc_sm8750_plls[] =3D { + &video_cc_pll0, +}; + +static u32 video_cc_sm8750_critical_cbcrs[] =3D { + 0x80a4, /* VIDEO_CC_AHB_CLK */ + 0x80f8, /* VIDEO_CC_SLEEP_CLK */ + 0x80d4, /* VIDEO_CC_XO_CLK */ +}; + +static void clk_sm8750_regs_configure(struct device *dev, struct regmap *r= egmap) +{ + /* Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for mvs0, mvs0c */ + regmap_update_bits(regmap, 0x8074, GENMASK(25, 21), GENMASK(25, 21)); + regmap_update_bits(regmap, 0x8040, GENMASK(25, 21), GENMASK(25, 21)); + + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); +} + +static struct qcom_cc_driver_data video_cc_sm8750_driver_data =3D { + .alpha_plls =3D video_cc_sm8750_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_sm8750_plls), + .clk_cbcrs =3D video_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_sm8750_critical_cbcrs), + .clk_regs_configure =3D clk_sm8750_regs_configure, +}; + +static struct qcom_cc_desc video_cc_sm8750_desc =3D { + .config =3D &video_cc_sm8750_regmap_config, + .clks =3D video_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sm8750_clocks), + .resets =3D video_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(video_cc_sm8750_resets), + .gdscs =3D video_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sm8750_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_sm8750_driver_data, +}; + +static const struct of_device_id video_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8750_match_table); + +static int video_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_sm8750_desc); +} + +static struct platform_driver video_cc_sm8750_driver =3D { + .probe =3D video_cc_sm8750_probe, + .driver =3D { + .name =3D "video_cc-sm8750", + .of_match_table =3D video_cc_sm8750_match_table, + }, +}; + +static int __init video_cc_sm8750_init(void) +{ + return platform_driver_register(&video_cc_sm8750_driver); +} +subsys_initcall(video_cc_sm8750_init); + +static void __exit video_cc_sm8750_exit(void) +{ + platform_driver_unregister(&video_cc_sm8750_driver); +} +module_exit(video_cc_sm8750_exit); + +MODULE_DESCRIPTION("QTI VIDEO_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1