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Mon, 17 Nov 2025 23:17:22 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2986a60b116sm129955285ad.79.2025.11.17.23.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 23:17:22 -0800 (PST) From: Taniya Das Date: Tue, 18 Nov 2025 12:47:06 +0530 Subject: [PATCH v4 2/5] clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com> References: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> In-Reply-To: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Jagadeesh Kona , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=AKSYvs3t c=1 sm=1 tr=0 ts=691c1d84 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=02cEW-DpipR3T3ESWNEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA1NiBTYWx0ZWRfX0tOSwA/kYDJu pAR2B2R+FzLWzMJyh7LXSB6zXzWyFlPWnPQuL5O1VzG7QV12DoN1Bqn4yvr86ZL/vM/r5st9e2X g3Zz3XgPTW4/UkMxFxO81YZ/EEgbNNEDaC2SJgM4GpE7oMo05bHHN716kQzydyQKxIulX0WPFUq b1oEJkZ5j2qaJVSu+vNydrOnK6792dhxl1oK87XdEdm9jVNHrB0lnyvBbodHTFRDpsLWOaAdJvy qAdUXN7GohgIYjVWQrrIyD1o2IuP8oNSU55TSFMdP0IELZMNUd0gQgAbq7kesTolKBtwe552F9V EL1ufIOlYxluTA0cpSJu1i7E5qotDEO+OA+6HJ0NZNfclBhy8fcJRyEvC24py0gbzABlgEYGE21 P/gBjBIVsVKBo2JgAEX5lVH2qhD3dA== X-Proofpoint-ORIG-GUID: 1LIVsl7RFQx1HFg-vgjHt29jf0qiiQkA X-Proofpoint-GUID: 1LIVsl7RFQx1HFg-vgjHt29jf0qiiQkA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180056 The ECPRI clock controller=E2=80=99s mem_ops clocks used the mem_enable_ack= _mask directly for both setting and polling. Add the newly introduced 'mem_enable_mask' to the memory control branch clocks of ECPRI clock controller to align to the new mem_ops handling. Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/ecpricc-qdu1000.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-= qdu1000.c index dbc11260479b6d25d52a7d00cfce78d4e35be224..c2a16616ed64508355a3d545572= 95cef24dfdf2f 100644 --- a/drivers/clk/qcom/ecpricc-qdu1000.c +++ b/drivers/clk/qcom/ecpricc-qdu1000.c @@ -920,6 +920,7 @@ static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fif= o_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x80b4, @@ -943,6 +944,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm= _ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x80bc, @@ -966,6 +968,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm= _ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x80ac, @@ -989,6 +992,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_m= acsec_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x80d8, @@ -1012,6 +1016,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2= c_hm_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x80e0, @@ -1053,6 +1058,7 @@ static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_ud= p_fifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x800c, @@ -1076,6 +1082,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x8014, @@ -1099,6 +1106,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x801c, @@ -1122,6 +1130,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x8024, @@ -1163,6 +1172,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x8044, @@ -1186,6 +1196,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x804c, @@ -1209,6 +1220,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x8054, @@ -1232,6 +1244,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x805c, @@ -1273,6 +1286,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x807c, @@ -1296,6 +1310,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x8084, @@ -1319,6 +1334,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x808c, @@ -1342,6 +1358,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x8094, @@ -1383,6 +1400,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x8004, @@ -1406,6 +1424,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x803c, @@ -1429,6 +1448,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x8074, @@ -1452,6 +1472,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x80c4, @@ -1475,6 +1496,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2= c_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x80e8, @@ -1498,6 +1520,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_db= g_c2c_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x802c, @@ -1521,6 +1544,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh= 0_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x8064, @@ -1544,6 +1568,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh= 1_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x809c, @@ -1603,6 +1628,7 @@ static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk= =3D { static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd140, @@ -1621,6 +1647,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841C, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd148, @@ -1639,6 +1666,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd150, @@ -1657,6 +1685,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd158, @@ -1675,6 +1704,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd160, --=20 2.34.1