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Mon, 17 Nov 2025 23:17:18 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2986a60b116sm129955285ad.79.2025.11.17.23.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 23:17:18 -0800 (PST) From: Taniya Das Date: Tue, 18 Nov 2025 12:47:05 +0530 Subject: [PATCH v4 1/5] clk: qcom: clk_mem_branch: add enable mask and invert flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-sm8750-videocc-v2-v4-1-049882a70c9f@oss.qualcomm.com> References: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> In-Reply-To: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Jagadeesh Kona , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: Iacu-GtDJcvu057qfV9W50-sSeZn-QoV X-Proofpoint-ORIG-GUID: Iacu-GtDJcvu057qfV9W50-sSeZn-QoV X-Authority-Analysis: v=2.4 cv=G6sR0tk5 c=1 sm=1 tr=0 ts=691c1d7f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=uR87BbDKUCx-STIg3aMA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA1NiBTYWx0ZWRfXzOCJbHTifh6b qwixNAf0mVnpZishpCr5HEG9uE8Wi+uEoQz2tiFWdRn5rMebb232wFRFbYzH5NFR9kXtm+OH8Cj FUOX6YMhtAtvHASNAfeRCRqTf3cv2HMGSgiFScrsLQN3NvC+ji3IKR8yYiRrXXnvZeG/LmfhQ8f ntG7F1Fve/g6CwAL7YkQiNqIUsU/PkepLMetdcjHMlBLukfVn3tT/xvCYr5T6H1xNJG5rXyO5PD WhUNEGPtxiuhk5Zmoih7uKv5/gdscroz5UWpBFuJInDEt30sctvTK8RuMjMvcECN1svWs1wrMuD pFUPWiIG9/ij3eSeBY/i7eXhJLb5Apy/1IzU8QlxIdRQHc/KPYxvBZIgy9Zmd2NAQZQWjpjghqs 2Ahg23BdWFjqvv3oCr7rOYduPsgRgw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180056 Introduce mem_enable_mask and mem_enable_invert in clk_mem_branch to describe memory gating implementations that use a separate mask and/or inverted enable logic. This documents hardware behavior in data instead of code and will be used by upcoming platform descriptions. Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 292756435f53648640717734af198442a315272e..6bc2ba2b5350554005b7f0c84f9= 33580b7582fc7 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -44,6 +44,8 @@ struct clk_branch { * @mem_enable_reg: branch clock memory gating register * @mem_ack_reg: branch clock memory ack register * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_= ack_reg + * @mem_enable_mask: branch clock memory enable mask + * @mem_enable_invert: branch clock memory enable and disable has invert l= ogic * @branch: branch clock gating handle * * Clock which can gate its memories. @@ -52,6 +54,8 @@ struct clk_mem_branch { u32 mem_enable_reg; u32 mem_ack_reg; u32 mem_enable_ack_mask; + u32 mem_enable_mask; + bool mem_enable_invert; struct clk_branch branch; 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Add the newly introduced 'mem_enable_mask' to the memory control branch clocks of ECPRI clock controller to align to the new mem_ops handling. Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/ecpricc-qdu1000.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-= qdu1000.c index dbc11260479b6d25d52a7d00cfce78d4e35be224..c2a16616ed64508355a3d545572= 95cef24dfdf2f 100644 --- a/drivers/clk/qcom/ecpricc-qdu1000.c +++ b/drivers/clk/qcom/ecpricc-qdu1000.c @@ -920,6 +920,7 @@ static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fif= o_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x80b4, @@ -943,6 +944,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm= _ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x80bc, @@ -966,6 +968,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm= _ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x80ac, @@ -989,6 +992,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_m= acsec_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x80d8, @@ -1012,6 +1016,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2= c_hm_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x80e0, @@ -1053,6 +1058,7 @@ static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_ud= p_fifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x800c, @@ -1076,6 +1082,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x8014, @@ -1099,6 +1106,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x801c, @@ -1122,6 +1130,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x8024, @@ -1163,6 +1172,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x8044, @@ -1186,6 +1196,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x804c, @@ -1209,6 +1220,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x8054, @@ -1232,6 +1244,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x805c, @@ -1273,6 +1286,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(0), .mem_enable_ack_mask =3D BIT(0), .branch =3D { .halt_reg =3D 0x807c, @@ -1296,6 +1310,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(1), .mem_enable_ack_mask =3D BIT(1), .branch =3D { .halt_reg =3D 0x8084, @@ -1319,6 +1334,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(2), .mem_enable_ack_mask =3D BIT(2), .branch =3D { .halt_reg =3D 0x808c, @@ -1342,6 +1358,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_h= m_ff_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(3), .mem_enable_ack_mask =3D BIT(3), .branch =3D { .halt_reg =3D 0x8094, @@ -1383,6 +1400,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_f= ifo_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x8004, @@ -1406,6 +1424,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_0_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x803c, @@ -1429,6 +1448,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_1_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(4), .mem_enable_ack_mask =3D BIT(4), .branch =3D { .halt_reg =3D 0x8074, @@ -1452,6 +1472,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_mac= sec_2_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x80c4, @@ -1475,6 +1496,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2= c_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x80e8, @@ -1498,6 +1520,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_db= g_c2c_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x802c, @@ -1521,6 +1544,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh= 0_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841c, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x8064, @@ -1544,6 +1568,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh= 1_hm_ref_clk =3D { static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(5), .mem_enable_ack_mask =3D BIT(5), .branch =3D { .halt_reg =3D 0x809c, @@ -1603,6 +1628,7 @@ static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk= =3D { static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk =3D { .mem_enable_reg =3D 0x8404, .mem_ack_reg =3D 0x8418, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd140, @@ -1621,6 +1647,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk =3D { .mem_enable_reg =3D 0x8408, .mem_ack_reg =3D 0x841C, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd148, @@ -1639,6 +1666,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk =3D { .mem_enable_reg =3D 0x840c, .mem_ack_reg =3D 0x8420, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd150, @@ -1657,6 +1685,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk =3D { .mem_enable_reg =3D 0x8410, .mem_ack_reg =3D 0x8424, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 0xd158, @@ -1675,6 +1704,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_s= ram_clk =3D { static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk =3D { .mem_enable_reg =3D 0x8414, .mem_ack_reg =3D 0x8428, + .mem_enable_mask =3D BIT(6), .mem_enable_ack_mask =3D BIT(6), .branch =3D { .halt_reg =3D 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definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180056 Some clock branches require inverted logic for memory gating, where disabling the memory involves setting a bit and enabling it involves clearing the same bit. This behavior differs from the standard approach memory branch clocks ops where enabling typically sets the bit. The mem_enable_invert to allow conditional handling of these sequences of the inverted control logic for memory operations required on those memory clock branches. Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 0f10090d4ae681babbdbbb1b6c68ffe77af7a784..16d85b2fe1d39be2b0c14ea1bfc= 305c42c685f58 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -142,8 +142,8 @@ static int clk_branch2_mem_enable(struct clk_hw *hw) u32 val; int ret; =20 - regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, - mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); + regmap_assign_bits(branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_mask, !mem_br->mem_enable_invert); =20 ret =3D regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, val, val & mem_br->mem_enable_ack_mask, 0, 200); @@ -159,8 +159,8 @@ static void clk_branch2_mem_disable(struct clk_hw *hw) { struct clk_mem_branch *mem_br =3D to_clk_mem_branch(hw); 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Signed-off-by: Taniya Das Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/qcom,sm8450-videocc.yaml | 5 ++- include/dt-bindings/clock/qcom,sm8750-videocc.h | 40 ++++++++++++++++++= ++++ 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index fcd2727dae46711650fc8fe71221a06630040026..b31bd833552937fa896f69966cf= e5c79d9cfdd21 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Video Clock & Reset Controller on SM8450 =20 maintainers: - - Taniya Das + - Taniya Das - Jagadeesh Kona =20 description: | @@ -17,6 +17,7 @@ description: | See also: include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h + include/dt-bindings/clock/qcom,sm8750-videocc.h =20 properties: compatible: @@ -25,6 +26,7 @@ properties: - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc + - qcom,sm8750-videocc - qcom,x1e80100-videocc =20 clocks: @@ -61,6 +63,7 @@ allOf: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8750-videocc then: required: - required-opps diff --git a/include/dt-bindings/clock/qcom,sm8750-videocc.h b/include/dt-b= indings/clock/qcom,sm8750-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..f3bfa2ba51607d0133efcdad9c7= 729eb7a49b177 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_FREERUN_CLK 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_FREERUN_CLK 9 +#define VIDEO_CC_MVS0C_SHIFT_CLK 10 +#define VIDEO_CC_PLL0 11 +#define VIDEO_CC_SLEEP_CLK 12 +#define VIDEO_CC_SLEEP_CLK_SRC 13 +#define VIDEO_CC_XO_CLK 14 +#define VIDEO_CC_XO_CLK_SRC 15 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5 +#define VIDEO_CC_XO_CLK_ARES 6 + +#endif --=20 2.34.1 From nobody Tue Dec 2 02:49:48 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71DDE302175 for ; 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Mon, 17 Nov 2025 23:17:36 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2986a60b116sm129955285ad.79.2025.11.17.23.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 23:17:36 -0800 (PST) From: Taniya Das Date: Tue, 18 Nov 2025 12:47:09 +0530 Subject: [PATCH v4 5/5] clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-sm8750-videocc-v2-v4-5-049882a70c9f@oss.qualcomm.com> References: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> In-Reply-To: <20251118-sm8750-videocc-v2-v4-0-049882a70c9f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Jagadeesh Kona , Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=AKSYvs3t c=1 sm=1 tr=0 ts=691c1d92 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=2N9sESmJbKjiMZoAsBIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA1NiBTYWx0ZWRfX8C5DufRhV9c3 1qaCW8xj97Lx+vrr5jNtgA/BgwiIrNtbgwKpYpqeKL0eiib2dfOnSvS4jeYoClaQcWPW9oiJJnD i6AOAZ7UGseEtd/roGpygD02r8A4LIQ5oa5BckBdAhV/7BBHaz19FUcEinD57bPrETfF766t+wo VXkj1fg0icXaoXMPP3y/91NH2TREWLYrdkEU9Q/wnrNY9+tSKaudvcLNCUwPBVQ95KVIq/g2gnx f+/1cLAQr9Ailu954O4cN9t2RFNCoHtGP1ILEw5RNyP7RRcXh53HJ+bRdukK68RiNMpTmfnBa0e h/+Jg1qOoyvvZLWzmrC1N1SXRrl8adDSMxJMJcZEsn+esgHwOvQhS384fHlVwOdIv4cgV7oNCk/ hRK3iHjpLjbFVRtB1Pd+IoPja0iMqg== X-Proofpoint-ORIG-GUID: MASpRRyWexezMlK8SlFkOvW1UwP-8nmf X-Proofpoint-GUID: MASpRRyWexezMlK8SlFkOvW1UwP-8nmf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180056 Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8750 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8750.c | 463 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 475 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index aeb6197d7c902098459c9b2cba75072bd519b0f3..2c5a0c86e01f0bf2518e5b78a9f= 50835fac3d019 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1489,6 +1489,17 @@ config SM_VIDEOCC_8550 Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config SM_VIDEOCC_8750 + tristate "SM8750 Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + select QCOM_GDSC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + SM8750 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 98de55eb64026a12d89587db295f8a6ac59ee2f7..fccb7eb5135dc4df3ccadf711f2= c7b9ce0459a83 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -181,6 +181,7 @@ obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o obj-$(CONFIG_SM_VIDEOCC_8350) +=3D videocc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8450) +=3D videocc-sm8450.o obj-$(CONFIG_SM_VIDEOCC_8550) +=3D videocc-sm8550.o +obj-$(CONFIG_SM_VIDEOCC_8750) +=3D videocc-sm8750.o obj-$(CONFIG_SM_VIDEOCC_MILOS) +=3D videocc-milos.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) +=3D kpss-xcc.o diff --git a/drivers/clk/qcom/videocc-sm8750.c b/drivers/clk/qcom/videocc-s= m8750.c new file mode 100644 index 0000000000000000000000000000000000000000..0acf3104d702b69eae8fe961c7f= 85f93715fd271 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8750.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1710000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1890000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x80e0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_2_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x80bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0x809c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x8060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x807c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch video_cc_mvs0_freerun_clk =3D { + .mem_enable_reg =3D 0x8090, + .mem_ack_reg =3D 0x8090, + .mem_enable_mask =3D BIT(3), + .mem_enable_ack_mask =3D GENMASK(11, 10), + .mem_enable_invert =3D true, + .branch =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x80dc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80dc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x8034, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x8068, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct clk_regmap *video_cc_sm8750_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.branch.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_sm8750_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_sm8750_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x80a0 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x8064 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x804c, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8030 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x808c, 2 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x805c, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x80d4, 2 }, +}; + +static const struct regmap_config video_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f4c, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *video_cc_sm8750_plls[] =3D { + &video_cc_pll0, +}; + +static u32 video_cc_sm8750_critical_cbcrs[] =3D { + 0x80a4, /* VIDEO_CC_AHB_CLK */ + 0x80f8, /* VIDEO_CC_SLEEP_CLK */ + 0x80d4, /* VIDEO_CC_XO_CLK */ +}; + +static void clk_sm8750_regs_configure(struct device *dev, struct regmap *r= egmap) +{ + /* Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for mvs0, mvs0c */ + regmap_update_bits(regmap, 0x8074, GENMASK(25, 21), GENMASK(25, 21)); + regmap_update_bits(regmap, 0x8040, GENMASK(25, 21), GENMASK(25, 21)); + + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); +} + +static struct qcom_cc_driver_data video_cc_sm8750_driver_data =3D { + .alpha_plls =3D video_cc_sm8750_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_sm8750_plls), + .clk_cbcrs =3D video_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_sm8750_critical_cbcrs), + .clk_regs_configure =3D clk_sm8750_regs_configure, +}; + +static struct qcom_cc_desc video_cc_sm8750_desc =3D { + .config =3D &video_cc_sm8750_regmap_config, + .clks =3D video_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sm8750_clocks), + .resets =3D video_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(video_cc_sm8750_resets), + .gdscs =3D video_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sm8750_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_sm8750_driver_data, +}; + +static const struct of_device_id video_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8750_match_table); + +static int video_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_sm8750_desc); +} + +static struct platform_driver video_cc_sm8750_driver =3D { + .probe =3D video_cc_sm8750_probe, + .driver =3D { + .name =3D "video_cc-sm8750", + .of_match_table =3D video_cc_sm8750_match_table, + }, +}; + +static int __init video_cc_sm8750_init(void) +{ + return platform_driver_register(&video_cc_sm8750_driver); +} +subsys_initcall(video_cc_sm8750_init); + +static void __exit video_cc_sm8750_exit(void) +{ + platform_driver_unregister(&video_cc_sm8750_driver); +} +module_exit(video_cc_sm8750_exit); + +MODULE_DESCRIPTION("QTI VIDEO_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1