From nobody Sat Feb 7 07:11:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6486310762 for ; Tue, 18 Nov 2025 08:52:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763455961; cv=none; b=LfwYJrJ66faiUM0C1tBGDEO7a9rEHhRxClMlexHh0nN4QonYoAm4Feq+NbmeRaDhPd1t5Xhhgxi+J4nCcT85ePCmfZPweQp+/T1iCF92PE6s0ZU2bEvzcxopiUdeLTG2Ka4HsKH6yQF33fZhJzlpu574H6E1UhU4tYwHsiYnFW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763455961; c=relaxed/simple; bh=LhwFqdN2Z7n0b/3haqROFi97DWeW1e45MN33dqohVcc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jkHO39BczpssPvQRQNdIe8m3ubjeJUIE6BZLO6b0EfGWIAYLYdOkXLTnEkLqIPZ5y+DT6EtfdD/7aDcASBZtZj2RcivK6TNfUkVutUdoRAXVTYkMXWSp5p7co68R1zAqio/JG6dGAGhU3isFT6ZiSmRdBcxb7w2VWzdqhWIFeNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NeT1kKaA; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=DCvGFpC6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NeT1kKaA"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="DCvGFpC6" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5AI8lDpE2755669 for ; Tue, 18 Nov 2025 08:52:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /7g2OKuSg98JcSl3vrLeYvBh8Jt1oxYXAVPORiW6MrY=; b=NeT1kKaABfzR/BB3 2VCBkQpXFdyhy//kDa5VdFH4Tm9TIXCRGQOslpe5ZUgpM+PEBPBuJcrvXDXZPbJb x5BLEM0cf9La2d+O5knuwTK0JYuZYxz7k/tzT4ma2j1kEuFE33/MbjBlv8ejsxFh qe1raIfaeycqBUyXdGYekS2G7H+88krj2swwXxe31mFwSW4NkJNEaA8M+mMqqXb7 DRW/okoPTIIDGIij2Zrn6dnrvfUqJnrIGqEP6K6yzNEg1Enhd41hh95GQTfB++Bo /oNxfiBSLdXs1/ZsbXoNiwU5xiS3/zSdvKxtzmZXDPwdAEoRkejAugCiomEuOJBF IoOEdA== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4agnkj00j7-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 18 Nov 2025 08:52:37 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2982b47ce35so61036155ad.2 for ; Tue, 18 Nov 2025 00:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1763455956; x=1764060756; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/7g2OKuSg98JcSl3vrLeYvBh8Jt1oxYXAVPORiW6MrY=; b=DCvGFpC6R68okQPm8pp+57wAFOLQg6vMg5ec/TXQ1DNBos91X5BtaLBaV23o1vd3sO hKi3ULfGbVUf5qJAcnRLFVJU6YEDMunAOYmRxxlPk72MiC2FsAgGgtJ7bXPipc2B8zLl yuPDfV8w+fuPnNRIbMNGkXnUznlsh0HKHVQIrrdBKtXTx3dEZQDiHJP3toYAwvB6P17A jfNAf3dpsHyoErGblKx735LWbDJseiqXCMkPjmYcsSotj2Te1/PqMHsRnADyaC0SwBJl HQ3iNl5f95M1RS+A+TYadf7dAn8ipaMH/C3807IzW1mD/BipsnJWpMJ3QIdPxYxOCJYD ra4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763455956; x=1764060756; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/7g2OKuSg98JcSl3vrLeYvBh8Jt1oxYXAVPORiW6MrY=; b=BeMXZ/TuevQjW+qLmzpjnkE3JskFoMra5yXKVJ1+kjW4cO0MZ9LzSTOAMbU3zyvziF OVK5gXkMLisLnKJgI0RUyz3fZarmtxKUsawZ/il4ZK8xdlUPAVsXtkelqRq0HIK5ksgw OonMUt1m2cKXYp+2Tb3jyr8UVGVDPfBP5z/YS5vug767lyCFXSugZPCjpSs3UA59fP2h EhSV2QE0S5LKoO5dhGfuNTb2G9epJZ/xjLsu+YFkZcBwJ1DagZtVTX3YOO5NdkMX0Vqg R5KQ5kiJg9wGCiB2iuG7W8nrCDgWefU0l/+6Dbc8FXC5wkjDJTlQw8pW9A/cMvBZCnF0 96ww== X-Forwarded-Encrypted: i=1; AJvYcCWNomUcWxHuwng+P2TRkEtqVTQLGtTF6/WCseW8rA6J8PKb6Im/6lsMfXseEsjDKwJrtKndCVe5J9PWUTc=@vger.kernel.org X-Gm-Message-State: AOJu0YxkJR9DaCUX9ZQCUFii4Qo3SiRTUq4xwo3A9QLBQunKgrhT75FQ 7KB/2ycaH1Z0/HbcjwoEPw51U/CfRqhBhYxesllgr3S6wdws6vYv1Ubv6fti9qZ6oJ/QvvwVNo0 EpSZKONRXCsTRFg04tF6FN209goYLxNReH5g6FP+RrIFJnhgeahpt2MYtMKVfaq0OAnI= X-Gm-Gg: ASbGncsKLVZpTBuMynNKi1+LeT0Xe5dgqhxi0GnckKd6351FIxzx6Qrgg/Ad5u0wrNc CRixxf8nan0XidvWkU/VcGfAhdey9ca9hl0+OjF6cDJdHBVtOJ6h0LgESAPZAAZhz0Pr7zZlPYC w84P6VrkXAhDRAt1V221OzxeC1NsqO5u9xiaIixzafs7YgD06pQHV5J6VQooQQHm/yxO+fV5H1Z MKof+hgeCv+oOJyfp8xXnItoCpYmze7fPPZ1mCfTy6w4kVhJgJ5dI2O+YSMscrkBLuoTxyAcBmK I2W8BRfP/LGhB7xYSsBpBYG6ezoHwL6A0KnGRrQZIASoJuR7T6lJoQV6vJYRpsxEt/U0k8YGmIN XWx56OmXPHYf01a4ECBRB2iU= X-Received: by 2002:a17:902:d60d:b0:27d:c542:fe25 with SMTP id d9443c01a7336-2986a7509eamr151666305ad.41.1763455955843; Tue, 18 Nov 2025 00:52:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IEaKKWg8VTkLpLm+WIizjRhJugezguXDK0qYctBty2k8hhQ32oWKVMzXXPVlxFUxwv+CmFd5Q== X-Received: by 2002:a17:902:d60d:b0:27d:c542:fe25 with SMTP id d9443c01a7336-2986a7509eamr151666035ad.41.1763455955222; Tue, 18 Nov 2025 00:52:35 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c2568c1sm162910695ad.47.2025.11.18.00.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 00:52:34 -0800 (PST) From: Akhil P Oommen Date: Tue, 18 Nov 2025 14:20:37 +0530 Subject: [PATCH v4 10/22] drm/msm/a6xx: Rebase GMU register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> References: <20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com> In-Reply-To: <20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763455868; l=31486; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=LhwFqdN2Z7n0b/3haqROFi97DWeW1e45MN33dqohVcc=; b=7e9crv4DLPT0wO9wMvi4dYMu7aLs9kr9TMfInbJ3ERgGtSIBWG/rnkDjZ7dOt2hHFXZpHjZK6 A9Q+4mcgrfuCsd+ltpwdQOgNJKnC+qa/AvXtOBidO2Pz5OYJFulzy7J X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-GUID: gjEtZNXwhpOI90AFFOyOmkIcKXp9XzqE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA2OSBTYWx0ZWRfX0jA5JTYC9dQh u66y0PIH7FcEA2vq64dASzEt7MgJaEDfkbB8rISxpwcEH5TrZjWPu04AJ3xlAvmKNLPhZ5I9rI+ wZny11eSIo6X7Dou8muuYRvIaCfEtusaWBHh26PXKq5WAMjMkVcNxlIAxfTmovSdo8o9m/7hwDy Z9D3OG7/tuhEtCzzqJGpzgsHC7AiyxCHBo9UENz3F8EgpQRiOy9RoJ9c0VOioigIll0SFLgLF42 tbIc87pwIDMJXd5/n1kn7MdBSOGxmommBtahERxL3MHOGWKKX3aT/Xj4J6S8JURhDT3zr801EkL CkixpCbDvrh+ZNvmXl/n2avTa8/o07R/hRl/FprumJ7K7gTCiqjUWoPTfBCbSlGVZJZZap3bxHL zlhbm8MI0RT3QIvhiFgDvKv3qoDdBA== X-Authority-Analysis: v=2.4 cv=cs+WUl4i c=1 sm=1 tr=0 ts=691c33d5 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=e5mUnYsNAAAA:8 a=EUspDBNiAAAA:8 a=-MIAqB6j9IGJsbAufOIA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-ORIG-GUID: gjEtZNXwhpOI90AFFOyOmkIcKXp9XzqE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180069 GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 100 +++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 56 ++--- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 +++++++++++-------= ---- 4 files changed, 221 insertions(+), 203 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index b0be246b44ab..a5aceb906827 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -610,22 +610,19 @@ static inline void pdc_write(void __iomem *ptr, u32 o= ffset, u32 value) writel(value, ptr + (offset << 2)); } =20 -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name); - static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct platform_device *pdev =3D to_platform_device(gmu->dev); - void __iomem *pdcptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc"); + void __iomem *pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu= _pdc"); u32 seqmem0_drv0_reg =3D REG_A6XX_RSCC_SEQ_MEM_0_DRV0; void __iomem *seqptr =3D NULL; uint32_t pdc_address_offset; bool pdc_in_aop =3D false; =20 if (IS_ERR(pdcptr)) - goto err; + return; =20 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) @@ -638,9 +635,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_address_offset =3D 0x30080; =20 if (!pdc_in_aop) { - seqptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); + seqptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq"); if (IS_ERR(seqptr)) - goto err; + return; } =20 /* Disable SDE clock gating */ @@ -730,12 +727,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) =20 /* ensure no writes happen before the uCode is fully written */ wmb(); - -err: - if (!IS_ERR_OR_NULL(pdcptr)) - iounmap(pdcptr); - if (!IS_ERR_OR_NULL(seqptr)) - iounmap(seqptr); } =20 /* @@ -1821,27 +1812,6 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gm= u) return 0; } =20 -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name) -{ - void __iomem *ret; - struct resource *res =3D platform_get_resource_byname(pdev, - IORESOURCE_MEM, name); - - if (!res) { - DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); - return ERR_PTR(-EINVAL); - } - - ret =3D ioremap(res->start, resource_size(res)); - if (!ret) { - DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); - return ERR_PTR(-EINVAL); - } - - return ret; -} - static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *= pdev, const char *name, irq_handler_t handler) { @@ -1892,7 +1862,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct platform_device *pdev =3D to_platform_device(gmu->dev); =20 mutex_lock(&gmu->lock); if (!gmu->initialized) { @@ -1921,8 +1890,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) qmp_put(gmu->qmp); =20 iounmap(gmu->mmio); - if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) - iounmap(gmu->rscc); gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 @@ -1949,10 +1916,38 @@ static int cxpd_notifier_cb(struct notifier_block *= nb, return 0; } =20 +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, + const char *name, resource_size_t *start) +{ + void __iomem *ret; + struct resource *res =3D platform_get_resource_byname(pdev, + IORESOURCE_MEM, name); + + if (!res) { + DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); + return ERR_PTR(-EINVAL); + } + + ret =3D ioremap(res->start, resource_size(res)); + if (!ret) { + DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); + return ERR_PTR(-EINVAL); + } + + if (start) + *start =3D res->start; + + return ret; +} + int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) { struct platform_device *pdev =3D of_find_device_by_node(node); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -1977,12 +1972,21 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) gmu->nr_clocks =3D ret; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_mmio; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); if (IS_ERR(gmu->cxpd)) { ret =3D PTR_ERR(gmu->cxpd); @@ -2024,10 +2028,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { + struct platform_device *pdev =3D of_find_device_by_node(node); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct platform_device *pdev =3D of_find_device_by_node(node); struct device_link *link; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -2122,15 +2129,24 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) goto err_memory; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_memory; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { - gmu->rscc =3D a6xx_gmu_get_mmio(pdev, "rscc"); + gmu->rscc =3D devm_platform_ioremap_resource_byname(pdev, "rscc"); if (IS_ERR(gmu->rscc)) { ret =3D -ENODEV; goto err_mmio; @@ -2208,8 +2224,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) =20 err_mmio: iounmap(gmu->mmio); - if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) - iounmap(gmu->rscc); free_irq(gmu->gmu_irq, gmu); free_irq(gmu->hfi_irq, gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 06cfc294016f..55b1c78daa8b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -68,6 +68,7 @@ struct a6xx_gmu { struct drm_gpuvm *vm; =20 void __iomem *mmio; + u32 mmio_offset; void __iomem *rscc; =20 int hfi_irq; @@ -130,20 +131,23 @@ struct a6xx_gmu { unsigned long status; }; =20 +#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset) + static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) { - return readl(gmu->mmio + (offset << 2)); + /* The 'offset' is based on GPU's start address. Adjust it */ + return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) { - writel(value, gmu->mmio + (offset << 2)); + writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) { - memcpy_toio(gmu->mmio + (offset << 2), data, size); + memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size); wmb(); } =20 @@ -160,17 +164,17 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u3= 2 lo, u32 hi) { u64 val; =20 - val =3D (u64) readl(gmu->mmio + (lo << 2)); - val |=3D ((u64) readl(gmu->mmio + (hi << 2)) << 32); + val =3D gmu_read(gmu, lo); + val |=3D ((u64) gmu_read(gmu, hi) << 32); =20 return val; } =20 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ - interval, timeout) + readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \ + cond, interval, timeout) #define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \ + readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val= , cond, \ interval, timeout) =20 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.h index 688b8ce02fdc..b49d8427b59e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -343,48 +343,48 @@ static const struct a6xx_registers a6xx_gbif_reglist = =3D =20 static const u32 a6xx_gmu_gx_registers[] =3D { /* GMU GX */ - 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b, - 0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b, - 0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b, - 0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084, - 0x0100, 0x012b, 0x0140, 0x0140, + 0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b, + 0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b, + 0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b, + 0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884, + 0x1a900, 0x1a92b, 0x1a940, 0x1a940, }; =20 static const u32 a6xx_gmu_cx_registers[] =3D { /* GMU CX */ - 0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a, - 0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c, - 0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089, - 0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0, - 0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140, - 0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154, - 0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165, - 0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc, - 0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201, + 0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a, + 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c, + 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889, + 0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0, + 0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940, + 0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954, + 0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965, + 0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc, + 0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01, /* GMU AO */ - 0x9300, 0x9316, 0x9400, 0x9400, + 0x23b00, 0x23b16, 0x23c00, 0x23c00, }; =20 static const u32 a6xx_gmu_gpucc_registers[] =3D { /* GPU CC */ - 0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b, - 0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40, - 0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002, - 0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402, - 0xb800, 0xb802, + 0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b, + 0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440, + 0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802, + 0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02, + 0x26000, 0x26002, /* GPU CC ACD */ - 0xbc00, 0xbc16, 0xbc20, 0xbc27, + 0x26400, 0x26416, 0x26420, 0x26427, }; =20 static const u32 a621_gmu_gpucc_registers[] =3D { /* GPU CC */ - 0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404, - 0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30, - 0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a, - 0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5, - 0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc, - 0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16, - 0xbe20, 0xbe2d, + 0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04, + 0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, + 0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a, + 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5, + 0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, + 0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616, + 0x26620, 0x2662d, }; =20 static const u32 a6xx_gmu_cx_rscc_registers[] =3D { diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index b15a242d974d..09b8a0b9c0de 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -40,56 +40,56 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + @@ -99,15 +99,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + - + - + @@ -119,71 +119,71 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -191,27 +191,27 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + =20 --=20 2.51.0