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So, use gmu_write() routines to write to this register. Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Cc: stable@vger.kernel.org Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index 838150ff49ab..d2d6b2fd3cba 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1255,7 +1255,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gp= u, return; =20 /* Set the fence to ALLOW mode so we can access the registers */ - gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); =20 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2], &a6xx_state->gmu_registers[3], false); --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 855C230F81F for ; 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Update a6xx_set_pagetable() to do this. While we are at it, sync both BV and BR before issuing a CP_RESET_CONTEXT_STATE command, to match the downstream sequence. Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 779c1da7c46d..e6393ef0fd78 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -224,7 +224,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, OUT_RING(ring, submit->seqno - 1); =20 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); - OUT_RING(ring, CP_SET_THREAD_BOTH); + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); =20 /* Reset state used to synchronize BR and BV */ OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1); @@ -235,7 +235,13 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_g= pu, CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS); =20 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); - OUT_RING(ring, CP_SET_THREAD_BR); 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Also, downstream does this w/a after moving the fence to allow mode. So do the same. Fixes: dbfbb376b50c ("drm/msm/a6xx: Add A621 support") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 72cd4fe0905c..52653ad376fc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -511,8 +511,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) * in the power down sequence not being fully executed. That in turn can * prevent CX_GDSC from collapsing. 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So skip dumping them during recovery. Suggested-by: Rob Clark Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e6393ef0fd78..c6b2fdb86c17 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1561,7 +1561,7 @@ static void a6xx_recover(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - int i, active_submits; + int active_submits; =20 adreno_dump_info(gpu); =20 @@ -1569,10 +1569,6 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Sometimes crashstate capture is skipped, so SQE should be halted here= again */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); =20 - for (i =3D 0; i < 8; i++) - DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 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IOW, they are backward compatible. So move its definition to adreno_common.xml. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 10 +- .../gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h | 412 +++++++++--------- .../gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h | 324 +++++++-------- .../gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 462 ++++++++++-------= ---- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4 +- .../gpu/drm/msm/registers/adreno/a7xx_enums.xml | 7 - .../gpu/drm/msm/registers/adreno/adreno_common.xml | 11 + 7 files changed, 617 insertions(+), 613 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.h index 1c18499b60bb..4c5fe627d368 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -575,7 +575,7 @@ struct gen7_sptp_cluster_registers { /* statetype: SP block state type for the cluster */ enum a7xx_statetype_id statetype; /* pipe_id: Pipe identifier */ - enum a7xx_pipe pipe_id; + enum adreno_pipe pipe_id; /* context_id: Context identifier */ int context_id; /* location_id: Location identifier */ @@ -801,10 +801,10 @@ static const char *a7xx_statetype_names[] =3D { }; =20 static const char *a7xx_pipe_names[] =3D { - A7XX_NAME(A7XX_PIPE_NONE), - A7XX_NAME(A7XX_PIPE_BR), - A7XX_NAME(A7XX_PIPE_BV), - A7XX_NAME(A7XX_PIPE_LPAC), + A7XX_NAME(PIPE_NONE), + A7XX_NAME(PIPE_BR), + A7XX_NAME(PIPE_BV), + A7XX_NAME(PIPE_LPAC), }; =20 static const char *a7xx_cluster_names[] =3D { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h index 04b49d385f9d..087473679893 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h @@ -82,85 +82,85 @@ static const u32 gen7_0_0_debugbus_blocks[] =3D { }; =20 static const struct gen7_shader_block gen7_0_0_shader_blocks[] =3D { - {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_5_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_6_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_7_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_CB_RAM, 0x390, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_TAG, 0x90, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA_2, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_TMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_SMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_STATE_DATA, 0x40, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_HWAVE_RAM, 0x100, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_L0_INST_BUF, 0x50, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_8_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_9_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_10_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_11_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_12_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, + {A7XX_TP0_TMO_DATA, 0x200, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_SMO_DATA, 0x80, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_1, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_0_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_1_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_2_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_3_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_4_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_5_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_6_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_7_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_CB_RAM, 0x390, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_TAG, 0x90, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_2, 0x200, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_TMO_TAG, 0x80, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_SMO_TAG, 0x80, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_STATE_DATA, 0x40, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_HWAVE_RAM, 0x100, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_L0_INST_BUF, 0x50, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_8_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_9_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_10_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_11_DATA, 0x800, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_12_DATA, 0x200, 4, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, }; =20 static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] =3D { @@ -303,7 +303,7 @@ static const u32 gen7_0_0_noncontext_rb_rbp_pipe_br_reg= isters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rbp_pipe_br_registe= rs), 8)); =20 -/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */ +/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BR */ static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] =3D { 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, @@ -313,7 +313,7 @@ static const u32 gen7_0_0_gras_cluster_gras_pipe_br_reg= isters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_br_registe= rs), 8)); =20 -/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */ +/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BV */ static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] =3D { 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, @@ -323,7 +323,7 @@ static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_reg= isters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_bv_registe= rs), 8)); =20 -/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */ static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] =3D { 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, 0x09b00, 0x09b08, @@ -331,7 +331,7 @@ static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registe= rs[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_br_registers),= 8)); =20 -/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */ static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] =3D { 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, 0x09b00, 0x09b08, @@ -339,7 +339,7 @@ static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registe= rs[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_bv_registers),= 8)); =20 -/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ +/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */ static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] =3D { 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811, 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829, @@ -355,7 +355,7 @@ static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_reg= isters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rac_cluster_ps_pipe_br_registe= rs), 8)); =20 -/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ +/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */ static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] =3D { 0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812, 0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a, @@ -370,7 +370,7 @@ static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_reg= isters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rbp_cluster_ps_pipe_br_registe= rs), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: = HLSQ_STATE */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_= STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = =3D { 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, @@ -381,7 +381,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq= _state_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_sta= te_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location= : HLSQ_STATE */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLS= Q_STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[= ] =3D { 0x0a9b0, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc, @@ -390,21 +390,21 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_= hlsq_state_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_s= tate_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: = HLSQ_DP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_= DP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] =3D= { 0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_= registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location= : HLSQ_DP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLS= Q_DP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = =3D { 0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_d= p_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: = SP_TOP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: SP_TO= P */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] =3D { 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8, 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, @@ -414,7 +414,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_t= op_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_r= egisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location= : SP_TOP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: SP_= TOP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = =3D { 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00, @@ -422,7 +422,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp= _top_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top= _registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: = uSPTP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: uSPTP= */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] =3D { 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3, @@ -432,7 +432,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_uspt= p_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_re= gisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location= : uSPTP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: uSP= TP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] =3D= { 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01, @@ -440,7 +440,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_us= ptp_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_= registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: = HLSQ_STATE */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: HLSQ_= STATE */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = =3D { 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a, @@ -453,7 +453,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq= _state_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_sta= te_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: = HLSQ_STATE */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: HLSQ_= STATE */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = =3D { 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a, @@ -466,7 +466,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq= _state_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_sta= te_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: = SP_TOP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: SP_TO= P */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] =3D { 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d, @@ -477,7 +477,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_t= op_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_r= egisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: = SP_TOP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: SP_TO= P */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] =3D { 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d, @@ -488,7 +488,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_t= op_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_r= egisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: = uSPTP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR Location: uSPTP= */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] =3D { 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867, @@ -498,7 +498,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_uspt= p_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_re= gisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: = uSPTP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV Location: uSPTP= */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] =3D { 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867, @@ -508,7 +508,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_uspt= p_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_re= gisters), 8)); =20 -/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */ +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] =3D { 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, @@ -516,35 +516,35 @@ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_= registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_br_regist= ers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: = HLSQ_STATE */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: HLSQ_= STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = =3D { 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_sta= te_registers), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: = SP_TOP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: SP_TO= P */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] =3D { 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_r= egisters), 8)); =20 -/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: = uSPTP */ +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV Location: uSPTP= */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] =3D { 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_re= gisters), 8)); =20 -/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */ +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BV */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] =3D { 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_regist= ers), 8)); =20 -/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */ +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] =3D { 0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, @@ -552,84 +552,84 @@ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpa= c_registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_regi= sters), 8)); =20 -/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */ +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BR */ static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] =3D { 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_br_regist= ers), 8)); =20 -/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */ +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: PIPE_BV */ static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] =3D { 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_regist= ers), 8)); =20 -/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */ static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] =3D { 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_br_registers)= , 8)); =20 -/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */ static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] =3D { 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_bv_registers)= , 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] =3D { 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_br_registers)= , 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] =3D { 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_bv_registers)= , 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */ +/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] =3D { 0x09101, 0x0910c, 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_br_registe= rs), 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */ +/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] =3D { 0x09101, 0x0910c, 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registe= rs), 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */ +/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] =3D { 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_br_regist= ers), 8)); =20 -/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */ +/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] =3D { 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_regist= ers), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STA= TE */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] =3D= { 0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae73, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_hlsq_state_= registers), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: SP_TOP */ static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] =3D { 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c, 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f, @@ -638,7 +638,7 @@ static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_= registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_sp_top_regi= sters), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: uSPTP */ static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] =3D { 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c, 0x0ae0f, 0x0ae0f, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3b, @@ -647,28 +647,28 @@ static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp= _registers[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_usptp_regis= ters), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_S= TATE */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: HLSQ_STATE = */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = =3D { 0x0af88, 0x0af8a, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_hlsq_stat= e_registers), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP= */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: SP_TOP */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] =3D { 0x0af80, 0x0af84, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_sp_top_re= gisters), 8)); =20 -/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP = */ +/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: uSPTP */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] =3D { 0x0af80, 0x0af84, 0x0af90, 0x0af92, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_reg= isters), 8)); =20 -/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */ +/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_NONE */ static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] =3D { 0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 0x0b60f, 0x0b621, 0x0b630, 0x0b633, @@ -676,14 +676,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_none_r= egisters[] =3D { }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registe= rs), 8)); =20 -/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ +/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_BR */ static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] =3D { 0x0b600, 0x0b600, UINT_MAX, UINT_MAX, }; static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers= ), 8)); =20 -/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */ +/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_LPAC */ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] =3D { 0x0b780, 0x0b780, UINT_MAX, UINT_MAX, @@ -703,172 +703,172 @@ static const struct gen7_sel_reg gen7_0_0_rb_rbp_se= l =3D { }; =20 static const struct gen7_cluster_registers gen7_0_0_clusters[] =3D { - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_0_0_noncontext_pipe_br_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT, gen7_0_0_noncontext_pipe_bv_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT, gen7_0_0_noncontext_pipe_lpac_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_0_0_noncontext_rb_rac_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_0_0_noncontext_rb_rbp_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_gras_cluster_gras_pipe_br_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_gras_cluster_gras_pipe_bv_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_gras_cluster_gras_pipe_br_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_gras_cluster_gras_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_pc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_pc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, }; =20 static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = =3D { - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE, gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_ST= ATE, gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP= _TOP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_US= PTP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STAT= E, gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP, gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_U= SPTP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h index 772652eb61f3..9bec75e830a3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h @@ -96,87 +96,87 @@ static const u32 gen7_2_0_debugbus_blocks[] =3D { }; =20 static const struct gen7_shader_block gen7_2_0_shader_blocks[] =3D { - {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_5_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_6_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_7_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_CB_RAM, 0x390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_13_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_14_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_TAG, 0xc0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_INST_DATA_2, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_TMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_SMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_STATE_DATA, 0x40, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_HWAVE_RAM, 0x100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_L0_INST_BUF, 0x50, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_8_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_9_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_10_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_11_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_SP_LB_12_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP= }, - {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, - {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE}, - {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE}, + {A7XX_TP0_TMO_DATA, 0x200, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_SMO_DATA, 0x80, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_1, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_0_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_1_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_2_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_3_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_4_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_5_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_6_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_7_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_CB_RAM, 0x390, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_13_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_14_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_TAG, 0xc0, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_2, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_TMO_TAG, 0x80, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_SMO_TAG, 0x80, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_STATE_DATA, 0x40, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_HWAVE_RAM, 0x100, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_L0_INST_BUF, 0x50, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_8_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_9_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_10_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_11_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_12_DATA, 0x800, 6, 2, PIPE_BR, A7XX_USPTP}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM, 0x200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, + {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE}, }; =20 static const u32 gen7_2_0_gpu_registers[] =3D { @@ -490,170 +490,170 @@ static const struct gen7_sel_reg gen7_2_0_rb_rbp_se= l =3D { }; =20 static const struct gen7_cluster_registers gen7_2_0_clusters[] =3D { - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_2_0_noncontext_pipe_br_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT, gen7_2_0_noncontext_pipe_bv_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT, gen7_0_0_noncontext_pipe_lpac_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_2_0_noncontext_rb_rac_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_2_0_noncontext_rb_rbp_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_2_0_gras_cluster_gras_pipe_br_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_2_0_gras_cluster_gras_pipe_bv_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_2_0_gras_cluster_gras_pipe_br_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_2_0_gras_cluster_gras_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_pc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_pc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, }; =20 static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = =3D { - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE, gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_NONE, 0, A7XX_USPTP, gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 }, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_ST= ATE, gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP, gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP= _TOP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_US= PTP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STAT= E, gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP, gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USP= TP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_U= SPTP, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, - { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USP= TP, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h index 0956dfca1f05..70805a5121be 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h @@ -118,97 +118,97 @@ static const u32 gen7_9_0_cx_debugbus_blocks[] =3D { }; =20 static const struct gen7_shader_block gen7_9_0_shader_blocks[] =3D { - { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_5_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_6_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_7_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_CB_RAM, 0x0390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_13_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_14_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_INST_TAG, 0x00C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_INST_DATA_2, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_TMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_SMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_STATE_DATA, 0x0040, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_8_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_9_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_10_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_11_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_SP_LB_12_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, - { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STA= TE }, - { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STA= TE }, - { A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BV, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE = }, - { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_ST= ATE }, - { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_ST= ATE }, - { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_ST= ATE }, - { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_ST= ATE }, - { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_= STATE }, - { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STAT= E }, - { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_ST= ATE }, - { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE= }, - { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE= }, - { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE= }, - { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STA= TE }, - { A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE }, - { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_= STATE }, - { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_= STATE }, - { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, A7XX_PIPE_LPAC, A7XX_HLS= Q_STATE }, - { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STA= TE }, - { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STA= TE }, - { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_S= TATE }, - { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ= _STATE }, - { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ= _STATE }, - { A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE = }, - { A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, - { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_INST_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_5_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_6_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_7_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_CB_RAM, 0x0390, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_13_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_14_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_INST_TAG, 0x00C0, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_INST_DATA_2, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_TMO_TAG, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_SMO_TAG, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_STATE_DATA, 0x0040, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_8_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_9_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_10_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_11_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_SP_LB_12_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP }, + { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BV, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BR, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BV, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, PIPE_BR, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE= }, + { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE= }, + { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE= }, + { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, PIPE_LPAC, A7XX_HLSQ_STA= TE }, + { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE = }, + { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STAT= E }, + { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, PIPE_BV, A7XX_HLSQ_STAT= E }, + { A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_BV, A7XX_HLSQ_STATE }, + { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_LPAC, A7XX_HLSQ_STATE }, }; =20 /* @@ -226,7 +226,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_pre_crashdumpe= r_gpu_registers), 8)); * Block : ['BROADCAST', 'CP', 'GRAS', 'GXCLKCTL'] * Block : ['PC', 'RBBM', 'RDVM', 'UCHE'] * Block : ['VFD', 'VPC', 'VSC'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 196 (Regs:1778) */ static const u32 gen7_9_0_gpu_registers[] =3D { @@ -290,7 +290,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_gxclkctl_regis= ters), 8)); =20 /* * Block : ['GMUAO', 'GMUCX', 'GMUCX_RAM'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 134 (Regs:429) */ static const u32 gen7_9_0_gmu_registers[] =3D { @@ -334,7 +334,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmu_registers)= , 8)); =20 /* * Block : ['GMUGX'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 44 (Regs:454) */ static const u32 gen7_9_0_gmugx_registers[] =3D { @@ -355,7 +355,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmugx_register= s), 8)); =20 /* * Block : ['CX_MISC'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 7 (Regs:56) */ static const u32 gen7_9_0_cx_misc_registers[] =3D { @@ -367,7 +367,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_misc_regist= ers), 8)); =20 /* * Block : ['DBGC'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 19 (Regs:155) */ static const u32 gen7_9_0_dbgc_registers[] =3D { @@ -382,7 +382,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_dbgc_registers= ), 8)); =20 /* * Block : ['CX_DBGC'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * pairs : 7 (Regs:75) */ static const u32 gen7_9_0_cx_dbgc_registers[] =3D { @@ -396,7 +396,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_dbgc_regist= ers), 8)); * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * pairs : 29 (Regs:573) */ @@ -417,7 +417,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pi= pe_br_registers), 8)); * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_NONE * pairs : 29 (Regs:573) */ @@ -438,7 +438,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pi= pe_bv_registers), 8)); * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_NONE * pairs : 2 (Regs:7) */ @@ -450,7 +450,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pi= pe_lpac_registers), 8)); =20 /* * Block : ['RB'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * pairs : 5 (Regs:37) */ @@ -463,7 +463,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb= _pipe_br_rac_registers), =20 /* * Block : ['RB'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * pairs : 15 (Regs:66) */ @@ -478,7 +478,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb= _pipe_br_rbp_registers), =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_HLSQ_STATE * pairs : 4 (Regs:28) @@ -491,7 +491,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_br_hlsq_state_regis =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_SP_TOP * pairs : 10 (Regs:61) @@ -506,7 +506,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_br_sp_top_registers =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_USPTP * pairs : 12 (Regs:62) @@ -521,7 +521,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_br_usptp_registers) =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_HLSQ_DP_STR * pairs : 2 (Regs:5) @@ -534,7 +534,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_br_hlsq_dp_str_regi =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_HLSQ_STATE * pairs : 1 (Regs:5) @@ -547,7 +547,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_lpac_hlsq_state_reg =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_SP_TOP * pairs : 1 (Regs:6) @@ -560,7 +560,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_lpac_sp_top_registe =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_USPTP * pairs : 2 (Regs:9) @@ -573,7 +573,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp= _pipe_lpac_usptp_register =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_NONE + * Pipeline: PIPE_NONE * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_USPTP * pairs : 5 (Regs:29) @@ -587,7 +587,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tp= l1_pipe_none_usptp_regist =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_USPTP * pairs : 1 (Regs:1) @@ -600,7 +600,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tp= l1_pipe_br_usptp_register =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_NONE * Location: A7XX_USPTP * pairs : 1 (Regs:1) @@ -613,7 +613,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tp= l1_pipe_lpac_usptp_regist =20 /* * Block : ['GRAS'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_GRAS * pairs : 14 (Regs:293) */ @@ -628,7 +628,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_br_c= luster_gras_registers), 8 =20 /* * Block : ['GRAS'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_GRAS * pairs : 14 (Regs:293) */ @@ -643,7 +643,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_bv_c= luster_gras_registers), 8 =20 /* * Block : ['PC'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_FE * pairs : 6 (Regs:31) */ @@ -656,7 +656,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_br_clu= ster_fe_registers), 8)); =20 /* * Block : ['PC'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_FE * pairs : 6 (Regs:31) */ @@ -669,7 +669,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_bv_clu= ster_fe_registers), 8)); =20 /* * Block : ['VFD'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_FE * pairs : 2 (Regs:236) */ @@ -681,7 +681,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_br_cl= uster_fe_registers), 8)); =20 /* * Block : ['VFD'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_FE * pairs : 2 (Regs:236) */ @@ -693,7 +693,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_bv_cl= uster_fe_registers), 8)); =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_FE * pairs : 2 (Regs:18) */ @@ -705,7 +705,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cl= uster_fe_registers), 8)); =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_PC_VS * pairs : 3 (Regs:30) */ @@ -717,7 +717,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cl= uster_pc_vs_registers), 8 =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_VPC_PS * pairs : 5 (Regs:76) */ @@ -730,7 +730,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cl= uster_vpc_ps_registers), =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_FE * pairs : 2 (Regs:18) */ @@ -742,7 +742,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cl= uster_fe_registers), 8)); =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_PC_VS * pairs : 3 (Regs:30) */ @@ -754,7 +754,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cl= uster_pc_vs_registers), 8 =20 /* * Block : ['VPC'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_VPC_PS * pairs : 5 (Regs:76) */ @@ -767,7 +767,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cl= uster_vpc_ps_registers), =20 /* * Block : ['RB'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_PS * pairs : 39 (Regs:133) */ @@ -788,7 +788,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_clu= ster_ps_rac_registers), 8 =20 /* * Block : ['RB'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_PS * pairs : 34 (Regs:100) */ @@ -808,7 +808,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_clu= ster_ps_rbp_registers), 8 =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_HLSQ_STATE * pairs : 29 (Regs:215) @@ -828,7 +828,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_vs_hlsq_state_reg =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_SP_TOP * pairs : 22 (Regs:73) @@ -846,7 +846,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_vs_sp_top_registe =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_USPTP * pairs : 16 (Regs:269) @@ -862,7 +862,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_vs_usptp_register =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_HLSQ_STATE * pairs : 21 (Regs:334) @@ -880,7 +880,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_ps_hlsq_state_reg =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_HLSQ_DP * pairs : 3 (Regs:19) @@ -893,7 +893,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_ps_hlsq_dp_regist =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_SP_TOP * pairs : 18 (Regs:77) @@ -910,7 +910,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_ps_sp_top_registe =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_USPTP * pairs : 17 (Regs:333) @@ -927,7 +927,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_ps_usptp_register =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_HLSQ_DP_STR * pairs : 1 (Regs:6) @@ -940,7 +940,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_clu= ster_sp_ps_hlsq_dp_str_re =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_HLSQ_STATE * pairs : 28 (Regs:213) @@ -959,7 +959,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_clu= ster_sp_vs_hlsq_state_reg =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_SP_TOP * pairs : 21 (Regs:71) @@ -977,7 +977,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_clu= ster_sp_vs_sp_top_registe =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_USPTP * pairs : 16 (Regs:266) @@ -993,7 +993,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_clu= ster_sp_vs_usptp_register =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_HLSQ_STATE * pairs : 14 (Regs:299) @@ -1009,7 +1009,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac= _cluster_sp_ps_hlsq_state_r =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_HLSQ_DP * pairs : 2 (Regs:13) @@ -1022,7 +1022,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac= _cluster_sp_ps_hlsq_dp_regi =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_SP_TOP * pairs : 9 (Regs:34) @@ -1037,7 +1037,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac= _cluster_sp_ps_sp_top_regis =20 /* * Block : ['SP'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_USPTP * pairs : 11 (Regs:279) @@ -1052,7 +1052,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac= _cluster_sp_ps_usptp_regist =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_USPTP * pairs : 3 (Regs:10) @@ -1065,7 +1065,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br= _cluster_sp_vs_usptp_regist =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_BR + * Pipeline: PIPE_BR * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_USPTP * pairs : 6 (Regs:42) @@ -1079,7 +1079,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br= _cluster_sp_ps_usptp_regist =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_BV + * Pipeline: PIPE_BV * Cluster : A7XX_CLUSTER_SP_VS * Location: A7XX_USPTP * pairs : 3 (Regs:10) @@ -1092,7 +1092,7 @@ static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_bv= _cluster_sp_vs_usptp_regist =20 /* * Block : ['TPL1'] - * Pipeline: A7XX_PIPE_LPAC + * Pipeline: PIPE_LPAC * Cluster : A7XX_CLUSTER_SP_PS * Location: A7XX_USPTP * pairs : 5 (Regs:7) @@ -1117,180 +1117,180 @@ static const struct gen7_sel_reg gen7_9_0_rb_rbp_= sel =3D { }; =20 static const struct gen7_cluster_registers gen7_9_0_clusters[] =3D { - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_9_0_non_context_pipe_br_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT, gen7_9_0_non_context_pipe_bv_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT, gen7_9_0_non_context_pipe_lpac_registers, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_9_0_non_context_rb_pipe_br_rac_registers, &gen7_9_0_rb_rac_sel, }, - { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, gen7_9_0_non_context_rb_pipe_br_rbp_registers, &gen7_9_0_rb_rbp_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, }, - { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_gras_pipe_br_cluster_gras_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_gras_pipe_br_cluster_gras_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_gras_pipe_bv_cluster_gras_registers, }, - { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_gras_pipe_bv_cluster_gras_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_pc_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_pc_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_pc_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_pc_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_vfd_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_vfd_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_vfd_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_vfd_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_br_cluster_fe_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_bv_cluster_fe_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, }, - { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0, gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, - { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + { A7XX_CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1, gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, }; =20 static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = =3D { - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_9_0_non_context_sp_pipe_br_sp_top_registers, 0xae00}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_non_context_sp_pipe_br_usptp_registers, 0xae00}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_DP_STR, gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers, 0xae00}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE, gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers, 0xaf80}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers, 0xaf80}, - { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_9_0_non_context_sp_pipe_lpac_usptp_registers, 0xaf80}, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_NONE, 0, A7XX_USPTP, gen7_9_0_non_context_tpl1_pipe_none_usptp_registers, 0xb600}, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_non_context_tpl1_pipe_br_usptp_registers, 0xb600}, - { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers, 0xb780}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_SP_TOP, gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_SP_TOP, gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ= _DP_STR, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP_S= TR, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_ST= ATE, gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HL= SQ_DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_DP, gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP= _TOP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_SP_TOP, gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_US= PTP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _STATE, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STAT= E, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ= _DP_STR, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP_S= TR, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ= _DP_STR, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP_S= TR, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ= _DP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_T= OP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP, gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ= _DP_STR, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP_S= TR, gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BV, 0, A7XX_USPTP, gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BV, 1, A7XX_USPTP, gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_US= PTP, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, - { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPT= P, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, }; =20 diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 9459b6038217..369b96d7f7c9 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -249,7 +249,7 @@ by a particular renderpass/blit. =20 - + @@ -3267,7 +3267,7 @@ by a particular renderpass/blit. - + diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml b/drivers/= gpu/drm/msm/registers/adreno/a7xx_enums.xml index 661b0dd0f675..8d195ee5d284 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_enums.xml @@ -93,13 +93,6 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> =20 - - - - - - - diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drive= rs/gpu/drm/msm/registers/adreno/adreno_common.xml index 218ec8bb966e..06020dc1df44 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -397,4 +397,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> =20 + + + + + + + + + + + --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 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adreno_func definitions for each sub-generations. To streamline the identification of the correct struct for a gpu, move it to the catalogue and move the gpu_init routine to struct adreno_gpu_funcs. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 7 +- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 50 +++---- drivers/gpu/drm/msm/adreno/a2xx_gpu.h | 2 + drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 13 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 52 ++++---- drivers/gpu/drm/msm/adreno/a3xx_gpu.h | 2 + drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 7 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 54 ++++---- drivers/gpu/drm/msm/adreno/a4xx_gpu.h | 2 + drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 17 +-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 61 ++++----- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 48 +++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 202 ++++++++++++++-----------= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 + drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +- 17 files changed, 275 insertions(+), 260 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a2xx_catalog.c index 5ddd015f930d..e9dbf3ddf89e 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c @@ -7,6 +7,7 @@ */ =20 #include "adreno_gpu.h" +#include "a2xx_gpu.h" =20 static const struct adreno_info a2xx_gpus[] =3D { { @@ -19,7 +20,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, }, { /* a200 on i.mx51 has only 128kib gmem */ .chip_ids =3D ADRENO_CHIP_IDS(0x02000001), .family =3D ADRENO_2XX_GEN1, @@ -30,7 +31,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x02020000), .family =3D ADRENO_2XX_GEN2, @@ -41,7 +42,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a2xx); diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index 963c0f669ee5..1b1ee14b65cf 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -486,39 +486,18 @@ static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct = msm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a2xx_hw_init, - .pm_suspend =3D msm_gpu_pm_suspend, - .pm_resume =3D msm_gpu_pm_resume, - .recover =3D a2xx_recover, - .submit =3D a2xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a2xx_irq, - .destroy =3D a2xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_state_get =3D a2xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D a2xx_create_vm, - .get_rptr =3D a2xx_get_rptr, - }, -}; - static const struct msm_gpu_perfcntr perfcntrs[] =3D { /* TODO */ }; =20 -struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) { struct a2xx_gpu *a2xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; int ret; =20 if (!pdev) { @@ -539,7 +518,7 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) gpu->perfcntrs =3D perfcntrs; gpu->num_perfcntrs =3D ARRAY_SIZE(perfcntrs); =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -558,3 +537,26 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a2xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a2xx_hw_init, + .pm_suspend =3D msm_gpu_pm_suspend, + .pm_resume =3D msm_gpu_pm_resume, + .recover =3D a2xx_recover, + .submit =3D a2xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a2xx_irq, + .destroy =3D a2xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_state_get =3D a2xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D a2xx_create_vm, + .get_rptr =3D a2xx_get_rptr, + }, + .init =3D a2xx_gpu_init, +}; diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.h index 53702f19990f..162ef98951f5 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.h @@ -19,6 +19,8 @@ struct a2xx_gpu { }; #define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base) =20 +extern const struct adreno_gpu_funcs a2xx_gpu_funcs; + struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu); void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, dma_addr_t *tran_error); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a3xx_catalog.c index 1498e6532f62..6ae8716fc08a 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c @@ -7,6 +7,7 @@ */ =20 #include "adreno_gpu.h" +#include "a3xx_gpu.h" =20 static const struct adreno_info a3xx_gpus[] =3D { { @@ -18,7 +19,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000520), .family =3D ADRENO_3XX, @@ -29,7 +30,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000600), .family =3D ADRENO_3XX, @@ -40,7 +41,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000620), .family =3D ADRENO_3XX, @@ -51,7 +52,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS( 0x03020000, @@ -66,7 +67,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS( 0x03030000, @@ -81,7 +82,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a3xx); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index a956cd79195e..f22d33e99e81 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -508,29 +508,6 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct m= sm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a3xx_hw_init, - .pm_suspend =3D msm_gpu_pm_suspend, - .pm_resume =3D msm_gpu_pm_resume, - .recover =3D a3xx_recover, - .submit =3D a3xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a3xx_irq, - .destroy =3D a3xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_busy =3D a3xx_gpu_busy, - .gpu_state_get =3D a3xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a3xx_get_rptr, - }, -}; - static const struct msm_gpu_perfcntr perfcntrs[] =3D { { REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO, SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" }, @@ -538,13 +515,14 @@ static const struct msm_gpu_perfcntr perfcntrs[] =3D { SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" }, }; =20 -struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) { struct a3xx_gpu *a3xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; struct icc_path *ocmem_icc_path; struct icc_path *icc_path; int ret; @@ -569,7 +547,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) =20 adreno_gpu->registers =3D a3xx_registers; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -613,3 +591,27 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a3xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a3xx_hw_init, + .pm_suspend =3D msm_gpu_pm_suspend, + .pm_resume =3D msm_gpu_pm_resume, + .recover =3D a3xx_recover, + .submit =3D a3xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a3xx_irq, + .destroy =3D a3xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_busy =3D a3xx_gpu_busy, + .gpu_state_get =3D a3xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a3xx_get_rptr, + }, + .init =3D a3xx_gpu_init, +}; diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.h index c555fb13e0d7..3d4ec9dbd918 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h @@ -23,4 +23,6 @@ struct a3xx_gpu { }; #define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base) =20 +extern const struct adreno_gpu_funcs a3xx_gpu_funcs; + #endif /* __A3XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a4xx_catalog.c index 09f9f228b75e..9192586f7ef0 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c @@ -7,6 +7,7 @@ */ =20 #include "adreno_gpu.h" +#include "a4xx_gpu.h" =20 static const struct adreno_info a4xx_gpus[] =3D { { @@ -19,7 +20,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x04020000), .family =3D ADRENO_4XX, @@ -30,7 +31,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D (SZ_1M + SZ_512K), .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x04030002), .family =3D ADRENO_4XX, @@ -41,7 +42,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D (SZ_1M + SZ_512K), .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a4xx); diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index 83f6329accba..db06c06067ae 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -627,37 +627,14 @@ static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct = msm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a4xx_hw_init, - .pm_suspend =3D a4xx_pm_suspend, - .pm_resume =3D a4xx_pm_resume, - .recover =3D a4xx_recover, - .submit =3D a4xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a4xx_irq, - .destroy =3D a4xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_busy =3D a4xx_gpu_busy, - .gpu_state_get =3D a4xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a4xx_get_rptr, - }, - .get_timestamp =3D a4xx_get_timestamp, -}; - -struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) { struct a4xx_gpu *a4xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; struct icc_path *ocmem_icc_path; struct icc_path *icc_path; int ret; @@ -680,7 +657,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) gpu->perfcntrs =3D NULL; gpu->num_perfcntrs =3D 0; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -726,3 +703,28 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a4xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a4xx_hw_init, + .pm_suspend =3D a4xx_pm_suspend, + .pm_resume =3D a4xx_pm_resume, + .recover =3D a4xx_recover, + .submit =3D a4xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a4xx_irq, + .destroy =3D a4xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_busy =3D a4xx_gpu_busy, + .gpu_state_get =3D a4xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a4xx_get_rptr, + }, + .init =3D a4xx_gpu_init, + .get_timestamp =3D a4xx_get_timestamp, +}; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.h index a01448cba2ea..71b164439f62 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h @@ -20,4 +20,6 @@ struct a4xx_gpu { }; #define to_a4xx_gpu(x) container_of(x, struct a4xx_gpu, base) =20 +extern const struct adreno_gpu_funcs a4xx_gpu_funcs; + #endif /* __A4XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a5xx_catalog.c index b48a636d8237..babd320f3b73 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -7,6 +7,7 @@ */ =20 #include "adreno_gpu.h" +#include "a5xx_gpu.h" =20 static const struct adreno_info a5xx_gpus[] =3D { { @@ -21,7 +22,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000600), .family =3D ADRENO_5XX, @@ -38,7 +39,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a506_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000800), @@ -55,7 +56,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a508_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000900), @@ -72,7 +73,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, /* Adreno 509 uses the same ZAP as 512 */ .zapfw =3D "a512_zap.mdt", }, { @@ -89,7 +90,7 @@ static const struct adreno_info a5xx_gpus[] =3D { * the GDSC which appears to make it grumpy */ .inactive_period =3D 250, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05010200), .family =3D ADRENO_5XX, @@ -105,7 +106,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a512_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS( @@ -127,7 +128,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_FAULT_DETECT_MASK, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a530_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05040001), @@ -145,7 +146,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a540_zap.mdt", } }; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 4a04dc43a8e6..56eaff2ee4e4 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1691,34 +1691,6 @@ static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, s= truct msm_ringbuffer *ring) return ring->memptrs->rptr =3D gpu_read(gpu, REG_A5XX_CP_RB_RPTR); } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a5xx_hw_init, - .ucode_load =3D a5xx_ucode_load, - .pm_suspend =3D a5xx_pm_suspend, - .pm_resume =3D a5xx_pm_resume, - .recover =3D a5xx_recover, - .submit =3D a5xx_submit, - .active_ring =3D a5xx_active_ring, - .irq =3D a5xx_irq, - .destroy =3D a5xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D a5xx_show, -#endif -#if defined(CONFIG_DEBUG_FS) - .debugfs_init =3D a5xx_debugfs_init, -#endif - .gpu_busy =3D a5xx_gpu_busy, - .gpu_state_get =3D a5xx_gpu_state_get, - .gpu_state_put =3D a5xx_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a5xx_get_rptr, - }, - .get_timestamp =3D a5xx_get_timestamp, -}; - static void check_speed_bin(struct device *dev) { struct nvmem_cell *cell; @@ -1751,7 +1723,7 @@ static void check_speed_bin(struct device *dev) devm_pm_opp_set_supported_hw(dev, &val, 1); } =20 -struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; @@ -1781,7 +1753,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) if (config->info->revn =3D=3D 510) nr_rings =3D 1; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_ri= ngs); if (ret) { a5xx_destroy(&(a5xx_gpu->base.base)); return ERR_PTR(ret); @@ -1806,3 +1778,32 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) =20 return gpu; } + +const struct adreno_gpu_funcs a5xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a5xx_hw_init, + .ucode_load =3D a5xx_ucode_load, + .pm_suspend =3D a5xx_pm_suspend, + .pm_resume =3D a5xx_pm_resume, + .recover =3D a5xx_recover, + .submit =3D a5xx_submit, + .active_ring =3D a5xx_active_ring, + .irq =3D a5xx_irq, + .destroy =3D a5xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D a5xx_show, +#endif +#if defined(CONFIG_DEBUG_FS) + .debugfs_init =3D a5xx_debugfs_init, +#endif + .gpu_busy =3D a5xx_gpu_busy, + .gpu_state_get =3D a5xx_gpu_state_get, + .gpu_state_put =3D a5xx_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a5xx_get_rptr, + }, + .init =3D a5xx_gpu_init, + .get_timestamp =3D a5xx_get_timestamp, +}; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.h index 9c0d701fe4b8..407bb950d350 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -133,6 +133,7 @@ struct a5xx_preempt_record { */ #define A5XX_PREEMPT_COUNTER_SIZE (16 * 4) =20 +extern const struct adreno_gpu_funcs a5xx_gpu_funcs; =20 int a5xx_power_init(struct msm_gpu *gpu); void a5xx_gpmu_ucode_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 5db01fa2ed44..70433965c303 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -683,7 +683,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D (SZ_128K + SZ_4K), .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gmuwrapper_funcs, .zapfw =3D "a610_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a612_hwcg, @@ -714,7 +714,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D (SZ_128K + SZ_4K), .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gmuwrapper_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a612_hwcg, .protect =3D &a630_protect, @@ -732,7 +732,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -763,7 +763,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -790,7 +790,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .protect =3D &a630_protect, .gmu_cgc_mode =3D 0x00000222, @@ -813,7 +813,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -838,7 +838,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -863,7 +863,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -889,7 +889,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a620_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a620_hwcg, @@ -912,7 +912,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a650_protect, @@ -949,7 +949,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a630_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a630_hwcg, @@ -969,7 +969,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a640_hwcg, @@ -993,7 +993,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a650_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a650_hwcg, @@ -1019,7 +1019,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a660_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, @@ -1038,7 +1038,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a660_protect, @@ -1061,7 +1061,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a660_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, @@ -1088,7 +1088,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a640_hwcg, @@ -1107,7 +1107,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a690_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, @@ -1442,7 +1442,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gmuwrapper_funcs, .zapfw =3D "a702_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a702_hwcg, @@ -1468,7 +1468,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "a730_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a730_hwcg, @@ -1489,7 +1489,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "a740_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, @@ -1523,7 +1523,7 @@ static const struct adreno_info a7xx_gpus[] =3D { ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, @@ -1564,7 +1564,7 @@ static const struct adreno_info a7xx_gpus[] =3D { ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .protect =3D &a730_protect, @@ -1597,7 +1597,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index c6b2fdb86c17..ba95b29855a3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2555,100 +2555,7 @@ static int a6xx_set_supported_hw(struct device *dev= , const struct adreno_info *i return 0; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_gmu_pm_suspend, - .pm_resume =3D a6xx_gmu_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a6xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, - .gpu_get_freq =3D a6xx_gmu_get_freq, - .gpu_set_freq =3D a6xx_gpu_set_freq, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - .sysprof_setup =3D a6xx_gmu_sysprof_setup, - }, - .get_timestamp =3D a6xx_gmu_get_timestamp, -}; - -static const struct adreno_gpu_funcs funcs_gmuwrapper =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_pm_suspend, - .pm_resume =3D a6xx_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a6xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - }, - .get_timestamp =3D a6xx_get_timestamp, -}; - -static const struct adreno_gpu_funcs funcs_a7xx =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_gmu_pm_suspend, - .pm_resume =3D a6xx_gmu_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a7xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, - .gpu_get_freq =3D a6xx_gmu_get_freq, - .gpu_set_freq =3D a6xx_gpu_set_freq, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - .sysprof_setup =3D a6xx_gmu_sysprof_setup, - }, - .get_timestamp =3D a6xx_gmu_get_timestamp, -}; - -struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; @@ -2659,7 +2566,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct msm_gpu *gpu; extern int enable_preemption; bool is_a7xx; - int ret; + int ret, nr_rings =3D 1; =20 a6xx_gpu =3D kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); if (!a6xx_gpu) @@ -2698,14 +2605,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); - else if (is_a7xx) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); - else if (adreno_has_gmu_wrapper(adreno_gpu) || - of_device_is_compatible(node, "qcom,adreno-rgmu")) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); - else - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + nr_rings =3D 4; + + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_ri= ngs); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2752,3 +2654,97 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 return gpu; } + +const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, + .gpu_get_freq =3D a6xx_gmu_get_freq, + .gpu_set_freq =3D a6xx_gpu_set_freq, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_gmu_get_timestamp, +}; + +const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_pm_suspend, + .pm_resume =3D a6xx_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_get_timestamp, +}; + +const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a7xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, + .gpu_get_freq =3D a6xx_gmu_get_freq, + .gpu_set_freq =3D a6xx_gpu_set_freq, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_gmu_get_timestamp, +}; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 0b17d36c36a9..ef66e1eb9152 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -216,6 +216,10 @@ struct a7xx_cp_smmu_info { #define A6XX_PROTECT_RDONLY(_reg, _len) \ ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) =20 +extern const struct adreno_gpu_funcs a6xx_gpu_funcs; +extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs; +extern const struct adreno_gpu_funcs a7xx_gpu_funcs; + static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) { if(adreno_is_a630(gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 28f744f3caf7..cb4113612b82 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -235,7 +235,7 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) priv->has_cached_coherent =3D !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); =20 - gpu =3D info->init(drm); + gpu =3D info->funcs->init(drm); if (IS_ERR(gpu)) { dev_warn(drm->dev, "failed to load adreno gpu\n"); return PTR_ERR(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 4acb03dcbc60..335acd5feb82 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -71,8 +71,11 @@ enum adreno_family { (((_c) >> 8) & 0xff), \ ((_c) & 0xff) =20 +struct adreno_gpu; + struct adreno_gpu_funcs { struct msm_gpu_funcs base; + struct msm_gpu *(*init)(struct drm_device *dev); int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); }; =20 @@ -101,7 +104,7 @@ struct adreno_info { const char *fw[ADRENO_FW_MAX]; uint32_t gmem; u64 quirks; - struct msm_gpu *(*init)(struct drm_device *dev); + const struct adreno_gpu_funcs *funcs; const char *zapfw; u32 inactive_period; union { @@ -685,12 +688,6 @@ OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, = uint16_t cnt) OUT_RING(ring, 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This will come handy when we implement A8x layer. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 52653ad376fc..b0be246b44ab 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1079,7 +1079,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) /* Halt the gmu cm3 core */ gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); =20 - a6xx_bus_clear_pending_transactions(adreno_gpu, true); + adreno_gpu->funcs->bus_halt(adreno_gpu, true); =20 /* Reset GPU core blocks */ a6xx_gpu_sw_reset(gpu, true); @@ -1251,7 +1251,7 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) if (ret) goto force_off; =20 - a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung); + adreno_gpu->funcs->bus_halt(adreno_gpu, a6xx_gpu->hung); =20 /* tell the GMU we want to slumber */ ret =3D a6xx_gmu_notify_slumber(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ba95b29855a3..575f2f9d3b1d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1595,7 +1595,7 @@ static void a6xx_recover(struct msm_gpu *gpu) =20 if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) { /* Drain the outstanding traffic on memory buses */ - a6xx_bus_clear_pending_transactions(adreno_gpu, true); + adreno_gpu->funcs->bus_halt(adreno_gpu, true); =20 /* Reset the GPU to a clean state */ a6xx_gpu_sw_reset(gpu, true); @@ -2316,7 +2316,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) mutex_lock(&a6xx_gpu->gmu.lock); =20 /* Drain the outstanding traffic on memory buses */ - a6xx_bus_clear_pending_transactions(adreno_gpu, true); + adreno_gpu->funcs->bus_halt(adreno_gpu, true); =20 if (adreno_is_a619_holi(adreno_gpu)) a6xx_sptprac_disable(gmu); @@ -2685,6 +2685,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_gmu_get_timestamp, + .bus_halt =3D a6xx_bus_clear_pending_transactions, }; =20 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs =3D { @@ -2715,6 +2716,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = =3D { }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_get_timestamp, + .bus_halt =3D a6xx_bus_clear_pending_transactions, }; =20 const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { @@ -2747,4 +2749,5 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { }, .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_gmu_get_timestamp, + .bus_halt =3D a6xx_bus_clear_pending_transactions, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 335acd5feb82..08bb601b3bd3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,6 +77,7 @@ struct adreno_gpu_funcs { struct msm_gpu_funcs base; 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This will help to use common code for mmu pagefault handler registration between a6x/a7x and a8x layer. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 575f2f9d3b1d..9edd23d419ec 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2641,7 +2641,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) adreno_gpu->uche_trap_base =3D 0x1fffffffff000ull; =20 msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, - a6xx_fault_handler); + adreno_gpu->funcs->mmu_fault_handler); =20 ret =3D a6xx_calc_ubwc_config(adreno_gpu); if (ret) { @@ -2686,6 +2686,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_gmu_get_timestamp, .bus_halt =3D a6xx_bus_clear_pending_transactions, + .mmu_fault_handler =3D a6xx_fault_handler, }; =20 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs =3D { @@ -2717,6 +2718,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = =3D { .init =3D a6xx_gpu_init, .get_timestamp =3D a6xx_get_timestamp, .bus_halt =3D a6xx_bus_clear_pending_transactions, + .mmu_fault_handler =3D a6xx_fault_handler, }; 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Co-developed-by: Rob Clark Signed-off-by: Rob Clark Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 8 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1950 +++++++++++++++-= ---- .../gpu/drm/msm/registers/adreno/a6xx_enums.xml | 2 +- .../drm/msm/registers/adreno/a8xx_descriptors.xml | 120 ++ .../gpu/drm/msm/registers/adreno/a8xx_enums.xml | 289 +++ .../gpu/drm/msm/registers/adreno/adreno_common.xml | 1 + 11 files changed, 1896 insertions(+), 513 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0c0dfb25f01b..7acf2cc13cd0 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -201,6 +201,7 @@ ADRENO_HEADERS =3D \ generated/a6xx_perfcntrs.xml.h \ generated/a7xx_enums.xml.h \ generated/a7xx_perfcntrs.xml.h \ + generated/a8xx_enums.xml.h \ generated/a6xx_gmu.xml.h \ generated/adreno_common.xml.h \ generated/adreno_pm4.xml.h \ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 9edd23d419ec..c4dde13e5661 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); =20 /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); =20 /* @@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); =20 /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); =20 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); @@ -1305,7 +1305,7 @@ static int hw_init(struct msm_gpu *gpu) } =20 if (adreno_is_a660_family(adreno_gpu)) - gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); + gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { @@ -1754,10 +1754,10 @@ static int a6xx_fault_handler(void *arg, unsigned l= ong iova, int flags, void *da const char *block =3D "unknown"; =20 u32 scratch[] =3D { - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)), }; =20 if (info) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.h index 4c5fe627d368..688b8ce02fdc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -71,8 +71,8 @@ static const struct a6xx_cluster { u32 sel_val; } a6xx_clusters[] =3D { CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNT= L_CD, 0x0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNT= L_CD, 0x9), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_C= D, 0x0), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_C= D, 0x9), CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), @@ -303,8 +303,8 @@ static const u32 a660_registers[] =3D { static const struct a6xx_registers a6xx_reglist[] =3D { REGS(a6xx_registers, 0, 0), REGS(a660_registers, 0, 0), - REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), - REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), + REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0), + REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9), }; =20 static const u32 a6xx_ahb_registers[] =3D { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h index 087473679893..d513e03fef08 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h @@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_r= egisters[] =3D { static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registe= rs), 8)); =20 static const struct gen7_sel_reg gen7_0_0_rb_rac_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0x0, }; =20 static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0x9, }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h index 9bec75e830a3..7897622ea6f7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h @@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hls= q_state_registers[] =3D { static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_stat= e_registers), 8)); =20 static const struct gen7_sel_reg gen7_2_0_rb_rac_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0x0, }; =20 static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0x9, }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/driver= s/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h index 70805a5121be..20125d1aa21d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h @@ -1105,14 +1105,14 @@ static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp= _ps_usptp_registers[] =3D { static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_uspt= p_registers), 8)); =20 static const struct gen7_sel_reg gen7_9_0_rb_rac_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0, }; =20 static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel =3D { - .host_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg =3D REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg =3D REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val =3D 0x9, }; =20 diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 369b96d7f7c9..484b8f048534 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -7,9 +7,11 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/freed= reno/ rules-fd.xsd"> + + =20 - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + @@ -115,11 +217,16 @@ by a particular renderpass/blit. - + + + + + - + + - + b0..7 identifies where MRB data starts (and RB data ends) b8.15 identifies where VSD data starts (and MRB data ends) @@ -131,7 +238,7 @@ by a particular renderpass/blit. - + low bits identify where CP_SET_DRAW_STATE stateobj processing starts (and IB2 data ends). I'm guessing @@ -147,176 +254,275 @@ by a particular renderpass/blit. - - - - - + + + + + + + + - + + + =20 - + + + + + + + + + + - + + + + + + + =20 - + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + + + + + + + + + + + + + + + + + + + + =20 - - - - - - - - - - - - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of dwords that have already been read but haven't been consu= med by $addr - - - + + + + + + + + + + + + + + + + + + + + + + number of remaining dwords incl current dword being consumed? - + + + + + + + + + + + + + + + + =20 - - + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -342,22 +548,59 @@ by a particular renderpass/blit. - - - + + + - =20 - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + =20 - - + + + + + + + + + + + + + =20 @@ -376,49 +619,96 @@ by a particular renderpass/blit. =20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + =20 =20 - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + =20 - + - - - - - + + + + + + + + =20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + =20 @@ -610,6 +941,8 @@ by a particular renderpass/blit. + + @@ -638,72 +971,277 @@ by a particular renderpass/blit. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - Set to true when binning, isn't changed afterwards - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - + + + + + + + + + + - + - - - + + + + + + + + + + + + + =20 - - + + + + - - - - - - + + + + + + - - + + - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + @@ -712,26 +1250,55 @@ by a particular renderpass/blit. + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + =20 + @@ -803,10 +1370,14 @@ by a particular renderpass/blit. =20 =20 - - + + + + - + + + =20 @@ -829,6 +1400,7 @@ by a particular renderpass/blit. =20 + =20 @@ -839,6 +1411,18 @@ by a particular renderpass/blit. =20 + + + + + + + + + + + + @@ -853,6 +1437,7 @@ by a particular renderpass/blit. =20 + =20 @@ -860,9 +1445,7 @@ by a particular renderpass/blit. =20 - - - + =20 @@ -887,6 +1470,7 @@ by a particular renderpass/blit. =20 + =20 @@ -921,10 +1505,23 @@ by a particular renderpass/blit. =20 + + + + + + + + + + + + + =20 @@ -951,6 +1548,13 @@ by a particular renderpass/blit. + + + + + + + =20 @@ -958,25 +1562,31 @@ by a particular renderpass/blit. =20 + + + =20 =20 + =20 =20 + =20 =20 + =20 @@ -984,9 +1594,17 @@ by a particular renderpass/blit. =20 + + + + + + + + @@ -994,6 +1612,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1008,6 +1627,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1022,10 +1642,16 @@ by a particular renderpass/blit. =20 + + + + =20 + + @@ -1085,6 +1711,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1123,6 +1750,23 @@ by a particular renderpass/blit. =20 =20 + + + + + Disable LRZ feedback writes + + + Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have + GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. + In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. + + + + + + + @@ -1130,6 +1774,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1137,6 +1782,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1158,13 +1804,21 @@ by a particular renderpass/blit. =20 + + + + + + + =20 =20 + =20 @@ -1176,14 +1830,26 @@ by a particular renderpass/blit. =20 + + + + + + + + + =20 =20 + + + @@ -1203,6 +1869,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1210,6 +1877,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1217,8 +1885,10 @@ by a particular renderpass/blit. =20 + =20 + =20 @@ -1226,6 +1896,7 @@ by a particular renderpass/blit. =20 + =20 @@ -1263,6 +1934,12 @@ by a particular renderpass/blit. =20 + + + + + + =20 @@ -1275,14 +1952,17 @@ by a particular renderpass/blit. =20 + =20 =20 + =20 + =20 @@ -1290,6 +1970,9 @@ by a particular renderpass/blit. =20 + + + =20 =20 + + + =20 + =20 @@ -1357,11 +2044,11 @@ by a particular renderpass/blit. =20 + =20 LUT used to convert quality buffer values to HW shading rate values.= An array of 4-bit values. - - - + + =20 @@ -1408,16 +2095,35 @@ by a particular renderpass/blit. =20 + + + + + + + + + + - + - - - - - + + + + + + + + + + + + + + =20 + =20 @@ -1534,8 +2241,32 @@ by a particular renderpass/blit. - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1627,6 +2358,8 @@ by a particular renderpass/blit. + + =20 @@ -1708,6 +2441,14 @@ by a particular renderpass/blit. =20 + + + + + + + + @@ -1720,6 +2461,14 @@ by a particular renderpass/blit. + + + + + + + + @@ -1799,7 +2548,7 @@ by a particular renderpass/blit. - + @@ -1814,7 +2563,17 @@ by a particular renderpass/blit. --> - + + + + + + + + + + + @@ -1849,9 +2608,19 @@ by a particular renderpass/blit. the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. - =20 - + + + + + + + + + + + + =20 =20 - + - + =20 @@ -1963,7 +2732,7 @@ by a particular renderpass/blit. - + @@ -1972,26 +2741,40 @@ by a particular renderpass/blit. - + + + + + - + + + + + + + - - - - + + + + + + + - - + + + =20 @@ -2014,6 +2797,10 @@ by a particular renderpass/blit. =20 + + + + @@ -2028,6 +2815,9 @@ by a particular renderpass/blit. =20 + + + =20 @@ -2042,6 +2832,7 @@ by a particular renderpass/blit. =20 + =20 @@ -2051,6 +2842,7 @@ by a particular renderpass/blit. =20 + @@ -2091,9 +2883,13 @@ by a particular renderpass/blit. =20 + + + + =20 @@ -2119,6 +2915,15 @@ by a particular renderpass/blit. =20 + + Packed array of a6xx_varying_interp_mode + + + + Packed array of a6xx_varying_ps_repl_mode + + + @@ -2128,6 +2933,11 @@ by a particular renderpass/blit. =20 + + + + + + =20 + =20 @@ -2181,13 +2994,23 @@ by a particular renderpass/blit. =20 + + + + + + + + =20 + =20 + =20 @@ -2211,6 +3034,10 @@ by a particular renderpass/blit. =20 + + + + @@ -2231,6 +3058,7 @@ by a particular renderpass/blit. =20 + =20 =20 - - - - + + + + + + + + + + - - - - + + + + + + + + + =20 + =20 @@ -2285,6 +3142,7 @@ by a particular renderpass/blit. =20 + =20 @@ -2292,10 +3150,13 @@ by a particular renderpass/blit. =20 + =20 + =20 + =20 =20 @@ -2304,6 +3165,7 @@ by a particular renderpass/blit. =20 + =20 @@ -2311,12 +3173,19 @@ by a particular renderpass/blit. =20 + =20 =20 + + + + + + =20 @@ -2326,6 +3195,9 @@ by a particular renderpass/blit. =20 + + + @@ -2333,6 +3205,7 @@ by a particular renderpass/blit. =20 + =20 + + =20 =20 + =20 @@ -2381,7 +3258,13 @@ by a particular renderpass/blit. =20 + + + + + + =20 @@ -2391,24 +3274,37 @@ by a particular renderpass/blit. =20 + + - - - - + + + + + + + + + + =20 + + + + + =20 @@ -2419,6 +3315,10 @@ by a particular renderpass/blit. =20 + + + + - + + + =20 @@ -2532,9 +3442,13 @@ by a particular renderpass/blit. =20 =20 - + + + + + =20 =20 - - - @@ -3036,6 +3951,7 @@ by a particular renderpass/blit. must be at least the actual CONSTLEN. + @@ -3158,6 +4074,18 @@ by a particular renderpass/blit. =20 + + + + + + + + + + + + =20 + =20 =20 + + @@ -3235,7 +4168,8 @@ by a particular renderpass/blit. =20 - + + @@ -3244,10 +4178,14 @@ by a particular renderpass/blit. =20 - + + + + + =20 - - + + =20 =20 + + + @@ -3307,6 +4271,8 @@ by a particular renderpass/blit. =20 + + @@ -3387,10 +4353,11 @@ by a particular renderpass/blit. + =20 - + =20 @@ -3458,10 +4430,8 @@ by a particular renderpass/blit. =20 - - - - + + =20 @@ -3745,6 +4715,7 @@ by a particular renderpass/blit. =20 + =20 @@ -3784,12 +4755,12 @@ by a particular renderpass/blit. - + =20 - + =20 =20 @@ -3918,6 +4889,7 @@ by a particular renderpass/blit. + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/= gpu/drm/msm/registers/adreno/a6xx_enums.xml index 4e42f055b85f..81538831dc19 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -303,7 +303,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 + + + + + + + + + + + + = + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml b/drivers/= gpu/drm/msm/registers/adreno/a8xx_enums.xml new file mode 100644 index 000000000000..aee8871d006f --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml @@ -0,0 +1,289 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drive= rs/gpu/drm/msm/registers/adreno/adreno_common.xml index 06020dc1df44..79d204f1e400 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -11,6 +11,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + =20 --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0b-0031df01.pphosted.com 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cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 00:52:34 -0800 (PST) From: Akhil P Oommen Date: Tue, 18 Nov 2025 14:20:37 +0530 Subject: [PATCH v4 10/22] drm/msm/a6xx: Rebase GMU register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> References: <20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com> In-Reply-To: <20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763455868; l=31486; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=LhwFqdN2Z7n0b/3haqROFi97DWeW1e45MN33dqohVcc=; b=7e9crv4DLPT0wO9wMvi4dYMu7aLs9kr9TMfInbJ3ERgGtSIBWG/rnkDjZ7dOt2hHFXZpHjZK6 A9Q+4mcgrfuCsd+ltpwdQOgNJKnC+qa/AvXtOBidO2Pz5OYJFulzy7J X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-GUID: gjEtZNXwhpOI90AFFOyOmkIcKXp9XzqE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA2OSBTYWx0ZWRfX0jA5JTYC9dQh u66y0PIH7FcEA2vq64dASzEt7MgJaEDfkbB8rISxpwcEH5TrZjWPu04AJ3xlAvmKNLPhZ5I9rI+ wZny11eSIo6X7Dou8muuYRvIaCfEtusaWBHh26PXKq5WAMjMkVcNxlIAxfTmovSdo8o9m/7hwDy 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adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180069 GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 100 +++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 56 ++--- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 +++++++++++-------= ---- 4 files changed, 221 insertions(+), 203 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index b0be246b44ab..a5aceb906827 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -610,22 +610,19 @@ static inline void pdc_write(void __iomem *ptr, u32 o= ffset, u32 value) writel(value, ptr + (offset << 2)); } =20 -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name); - static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct platform_device *pdev =3D to_platform_device(gmu->dev); - void __iomem *pdcptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc"); + void __iomem *pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu= _pdc"); u32 seqmem0_drv0_reg =3D REG_A6XX_RSCC_SEQ_MEM_0_DRV0; void __iomem *seqptr =3D NULL; uint32_t pdc_address_offset; bool pdc_in_aop =3D false; =20 if (IS_ERR(pdcptr)) - goto err; + return; =20 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) @@ -638,9 +635,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_address_offset =3D 0x30080; =20 if (!pdc_in_aop) { - seqptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); + seqptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq"); if (IS_ERR(seqptr)) - goto err; + return; } =20 /* Disable SDE clock gating */ @@ -730,12 +727,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) =20 /* ensure no writes happen before the uCode is fully written */ wmb(); - -err: - if (!IS_ERR_OR_NULL(pdcptr)) - iounmap(pdcptr); - if (!IS_ERR_OR_NULL(seqptr)) - iounmap(seqptr); } =20 /* @@ -1821,27 +1812,6 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gm= u) return 0; } =20 -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name) -{ - void __iomem *ret; - struct resource *res =3D platform_get_resource_byname(pdev, - IORESOURCE_MEM, name); - - if (!res) { - DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); - return ERR_PTR(-EINVAL); - } - - ret =3D ioremap(res->start, resource_size(res)); - if (!ret) { - DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); - return ERR_PTR(-EINVAL); - } - - return ret; -} - static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *= pdev, const char *name, irq_handler_t handler) { @@ -1892,7 +1862,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct platform_device *pdev =3D to_platform_device(gmu->dev); =20 mutex_lock(&gmu->lock); if (!gmu->initialized) { @@ -1921,8 +1890,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) qmp_put(gmu->qmp); =20 iounmap(gmu->mmio); - if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) - iounmap(gmu->rscc); gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 @@ -1949,10 +1916,38 @@ static int cxpd_notifier_cb(struct notifier_block *= nb, return 0; } =20 +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, + const char *name, resource_size_t *start) +{ + void __iomem *ret; + struct resource *res =3D platform_get_resource_byname(pdev, + IORESOURCE_MEM, name); + + if (!res) { + DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); + return ERR_PTR(-EINVAL); + } + + ret =3D ioremap(res->start, resource_size(res)); + if (!ret) { + DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); + return ERR_PTR(-EINVAL); + } + + if (start) + *start =3D res->start; + + return ret; +} + int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) { struct platform_device *pdev =3D of_find_device_by_node(node); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -1977,12 +1972,21 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) gmu->nr_clocks =3D ret; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_mmio; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); if (IS_ERR(gmu->cxpd)) { ret =3D PTR_ERR(gmu->cxpd); @@ -2024,10 +2028,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { + struct platform_device *pdev =3D of_find_device_by_node(node); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct platform_device *pdev =3D of_find_device_by_node(node); struct device_link *link; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -2122,15 +2129,24 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) goto err_memory; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_memory; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { - gmu->rscc =3D a6xx_gmu_get_mmio(pdev, "rscc"); + gmu->rscc =3D devm_platform_ioremap_resource_byname(pdev, "rscc"); if (IS_ERR(gmu->rscc)) { ret =3D -ENODEV; goto err_mmio; @@ -2208,8 +2224,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) =20 err_mmio: iounmap(gmu->mmio); - if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) - iounmap(gmu->rscc); free_irq(gmu->gmu_irq, gmu); free_irq(gmu->hfi_irq, gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 06cfc294016f..55b1c78daa8b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -68,6 +68,7 @@ struct a6xx_gmu { struct drm_gpuvm *vm; =20 void __iomem *mmio; + u32 mmio_offset; void __iomem *rscc; =20 int hfi_irq; @@ -130,20 +131,23 @@ struct a6xx_gmu { unsigned long status; }; =20 +#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset) + static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) { - return readl(gmu->mmio + (offset << 2)); + /* The 'offset' is based on GPU's start address. Adjust it */ + return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) { - writel(value, gmu->mmio + (offset << 2)); + writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) { - memcpy_toio(gmu->mmio + (offset << 2), data, size); + memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size); wmb(); } =20 @@ -160,17 +164,17 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u3= 2 lo, u32 hi) { u64 val; =20 - val =3D (u64) readl(gmu->mmio + (lo << 2)); - val |=3D ((u64) readl(gmu->mmio + (hi << 2)) << 32); + val =3D gmu_read(gmu, lo); + val |=3D ((u64) gmu_read(gmu, hi) << 32); =20 return val; } =20 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ - interval, timeout) + readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \ + cond, interval, timeout) #define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \ + readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val= , cond, \ interval, timeout) =20 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.h index 688b8ce02fdc..b49d8427b59e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -343,48 +343,48 @@ static const struct a6xx_registers a6xx_gbif_reglist = =3D =20 static const u32 a6xx_gmu_gx_registers[] =3D { /* GMU GX */ - 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b, - 0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b, - 0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b, - 0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084, - 0x0100, 0x012b, 0x0140, 0x0140, + 0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b, + 0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b, + 0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b, + 0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884, + 0x1a900, 0x1a92b, 0x1a940, 0x1a940, }; =20 static const u32 a6xx_gmu_cx_registers[] =3D { /* GMU CX */ - 0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a, - 0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c, - 0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089, - 0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0, - 0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140, - 0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154, - 0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165, - 0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc, - 0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201, + 0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a, + 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c, + 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889, + 0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0, + 0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940, + 0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954, + 0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965, + 0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc, + 0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01, /* GMU AO */ - 0x9300, 0x9316, 0x9400, 0x9400, + 0x23b00, 0x23b16, 0x23c00, 0x23c00, }; =20 static const u32 a6xx_gmu_gpucc_registers[] =3D { /* GPU CC */ - 0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b, - 0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40, - 0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002, - 0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402, - 0xb800, 0xb802, + 0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b, + 0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440, + 0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802, + 0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02, + 0x26000, 0x26002, /* GPU CC ACD */ - 0xbc00, 0xbc16, 0xbc20, 0xbc27, + 0x26400, 0x26416, 0x26420, 0x26427, }; =20 static const u32 a621_gmu_gpucc_registers[] =3D { /* GPU CC */ - 0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404, - 0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30, - 0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a, - 0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5, - 0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc, - 0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16, - 0xbe20, 0xbe2d, + 0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04, + 0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, + 0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a, + 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5, + 0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, + 0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616, + 0x26620, 0x2662d, }; =20 static const u32 a6xx_gmu_cx_rscc_registers[] =3D { diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index b15a242d974d..09b8a0b9c0de 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -40,56 +40,56 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + @@ -99,15 +99,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + - + - + @@ -119,71 +119,71 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -191,27 +191,27 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + =20 --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F01263112B6 for ; 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Unfortunately, there are minor shuffling in the register offsets in the GMU CX register region. So, update the driver to use the correct register offsets on A8x hw. Some A8x GPUs have more than 16 powerlevels on GX domain and 4 on CX domain. To accommodate this, increase the arrays' sizes which hold gx and cx power levels. Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 77 +++++++++++++++++--= ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 4 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++ drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 48 ++++++++++---- 4 files changed, 102 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index a5aceb906827..e566f3b7eab4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -224,14 +224,19 @@ unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) =20 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) { - u32 val; + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int local =3D gmu->idle_level; + u32 val; =20 /* SPTP and IFPC both report as IFPC */ if (gmu->idle_level =3D=3D GMU_IDLE_STATE_SPTP) local =3D GMU_IDLE_STATE_IFPC; =20 - val =3D gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); + if (adreno_is_a8xx(adreno_gpu)) + val =3D gmu_read(gmu, REG_A8XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); + else + val =3D gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); =20 if (val =3D=3D local) { if (gmu->idle_level !=3D GMU_IDLE_STATE_IFPC || @@ -269,7 +274,9 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) /* Set the log wptr index * note: downstream saves the value in poweroff and restores it here */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GMU_GENERAL_9, 0); + else if (adreno_is_a7xx(adreno_gpu)) gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); else gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); @@ -511,7 +518,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) * in the power down sequence not being fully executed. That in turn can * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. */ - if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); + else if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))) gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); } @@ -519,10 +528,15 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *g= mu) /* Let the GMU know that we are about to go into slumber */ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; int ret; =20 /* Disable the power counter so the GMU isn't busy */ - gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); + else + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); =20 /* Disable SPTP_PC if the CPU is responsible for it */ if (gmu->idle_level < GMU_IDLE_STATE_SPTP) @@ -615,12 +629,17 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct platform_device *pdev =3D to_platform_device(gmu->dev); - void __iomem *pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu= _pdc"); u32 seqmem0_drv0_reg =3D REG_A6XX_RSCC_SEQ_MEM_0_DRV0; void __iomem *seqptr =3D NULL; uint32_t pdc_address_offset; + void __iomem *pdcptr; bool pdc_in_aop =3D false; =20 + /* On A8x and above, RPMH/PDC configurations are entirely configured in A= OP */ + if (adreno_is_a8xx(adreno_gpu)) + return; + + pdcptr =3D devm_platform_ioremap_resource_byname(pdev, "gmu_pdc"); if (IS_ERR(pdcptr)) return; =20 @@ -749,7 +768,7 @@ static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); =20 /* A7xx knows better by default! */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) return; =20 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); @@ -812,7 +831,9 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) u32 itcm_base =3D 0x00000000; u32 dtcm_base =3D 0x00040000; =20 - if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a650_family(adreno_gpu) || + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) dtcm_base =3D 0x10004000; =20 if (gmu->legacy) { @@ -876,12 +897,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, un= signed int state) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } else if (adreno_is_a8xx(adreno_gpu)) { + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); + gmu_write(gmu, REG_A8XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); } =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); - else + else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 ret =3D a6xx_rpmh_start(gmu); @@ -906,7 +930,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); =20 - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a8xx(adreno_gpu)) { + fence_range_upper =3D 0x32; + fence_range_lower =3D 0x8c0; + } else if (adreno_is_a7xx(adreno_gpu)) { fence_range_upper =3D 0x32; fence_range_lower =3D 0x8a0; } else { @@ -940,7 +967,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) chipid |=3D (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ } =20 - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a8xx(adreno_gpu)) { + gmu_write(gmu, REG_A8XX_GMU_GENERAL_10, chipid); + gmu_write(gmu, REG_A8XX_GMU_GENERAL_8, + (gmu->log.iova & GENMASK(31, 12)) | + ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); + } else if (adreno_is_a7xx(adreno_gpu)) { gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, (gmu->log.iova & GENMASK(31, 12)) | @@ -1003,7 +1035,7 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) u32 val, seqmem_off =3D 0; =20 /* The second spin of A7xx GPUs messed with some register offsets.. */ - if (adreno_is_a740_family(adreno_gpu)) + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) seqmem_off =3D 4; =20 /* Make sure there are no outstanding RPMh votes */ @@ -1016,7 +1048,7 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, val, (val & 1), 100, 1000); =20 - if (!adreno_is_a740_family(adreno_gpu)) + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) return; =20 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, @@ -1044,7 +1076,10 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) * Turn off keep alive that might have been enabled by the hang * interrupt */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + if (adreno_is_a8xx(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + else + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); =20 /* Flush all the queues */ a6xx_hfi_stop(gmu); @@ -1148,7 +1183,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) enable_irq(gmu->gmu_irq); =20 /* Check to see if we are doing a cold or warm boot */ - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { @@ -1477,7 +1512,7 @@ static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_= gpu *adreno_gpu, vote =3D clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); =20 /* GMUs on A7xx votes on both x & y */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) data[bcm_index] =3D BCM_TCS_CMD(commit, true, vote, vote); else data[bcm_index] =3D BCM_TCS_CMD(commit, true, 0, vote); @@ -2070,13 +2105,14 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) */ gmu->dummy.size =3D SZ_4K; if (adreno_is_a660_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) { ret =3D a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000, "debug"); if (ret) goto err_memory; =20 - gmu->dummy.size =3D SZ_8K; + gmu->dummy.size =3D SZ_16K; } =20 /* Allocate memory for the GMU dummy page */ @@ -2087,7 +2123,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) =20 /* Note that a650 family also includes a660 family: */ if (adreno_is_a650_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + adreno_is_a7xx(adreno_gpu) || + adreno_is_a8xx(adreno_gpu)) { ret =3D a6xx_gmu_memory_alloc(gmu, &gmu->icache, SZ_16M - SZ_16K, 0x04000, "icache"); if (ret) @@ -2151,6 +2188,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) ret =3D -ENODEV; goto err_mmio; } + } else if (adreno_is_a8xx(adreno_gpu)) { + gmu->rscc =3D gmu->mmio + 0x19000; } else { gmu->rscc =3D gmu->mmio + 0x23000; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 55b1c78daa8b..edf6c282cd76 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -19,8 +19,8 @@ struct a6xx_gmu_bo { u64 iova; }; =20 -#define GMU_MAX_GX_FREQS 16 -#define GMU_MAX_CX_FREQS 4 +#define GMU_MAX_GX_FREQS 32 +#define GMU_MAX_CX_FREQS 6 #define GMU_MAX_BCMS 3 =20 struct a6xx_bcm { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 922d2dee70fb..dfc1bf499b08 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -50,6 +50,8 @@ enum adreno_family { ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ ADRENO_7XX_GEN3, /* a750 family */ + ADRENO_8XX_GEN1, /* a830 family */ + ADRENO_8XX_GEN2, /* a840 family */ }; =20 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -565,6 +567,11 @@ static inline int adreno_is_a7xx(struct adreno_gpu *gp= u) adreno_is_a740_family(gpu); } =20 +static inline int adreno_is_a8xx(struct adreno_gpu *gpu) +{ + return gpu->info->family >=3D ADRENO_8XX_GEN1; +} + /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ #define ADRENO_VM_START 0x100000000ULL u64 adreno_private_vm_size(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index 09b8a0b9c0de..5dce7934056d 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -66,10 +66,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> + + + + + @@ -89,7 +94,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> - + @@ -99,7 +104,11 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + + + + + @@ -120,9 +129,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> - - - + + + + + + @@ -130,8 +142,10 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> - - + + + + @@ -164,6 +178,14 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> + + + + + + + + @@ -233,12 +255,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - - + + + + + + =20 --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73CFF3043B9 for ; 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This is not true for recent targets. So, rework the rpmh init sequence to probe and calculate the votes with the respective rails, ie, GX rails should use MxG as secondary rail and Cx rail should use MxA as the secondary rail. Fixes: d6225e0cd096 ("drm/msm/adreno: Add support for X185 GPU") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index e566f3b7eab4..b76960c6d444 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1544,13 +1544,14 @@ static unsigned int a6xx_gmu_get_arc_level(struct d= evice *dev, } =20 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, - unsigned long *freqs, int freqs_count, const char *id) + unsigned long *freqs, int freqs_count, + const char *pri_id, const char *sec_id) { int i, j; const u16 *pri, *sec; size_t pri_count, sec_count; =20 - pri =3D cmd_db_read_aux_data(id, &pri_count); + pri =3D cmd_db_read_aux_data(pri_id, &pri_count); if (IS_ERR(pri)) return PTR_ERR(pri); /* @@ -1561,13 +1562,7 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct devic= e *dev, u32 *votes, if (!pri_count) return -EINVAL; =20 - /* - * Some targets have a separate gfx mxc rail. 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Create this new vote table and implement the new HFI message which allows passing vote tables to send this data to GMU. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 54 +++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 53 +++++++++++++++++++++++++++++++= +++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 17 +++++++++++ 4 files changed, 125 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index b76960c6d444..cede210a0a78 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1616,6 +1616,57 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct devic= e *dev, u32 *votes, return 0; } =20 +static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, + unsigned long *freqs, int freqs_count) +{ + const u16 *mx; + size_t count; + + mx =3D cmd_db_read_aux_data("mx.lvl", &count); + if (IS_ERR(mx)) + return PTR_ERR(mx); + /* + * The data comes back as an array of unsigned shorts so adjust the + * count accordingly + */ + count >>=3D 1; + if (!count) + return -EINVAL; + + /* Fix the vote for zero frequency */ + votes[0] =3D 0xffffffff; + + /* Construct a vote for rest of the corners */ + for (int i =3D 1; i < freqs_count; i++) { + unsigned int level =3D a6xx_gmu_get_arc_level(dev, freqs[i]); + u8 j, index =3D 0; + + /* Get the primary index that matches the arc level */ + for (j =3D 0; j < count; j++) { + if (mx[j] >=3D level) { + index =3D j; + break; + } + } + + if (j =3D=3D count) { + DRM_DEV_ERROR(dev, + "Mx Level %u not found in the RPMh list\n", + level); + DRM_DEV_ERROR(dev, "Available levels:\n"); + for (j =3D 0; j < count; j++) + DRM_DEV_ERROR(dev, " %u\n", mx[j]); + + return -EINVAL; + } + + /* Construct the vote */ + votes[i] =3D (0x3fff << 14) | (index << 8) | (0xff); + } + + return 0; +} + /* * The GMU votes with the RPMh for itself and on behalf of the GPU but we = need * to construct the list of votes on the CPU and send it over. Query the R= PMh @@ -1649,6 +1700,9 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *= gmu) ret |=3D a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl"); =20 + ret |=3D a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes, + gmu->gpu_freqs, gmu->nr_gpu_freqs); + /* Build the interconnect votes */ if (info->bcms && gmu->nr_gpu_bws > 1) ret |=3D a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index edf6c282cd76..2af074c8e8cf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -97,6 +97,7 @@ struct a6xx_gmu { int nr_gpu_freqs; unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; u32 gx_arc_votes[GMU_MAX_GX_FREQS]; + u32 dep_arc_votes[GMU_MAX_GX_FREQS]; struct a6xx_hfi_acd_table acd_table; =20 int nr_gpu_bws; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index 206eb204cea1..53cfdf4e6c34 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -23,6 +23,7 @@ static const char * const a6xx_hfi_msg_id[] =3D { HFI_MSG_ID(HFI_H2F_MSG_START), HFI_MSG_ID(HFI_H2F_FEATURE_CTRL), HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START), + HFI_MSG_ID(HFI_H2F_MSG_TABLE), HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE), HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER), }; @@ -270,11 +271,63 @@ static int a6xx_hfi_send_perf_table_v1(struct a6xx_gm= u *gmu) NULL, 0); } =20 +static int a8xx_hfi_send_perf_table(struct a6xx_gmu *gmu) +{ + unsigned int num_gx_votes =3D 3, num_cx_votes =3D 2; + struct a6xx_hfi_table_entry *entry; + struct a6xx_hfi_table *tbl; + int ret, i; + u32 size; + + size =3D sizeof(*tbl) + (2 * sizeof(tbl->entry[0])) + + (gmu->nr_gpu_freqs * num_gx_votes * sizeof(gmu->gx_arc_votes[0])) + + (gmu->nr_gmu_freqs * num_cx_votes * sizeof(gmu->cx_arc_votes[0])); + tbl =3D kzalloc(size, GFP_KERNEL); + tbl->type =3D HFI_TABLE_GPU_PERF; + + /* First fill GX votes */ + entry =3D &tbl->entry[0]; + entry->count =3D gmu->nr_gpu_freqs; + entry->stride =3D num_gx_votes; + + for (i =3D 0; i < gmu->nr_gpu_freqs; i++) { + unsigned int base =3D i * entry->stride; + + entry->data[base+0] =3D gmu->gx_arc_votes[i]; + entry->data[base+1] =3D gmu->dep_arc_votes[i]; + entry->data[base+2] =3D gmu->gpu_freqs[i] / 1000; + } + + /* Then fill CX votes */ + entry =3D (struct a6xx_hfi_table_entry *) + &tbl->entry[0].data[gmu->nr_gpu_freqs * num_gx_votes]; + + entry->count =3D gmu->nr_gmu_freqs; + entry->stride =3D num_cx_votes; + + for (i =3D 0; i < gmu->nr_gmu_freqs; i++) { + unsigned int base =3D i * entry->stride; + + entry->data[base] =3D gmu->cx_arc_votes[i]; + entry->data[base+1] =3D gmu->gmu_freqs[i] / 1000; + } + + ret =3D a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0); + + kfree(tbl); + return ret; +} + static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_hfi_msg_perf_table msg =3D { 0 }; int i; =20 + if (adreno_is_a8xx(adreno_gpu)) + return a8xx_hfi_send_perf_table(gmu); + msg.num_gpu_levels =3D gmu->nr_gpu_freqs; msg.num_gmu_levels =3D gmu->nr_gmu_freqs; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.h index 653ef720e2da..6f9f74a0bc85 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -185,6 +185,23 @@ struct a6xx_hfi_msg_core_fw_start { u32 handle; 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A major update to the design is the introduction of Slice architecture. Slices are sort of mini-GPUs within the GPU which are more independent in processing Graphics and compute workloads. Also, in addition to the BV and BR pipe we saw in A7x, CP has more concurrency with additional pipes. From a software interface perspective, these changes have a significant impact on the KMD side. First, the GPU register space has been extensively reorganized. Second, to avoid a register space explosion caused by the new slice architecture and additional pipes, many registers are now virtualized, instead of duplicated as in A7x. KMD must configure an aperture register with the appropriate slice and pipe ID before accessing these virtualized registers. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 118 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 23 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 1202 +++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 + drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 1 + 7 files changed, 1321 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7acf2cc13cd0..8aa7d07303fb 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -24,6 +24,7 @@ adreno-y :=3D \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ adreno/a6xx_preempt.o \ + adreno/a8xx_gpu.o \ =20 adreno-$(CONFIG_DEBUG_FS) +=3D adreno/a5xx_debugfs.o \ =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index cede210a0a78..5c30b3258165 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1174,6 +1174,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) return ret; } =20 + /* Read the slice info on A8x GPUs */ + a8xx_gpu_get_slice_info(gpu); + /* Set the bus quota to a reasonable value for boot */ a6xx_gmu_set_initial_bw(gpu, gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index c4dde13e5661..810b64b909f5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -157,7 +157,7 @@ static void update_shadow_rptr(struct msm_gpu *gpu, str= uct msm_ringbuffer *ring) } } =20 -static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -245,14 +245,21 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_= gpu, } =20 if (!sysprof) { - if (!adreno_is_a7xx(adreno_gpu)) { + if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) { /* Turn off protected mode to write to special registers */ OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); OUT_RING(ring, 0); } =20 - OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); - OUT_RING(ring, 1); + if (adreno_is_a8xx(adreno_gpu)) { + OUT_PKT4(ring, REG_A8XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); + OUT_RING(ring, 1); + OUT_PKT4(ring, REG_A8XX_RBBM_SLICE_PERFCTR_SRAM_INIT_CMD, 1); + OUT_RING(ring, 1); + } else { + OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); + OUT_RING(ring, 1); + } } =20 /* Execute the table update */ @@ -281,7 +288,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, * to make sure BV doesn't race ahead while BR is still switching * pagetables. */ - if (adreno_is_a7xx(&a6xx_gpu->base)) { + if (adreno_is_a7xx(&a6xx_gpu->base) || adreno_is_a8xx(&a6xx_gpu->base)) { OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); } @@ -295,20 +302,22 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_= gpu, OUT_RING(ring, CACHE_INVALIDATE); =20 if (!sysprof) { + u32 reg_status =3D adreno_is_a8xx(adreno_gpu) ? + REG_A8XX_RBBM_PERFCTR_SRAM_INIT_STATUS : + REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS; /* * Wait for SRAM clear after the pgtable update, so the * two can happen in parallel: */ OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); - OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO( - REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); + OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(reg_status)); OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0)); OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); =20 - if (!adreno_is_a7xx(adreno_gpu)) { + if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) { /* Re-enable protected mode: */ OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); OUT_RING(ring, 1); @@ -446,6 +455,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct msm_ringbuffer *ring =3D submit->ring; + u32 rbbm_perfctr_cp0, cp_always_on_counter; unsigned int i, ibs =3D 0; =20 adreno_check_and_reenable_stall(adreno_gpu); @@ -466,10 +476,16 @@ static void a7xx_submit(struct msm_gpu *gpu, struct m= sm_gem_submit *submit) if (gpu->nr_rings > 1) a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); =20 - get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), - rbmemptr_stats(ring, index, cpcycles_start)); - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, - rbmemptr_stats(ring, index, alwayson_start)); + if (adreno_is_a8xx(adreno_gpu)) { + rbbm_perfctr_cp0 =3D REG_A8XX_RBBM_PERFCTR_CP(0); + cp_always_on_counter =3D REG_A8XX_CP_ALWAYS_ON_COUNTER; + } else { + rbbm_perfctr_cp0 =3D REG_A7XX_RBBM_PERFCTR_CP(0); + cp_always_on_counter =3D REG_A6XX_CP_ALWAYS_ON_COUNTER; + } + + get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpc= ycles_start)); + get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index,= alwayson_start)); =20 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, CP_SET_THREAD_BOTH); @@ -516,14 +532,17 @@ static void a7xx_submit(struct msm_gpu *gpu, struct m= sm_gem_submit *submit) OUT_RING(ring, 0x00e); /* IB1LIST end */ } =20 - get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), - rbmemptr_stats(ring, index, cpcycles_end)); - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, - rbmemptr_stats(ring, index, alwayson_end)); + get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpc= ycles_end)); + get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index,= alwayson_end)); =20 /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); - OUT_RING(ring, submit->seqno); + if (adreno_is_a8xx(adreno_gpu)) { + OUT_PKT4(ring, REG_A8XX_CP_SCRATCH_GLOBAL(2), 1); + OUT_RING(ring, submit->seqno); + } else { + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); + OUT_RING(ring, submit->seqno); + } =20 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, CP_SET_THREAD_BR); @@ -723,8 +742,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) /* Copy the data into the internal struct to drop the const qualifier (te= mporarily) */ *cfg =3D *common_cfg; =20 - cfg->ubwc_swizzle =3D 0x6; - cfg->highest_bank_bit =3D 15; + /* Use common config as is for A8x */ + if (!adreno_is_a8xx(gpu)) { + cfg->ubwc_swizzle =3D 0x6; + cfg->highest_bank_bit =3D 15; + } =20 if (adreno_is_a610(gpu)) { cfg->highest_bank_bit =3D 13; @@ -1013,7 +1035,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu = *a6xx_gpu, return false; =20 /* A7xx is safe! */ - if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || adreno_is= _a8xx(adreno_gpu)) return true; =20 /* @@ -1127,7 +1149,7 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) return 0; } =20 -static int a6xx_zap_shader_init(struct msm_gpu *gpu) +int a6xx_zap_shader_init(struct msm_gpu *gpu) { static bool loaded; int ret; @@ -2089,7 +2111,7 @@ static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) u32 fuse_val; int ret; =20 - if (adreno_is_a750(adreno_gpu)) { + if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { /* * Assume that if qcom scm isn't available, that whatever * replacement allows writing the fuse register ourselves. @@ -2115,9 +2137,9 @@ static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) return ret; =20 /* - * On a750 raytracing may be disabled by the firmware, find out - * whether that's the case. The scm call above sets the fuse - * register. + * On A7XX_GEN3 and newer, raytracing may be disabled by the + * firmware, find out whether that's the case. The scm call + * above sets the fuse register. */ fuse_val =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); @@ -2178,7 +2200,7 @@ void a6xx_bus_clear_pending_transactions(struct adren= o_gpu *adreno_gpu, bool gx_ void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) { /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ - if (adreno_is_a610(to_adreno_gpu(gpu))) + if (adreno_is_a610(to_adreno_gpu(gpu)) || adreno_is_a8xx(to_adreno_gpu(gp= u))) return; =20 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); @@ -2209,7 +2231,12 @@ static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) =20 msm_devfreq_resume(gpu); =20 - adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activ= ate(a6xx_gpu); + if (adreno_is_a8xx(adreno_gpu)) + a8xx_llc_activate(a6xx_gpu); + else if (adreno_is_a7xx(adreno_gpu)) + a7xx_llc_activate(a6xx_gpu); + else + a6xx_llc_activate(a6xx_gpu); =20 return ret; } @@ -2589,10 +2616,8 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) adreno_gpu->base.hw_apriv =3D !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); =20 - /* gpu->info only gets assigned in adreno_gpu_init() */ - is_a7xx =3D config->info->family =3D=3D ADRENO_7XX_GEN1 || - config->info->family =3D=3D ADRENO_7XX_GEN2 || - config->info->family =3D=3D ADRENO_7XX_GEN3; + /* gpu->info only gets assigned in adreno_gpu_init(). A8x is included int= entionally */ + is_a7xx =3D config->info->family >=3D ADRENO_7XX_GEN1; =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 @@ -2630,7 +2655,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) return ERR_PTR(ret); } =20 - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { ret =3D a7xx_cx_mem_init(a6xx_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); @@ -2754,3 +2779,30 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { .bus_halt =3D a6xx_bus_clear_pending_transactions, .mmu_fault_handler =3D a6xx_fault_handler, }; + +const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a8xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, + .recover =3D a8xx_recover, + .submit =3D a7xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a8xx_irq, + .destroy =3D a6xx_destroy, + .gpu_busy =3D a8xx_gpu_busy, + .gpu_get_freq =3D a6xx_gmu_get_freq, + .gpu_set_freq =3D a6xx_gpu_set_freq, + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a8xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a8xx_gmu_get_timestamp, + .bus_halt =3D a8xx_bus_clear_pending_transactions, + .mmu_fault_handler =3D a8xx_fault_handler, +}; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index ef66e1eb9152..e6218b0b9732 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,8 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist; + const struct adreno_reglist_pipe *nonctxt_reglist; + u32 max_slices; u32 gmu_chipid; u32 gmu_cgc_mode; u32 prim_fifo_threshold; @@ -101,6 +103,11 @@ struct a6xx_gpu { void *htw_llc_slice; bool have_mmu500; bool hung; + + u32 cached_aperture; + spinlock_t aperture_lock; + + u32 slice_mask; }; =20 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) @@ -302,5 +309,19 @@ int a6xx_gpu_state_put(struct msm_gpu_state *state); void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mas= k, bool is_64b); - +void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +int a6xx_zap_shader_init(struct msm_gpu *gpu); + +void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); +int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *dat= a); +void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value); +u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate); +int a8xx_gpu_feature_probe(struct msm_gpu *gpu); +void a8xx_gpu_get_slice_info(struct msm_gpu *gpu); +int a8xx_hw_init(struct msm_gpu *gpu); +irqreturn_t a8xx_irq(struct msm_gpu *gpu); +void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu); +bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +void a8xx_recover(struct msm_gpu *gpu); #endif /* __A6XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c new file mode 100644 index 000000000000..c9cd7546024a --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -0,0 +1,1202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ + + +#include "msm_gem.h" +#include "msm_mmu.h" +#include "msm_gpu_trace.h" +#include "a6xx_gpu.h" +#include "a6xx_gmu.xml.h" + +#include +#include +#include +#include +#include + +#define GPU_PAS_ID 13 + +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe = pipe, u32 slice) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + u32 val; + + val =3D A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_H= OST_SLICEID(slice); + + if (a6xx_gpu->cached_aperture =3D=3D val) + return; + + gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); + + a6xx_gpu->cached_aperture =3D val; +} + +static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pi= pe, unsigned long *flags) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); + + a8xx_aperture_slice_set(gpu, pipe, 0); +} + +static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); +} + +static void a8xx_aperture_clear(struct msm_gpu *gpu) +{ + unsigned long flags; + + a8xx_aperture_acquire(gpu, PIPE_NONE, &flags); + a8xx_aperture_release(gpu, flags); +} + +static void a8xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u3= 2 offset, u32 data) +{ + unsigned long flags; + + a8xx_aperture_acquire(gpu, pipe, &flags); + gpu_write(gpu, offset, data); + a8xx_aperture_release(gpu, flags); +} + +static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe= , u32 slice, u32 offset) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); + a8xx_aperture_slice_set(gpu, pipe, slice); + val =3D gpu_read(gpu, offset); + spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); + + return val; +} + +void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + const struct a6xx_info *info =3D adreno_gpu->info->a6xx; + u32 slice_mask; + + if (adreno_gpu->info->family < ADRENO_8XX_GEN1) + return; + + if (a6xx_gpu->slice_mask) + return; + + slice_mask =3D GENMASK(info->max_slices - 1, 0); + + /* GEN1 doesn't support partial slice configurations */ + if (adreno_gpu->info->family =3D=3D ADRENO_8XX_GEN1) { + a6xx_gpu->slice_mask =3D slice_mask; + return; + } + + slice_mask &=3D a6xx_llc_read(a6xx_gpu, + REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); + + a6xx_gpu->slice_mask =3D slice_mask; + + /* Chip ID depends on the number of slices available. So update it */ + adreno_gpu->chip_id |=3D FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask)); +} + +static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu) +{ + return ffs(a6xx_gpu->slice_mask) - 1; +} + +static inline bool _a8xx_check_idle(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + /* Check that the GMU is idle */ + if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + return false; + + /* Check that the CX master is idle */ + if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) & + ~A8XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) + return false; + + return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) & + A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); +} + +static bool a8xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + /* wait for CP to drain ringbuffer: */ + if (!adreno_idle(gpu, ring)) + return false; + + if (spin_until(_a8xx_check_idle(gpu))) { + DRM_ERROR( + "%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/= wptr %d/%d\n", + gpu->name, __builtin_return_address(0), + gpu_read(gpu, REG_A8XX_RBBM_STATUS), + gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS), + gpu_read(gpu, REG_A6XX_CP_RB_RPTR), + gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); + return false; + } + + return true; +} + +void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + uint32_t wptr; + unsigned long flags; + + spin_lock_irqsave(&ring->preempt_lock, flags); + + /* Copy the shadow to the actual register */ + ring->cur =3D ring->next; + + /* Make sure to wrap wptr if we need to */ + wptr =3D get_wptr(ring); + + /* Update HW if this is the current ring and we are not in preempt*/ + if (!a6xx_in_preempt(a6xx_gpu)) { + if (a6xx_gpu->cur_ring =3D=3D ring) + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + else + ring->restore_wptr =3D true; + } else { + ring->restore_wptr =3D true; + } + + spin_unlock_irqrestore(&ring->preempt_lock, flags); +} + +static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + u32 val; + + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, + state ? 0x110111 : 0); + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, + state ? 0x55555 : 0); + + gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state); + + if (state) { + gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_CGC_P2S_STATUS, val, + val & A8XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } else { + /* + * GMU enables clk gating in GBIF during boot up. So, + * override that here when hwcg feature is disabled + */ + gpu_rmw(gpu, REG_A8XX_GBIF_CX_CONFIG, BIT(0), 0); + } +} + +static void a8xx_set_cp_protect(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + const struct adreno_protect *protect =3D adreno_gpu->info->a6xx->protect; + u32 cntl, final_cfg; + unsigned int i; + + cntl =3D A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN | + A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_FAULT_ON_VIOL_EN | + A8XX_CP_PROTECT_CNTL_PIPE_LAST_SPAN_INF_RANGE | + A8XX_CP_PROTECT_CNTL_PIPE_HALT_SQE_RANGE__MASK; + /* + * Enable access protection to privileged registers, fault on an access + * protect violation and select the last span to protect from the start + * address all the way to the end of the register address space + */ + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); + + a8xx_aperture_clear(gpu); + + for (i =3D 0; i < protect->count; i++) { + /* Intentionally skip writing to some registers */ + if (protect->regs[i]) { + gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); + final_cfg =3D protect->regs[i]; + } + } + + /* + * Last span feature is only supported on PIPE specific register. + * So update those here + */ + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + + a8xx_aperture_clear(gpu); +} + +static void a8xx_set_ubwc_config(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->ubwc_config; + u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L2); + u32 level3_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L3); + bool rgba8888_lossless =3D false, fp16compoptdis =3D false; + bool yuvnotcomptofc =3D false, min_acc_len_64b =3D false; + bool rgb565_predicator =3D false, amsbc =3D false; + bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); + u32 ubwc_version =3D cfg->ubwc_enc_version; + u32 hbb, hbb_hi, hbb_lo, mode =3D 1; + u8 uavflagprd_inv =3D 2; + + switch (ubwc_version) { + case UBWC_5_0: + amsbc =3D true; + rgb565_predicator =3D true; + mode =3D 4; + break; + case UBWC_4_0: + amsbc =3D true; + rgb565_predicator =3D true; + fp16compoptdis =3D true; + rgba8888_lossless =3D true; + mode =3D 2; + break; + case UBWC_3_0: + amsbc =3D true; + mode =3D 1; + break; + default: + dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version); + break; + } + + /* + * We subtract 13 from the highest bank bit (13 is the minimum value + * allowed by hw) and write the lowest two bits of the remaining value + * as hbb_lo and the one above it as hbb_hi to the hardware. + */ + WARN_ON(cfg->highest_bank_bit < 13); + hbb =3D cfg->highest_bank_bit - 13; + hbb_hi =3D hbb >> 2; + hbb_lo =3D hbb & 3; + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5); + + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL, + yuvnotcomptofc << 6 | + hbb_hi << 3 | + hbb_lo << 1); + + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CMP_NC_MODE_CNTL, + mode << 15 | + yuvnotcomptofc << 6 | + rgba8888_lossless << 4 | + fp16compoptdis << 3 | + rgb565_predicator << 2 | + amsbc << 1 | + min_acc_len_64b); + + a8xx_aperture_clear(gpu); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, + level3_swizzling_dis << 13 | + level2_swizzling_dis << 12 | + hbb_hi << 10 | + uavflagprd_inv << 4 | + min_acc_len_64b << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, + level3_swizzling_dis << 7 | + level2_swizzling_dis << 6 | + hbb_hi << 4 | + min_acc_len_64b << 3 | + hbb_lo << 1 | ubwc_mode); +} + +static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + const struct a6xx_info *info =3D adreno_gpu->info->a6xx; + const struct adreno_reglist_pipe *regs =3D info->nonctxt_reglist; + unsigned int pipe_id, i; + unsigned long flags; + + for (pipe_id =3D PIPE_NONE; pipe_id <=3D PIPE_DDE_BV; pipe_id++) { + /* We don't have support for LPAC yet */ + if (pipe_id =3D=3D PIPE_LPAC) + continue; + + a8xx_aperture_acquire(gpu, pipe_id, &flags); + + for (i =3D 0; regs[i].offset; i++) { + if (!(BIT(pipe_id) & regs[i].pipe)) + continue; + + if (regs[i].offset =3D=3D REG_A8XX_RB_GC_GMEM_PROTECT) + *gmem_protect =3D regs[i].value; + + gpu_write(gpu, regs[i].offset, regs[i].value); + } + + a8xx_aperture_release(gpu, flags); + } + + a8xx_aperture_clear(gpu); +} + +static int a8xx_cp_init(struct msm_gpu *gpu) +{ + struct msm_ringbuffer *ring =3D gpu->rb[0]; + u32 mask; + + /* Disable concurrent binning before sending CP init */ + OUT_PKT7(ring, CP_THREAD_CONTROL, 1); + OUT_RING(ring, BIT(27)); + + OUT_PKT7(ring, CP_ME_INIT, 4); + + /* Use multiple HW contexts */ + mask =3D BIT(0); + + /* Enable error detection */ + mask |=3D BIT(1); + + /* Set default reset state */ + mask |=3D BIT(3); + + /* Disable save/restore of performance counters across preemption */ + mask |=3D BIT(6); + + OUT_RING(ring, mask); + + /* Enable multiple hardware contexts */ + OUT_RING(ring, 0x00000003); + + /* Enable error detection */ + OUT_RING(ring, 0x20000000); + + /* Operation mode mask */ + OUT_RING(ring, 0x00000002); + + a6xx_flush(gpu, ring); + return a8xx_idle(gpu, ring) ? 0 : -EINVAL; +} + +#define A8XX_INT_MASK \ + (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ + A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ + A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ + A6XX_RBBM_INT_0_MASK_CP_SW | \ + A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ + A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ + A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ + A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ + A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ + A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ + A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ + A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) + +#define A8XX_APRIV_MASK \ + (A8XX_CP_APRIV_CNTL_PIPE_ICACHE | \ + A8XX_CP_APRIV_CNTL_PIPE_RBFETCH | \ + A8XX_CP_APRIV_CNTL_PIPE_RBPRIVLEVEL | \ + A8XX_CP_APRIV_CNTL_PIPE_RBRPWB) + +#define A8XX_BR_APRIV_MASK \ + (A8XX_APRIV_MASK | \ + A8XX_CP_APRIV_CNTL_PIPE_CDREAD | \ + A8XX_CP_APRIV_CNTL_PIPE_CDWRITE) + +#define A8XX_CP_GLOBAL_INT_MASK \ + (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTLPAC | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE0 | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE1 | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBR | \ + A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBV | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTLPAC | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE0 | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE1 | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBR | \ + A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBV) + +#define A8XX_CP_INTERRUPT_STATUS_MASK_PIPE \ + (A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFRBWRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB1WRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB2WRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB3WRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFSDSWRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFMRBWRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFVSDWRAP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_OPCODEERROR | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VSDPARITYERROR | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_REGISTERPROTECTIONERROR | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_ILLEGALINSTRUCTION | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_SMMUFAULT | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPCLIENT| \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPTYPE | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPREAD | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESP | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTWROVF | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTREFCNTOVF | \ + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTCLRRESMISS) + +#define A8XX_CP_HW_FAULT_STATUS_MASK_PIPE \ + (A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFRBFAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB1FAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB2FAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB3FAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFSDSFAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFMRBFAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFVSDFAULT | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_SQEREADBURSTOVF | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_EVENTENGINEOVF | \ + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_UCODEERROR) + +static int hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + unsigned int pipe_id, i; + u32 gmem_protect =3D 0; + u64 gmem_range_min; + int ret; + + ret =3D a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (ret) + return ret; + + /* Clear the cached value to force aperture configuration next time */ + a6xx_gpu->cached_aperture =3D UINT_MAX; + a8xx_aperture_clear(gpu); + + /* Clear GBIF halt in case GX domain was not collapsed */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_read(gpu, REG_A6XX_GBIF_HALT); + + gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 0); + gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT); + + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); + + /* + * Disable the trusted memory range - we don't actually supported secure + * memory rendering at this point in time and we don't want to block off + * part of the virtual memory space. + */ + gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + + gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); + gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); + gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); + gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); + + /* Make all blocks contribute to the GPU BUSY perf counter */ + gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); + + /* Setup GMEM Range in UCHE */ + gmem_range_min =3D SZ_64M; + /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ + gpu_write64(gpu, REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, gmem_range_min); + gpu_write64(gpu, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, gmem_range_min); + + /* Setup UCHE Trap region */ + gpu_write64(gpu, REG_A8XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); + gpu_write64(gpu, REG_A8XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_bas= e); + gpu_write64(gpu, REG_A8XX_UCHE_CCHE_TRAP_BASE, adreno_gpu->uche_trap_base= ); + gpu_write64(gpu, REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, adreno_gpu->uche_tra= p_base); + + /* Turn on performance counters */ + gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_CNTL, 0x1); + gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, 0x1); + + /* Turn on the IFPC counter (countable 4 on XOCLK1) */ + gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_= 1, + FIELD_PREP(GENMASK(7, 0), 0x4)); + + /* Select CP0 to always count cycles */ + gpu_write(gpu, REG_A8XX_CP_PERFCTR_CP_SEL(0), 1); + + a8xx_set_ubwc_config(gpu); + + /* Set weights for bicubic filtering */ + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 0x3fe05ff4); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 0x3fa0ebee); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 0x3f5193ed); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 0x3f0243f0); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), 0x00000000); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), 0x3fd093e8); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), 0x3f4133dc); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), 0x3ea1dfdb); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), 0x3e0283e0); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), 0x0000ac2b); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), 0x0000f01d); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), 0x00114412); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), 0x0021980a); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), 0x0051ec05); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), 0x0000380e); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), 0x3ff09001); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), 0x3fc10bfa); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), 0x3f9193f7); + gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), 0x3f7227f7); + + gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); + + a8xx_nonctxt_config(gpu, &gmem_protect); + + /* Enable fault detection */ + gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); + gpu_write(gpu, REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, BIT(30)); + + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable the power counter */ + gmu_rmw(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0, 0xff, BIT(= 5)); + gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + + /* Protect registers from the CP */ + a8xx_set_cp_protect(gpu); + + /* Enable the GMEM save/restore feature for preemption */ + a8xx_write_pipe(gpu, PIPE_BR, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTOR= E_ENABLE, 1); + + for (pipe_id =3D PIPE_BR; pipe_id <=3D PIPE_DDE_BV; pipe_id++) { + u32 apriv_mask =3D A8XX_APRIV_MASK; + unsigned long flags; + + if (pipe_id =3D=3D PIPE_LPAC) + continue; + + if (pipe_id =3D=3D PIPE_BR) + apriv_mask =3D A8XX_BR_APRIV_MASK; + + a8xx_aperture_acquire(gpu, pipe_id, &flags); + gpu_write(gpu, REG_A8XX_CP_APRIV_CNTL_PIPE, apriv_mask); + gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, + A8XX_CP_INTERRUPT_STATUS_MASK_PIPE); + gpu_write(gpu, REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, + A8XX_CP_HW_FAULT_STATUS_MASK_PIPE); + a8xx_aperture_release(gpu, flags); + } + + a8xx_aperture_clear(gpu); + + /* Enable interrupts */ + gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, A8XX_CP_GLOBAL_I= NT_MASK); + gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A8XX_INT_MASK); + + ret =3D adreno_hw_init(gpu); + if (ret) + goto out; + + gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); + /* Set the ringbuffer address */ + gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); + gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); + + /* Configure the RPTR shadow if needed: */ + gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0]= )); + gpu_write64(gpu, REG_A8XX_CP_RB_RPTR_ADDR_BV, rbmemptr(gpu->rb[0], bv_rpt= r)); + + for (i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; + + /* Always come up on rb 0 */ + a6xx_gpu->cur_ring =3D gpu->rb[0]; + + for (i =3D 0; i < gpu->nr_rings; i++) + gpu->rb[i]->cur_ctx_seqno =3D 0; + + /* Enable the SQE_to start the CP engine */ + gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 1); + + ret =3D a8xx_cp_init(gpu); + if (ret) + goto out; + + /* + * Try to load a zap shader into the secure world. If successful + * we can use the CP to switch out of secure mode. If not then we + * have no resource but to try to switch ourselves out manually. If we + * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will + * be blocked and a permissions violation will soon follow. + */ + ret =3D a6xx_zap_shader_init(gpu); + if (!ret) { + OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); + OUT_RING(gpu->rb[0], 0x00000000); + + a6xx_flush(gpu, gpu->rb[0]); + if (!a8xx_idle(gpu, gpu->rb[0])) + return -EINVAL; + } else if (ret =3D=3D -ENODEV) { + /* + * This device does not use zap shader (but print a warning + * just in case someone got their dt wrong.. hopefully they + * have a debug UART to realize the error of their ways... + * if you mess this up you are about to crash horribly) + */ + dev_warn_once(gpu->dev->dev, + "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); + ret =3D 0; + } else { + return ret; + } + + /* + * GMEM_PROTECT register should be programmed after GPU is transitioned to + * non-secure mode + */ + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); + WARN_ON(!gmem_protect); + a8xx_aperture_clear(gpu); + + /* Enable hardware clockgating */ + a8xx_set_hwcg(gpu, true); +out: + /* + * Tell the GMU that we are done touching the GPU and it can start power + * management + */ + a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + + return ret; +} + +int a8xx_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int ret; + + mutex_lock(&a6xx_gpu->gmu.lock); + ret =3D hw_init(gpu); + mutex_unlock(&a6xx_gpu->gmu.lock); + + return ret; +} + +static void a8xx_dump(struct msm_gpu *gpu) +{ + DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", gpu_read(gpu, REG_A8XX_= RBBM_STATUS)); + adreno_dump(gpu); +} + +void a8xx_recover(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int active_submits; + + adreno_dump_info(gpu); + + if (hang_debug) + a8xx_dump(gpu); + + /* + * To handle recovery specific sequences during the rpm suspend we are + * about to trigger + */ + a6xx_gpu->hung =3D true; + + /* Halt SQE first */ + gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 3); + + pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); + + /* active_submit won't change until we make a submission */ + mutex_lock(&gpu->active_lock); + active_submits =3D gpu->active_submits; + + /* + * Temporarily clear active_submits count to silence a WARN() in the + * runtime suspend cb + */ + gpu->active_submits =3D 0; + + reinit_completion(&gmu->pd_gate); + dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); + dev_pm_genpd_synced_poweroff(gmu->cxpd); + + /* Drop the rpm refcount from active submits */ + if (active_submits) + pm_runtime_put(&gpu->pdev->dev); + + /* And the final one from recover worker */ + pm_runtime_put_sync(&gpu->pdev->dev); + + if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) + DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); + + dev_pm_genpd_remove_notifier(gmu->cxpd); + + pm_runtime_use_autosuspend(&gpu->pdev->dev); + + if (active_submits) + pm_runtime_get(&gpu->pdev->dev); + + pm_runtime_get_sync(&gpu->pdev->dev); + + gpu->active_submits =3D active_submits; + mutex_unlock(&gpu->active_lock); + + msm_gpu_hw_init(gpu); + a6xx_gpu->hung =3D false; +} + +static const char *a8xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) +{ + static const char * const uche_clients[] =3D { + "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", "BR_HLSQ", "BR_PC", "BR_LRZ", "BR= _TP", + "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", "BV_HLSQ", "BV_PC", "BV_LRZ", "BV= _TP", + "STCHE", + }; + static const char * const uche_clients_lpac[] =3D { + "-", "SP_LPAC", "-", "-", "HLSQ_LPAC", "-", "-", "TP_LPAC", + }; + u32 val; + + /* + * The source of the data depends on the mid ID read from FSYNR1. + * and the client ID read from the UCHE block + */ + val =3D gpu_read(gpu, REG_A8XX_UCHE_CLIENT_PF); + + val &=3D GENMASK(6, 0); + + /* mid=3D3 refers to BR or BV */ + if (mid =3D=3D 3) { + if (val < ARRAY_SIZE(uche_clients)) + return uche_clients[val]; + else + return "UCHE"; + } + + /* mid=3D8 refers to LPAC */ + if (mid =3D=3D 8) { + if (val < ARRAY_SIZE(uche_clients_lpac)) + return uche_clients_lpac[val]; + else + return "UCHE_LPAC"; + } + + return "Unknown"; +} + +static const char *a8xx_fault_block(struct msm_gpu *gpu, u32 id) +{ + switch (id) { + case 0x0: + return "CP"; + case 0x1: + return "UCHE: Unknown"; + case 0x2: + return "UCHE_LPAC: Unknown"; + case 0x3: + case 0x8: + return a8xx_uche_fault_block(gpu, id); + case 0x4: + return "CCU"; + case 0x5: + return "Flag cache"; + case 0x6: + return "PREFETCH"; + case 0x7: + return "GMU"; + case 0x9: + return "UCHE_HPAC"; + } + + return "Unknown"; +} + +int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *dat= a) +{ + struct msm_gpu *gpu =3D arg; + struct adreno_smmu_fault_info *info =3D data; + const char *block =3D "unknown"; + + u32 scratch[] =3D { + gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(0)), + gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(1)), + gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(2)), + gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(3)), + }; + + if (info) + block =3D a8xx_fault_block(gpu, info->fsynr1 & 0xff); + + return adreno_fault_handler(gpu, iova, flags, info, block, scratch); +} + +static void a8xx_cp_hw_err_irq(struct msm_gpu *gpu) +{ + u32 status =3D gpu_read(gpu, REG_A8XX_CP_INTERRUPT_STATUS_GLOBAL); + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + u32 slice =3D a8xx_get_first_slice(a6xx_gpu); + u32 hw_fault_mask =3D GENMASK(6, 0); + u32 sw_fault_mask =3D GENMASK(22, 16); + u32 pipe =3D 0; + + dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Global INT status: 0x%x\n"= , status); + + if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR | + A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR)) + pipe |=3D BIT(PIPE_BR); + + if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV | + A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV)) + pipe |=3D BIT(PIPE_BV); + + if (!pipe) { + dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Unknown pipe\n"); + goto out; + } + + for (unsigned int pipe_id =3D PIPE_NONE; pipe_id <=3D PIPE_DDE_BV; pipe_i= d++) { + if (!(BIT(pipe_id) & pipe)) + continue; + + if (hw_fault_mask & status) { + status =3D a8xx_read_pipe_slice(gpu, pipe_id, slice, + REG_A8XX_CP_HW_FAULT_STATUS_PIPE); + dev_err_ratelimited(&gpu->pdev->dev, + "CP HW FAULT pipe: %u status: 0x%x\n", pipe_id, status); + } + + if (sw_fault_mask & status) { + status =3D a8xx_read_pipe_slice(gpu, pipe_id, slice, + REG_A8XX_CP_INTERRUPT_STATUS_PIPE); + dev_err_ratelimited(&gpu->pdev->dev, + "CP SW FAULT pipe: %u status: 0x%x\n", pipe_id, status); + + if (status & BIT(8)) { + a8xx_write_pipe(gpu, pipe_id, REG_A8XX_CP_SQE_STAT_ADDR_PIPE, 1); + status =3D a8xx_read_pipe_slice(gpu, pipe_id, slice, + REG_A8XX_CP_SQE_STAT_DATA_PIPE); + dev_err_ratelimited(&gpu->pdev->dev, + "CP Opcode error, opcode=3D0x%x\n", status); + } + + if (status & BIT(10)) { + status =3D a8xx_read_pipe_slice(gpu, pipe_id, slice, + REG_A8XX_CP_PROTECT_STATUS_PIPE); + dev_err_ratelimited(&gpu->pdev->dev, + "CP REG PROTECT error, status=3D0x%x\n", status); + } + } + } + +out: + /* Turn off interrupts to avoid triggering recovery again */ + a8xx_aperture_clear(gpu); + gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, 0); + gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, 0); + + kthread_queue_work(gpu->worker, &gpu->recover_work); +} + +static u32 gpu_periph_read(struct msm_gpu *gpu, u32 dbg_offset) +{ + gpu_write(gpu, REG_A8XX_CP_SQE_UCODE_DBG_ADDR_PIPE, dbg_offset); + + return gpu_read(gpu, REG_A8XX_CP_SQE_UCODE_DBG_DATA_PIPE); +} + +static u64 gpu_periph_read64(struct msm_gpu *gpu, u32 dbg_offset) +{ + u64 lo, hi; + + lo =3D gpu_periph_read(gpu, dbg_offset); + hi =3D gpu_periph_read(gpu, dbg_offset + 1); + + return (hi << 32) | lo; +} + +#define CP_PERIPH_IB1_BASE_LO 0x7005 +#define CP_PERIPH_IB1_BASE_HI 0x7006 +#define CP_PERIPH_IB1_SIZE 0x7007 +#define CP_PERIPH_IB1_OFFSET 0x7008 +#define CP_PERIPH_IB2_BASE_LO 0x7009 +#define CP_PERIPH_IB2_BASE_HI 0x700a +#define CP_PERIPH_IB2_SIZE 0x700b +#define CP_PERIPH_IB2_OFFSET 0x700c +#define CP_PERIPH_IB3_BASE_LO 0x700d +#define CP_PERIPH_IB3_BASE_HI 0x700e +#define CP_PERIPH_IB3_SIZE 0x700f +#define CP_PERIPH_IB3_OFFSET 0x7010 + +static void a8xx_fault_detect_irq(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring =3D gpu->funcs->active_ring(gpu); + unsigned long flags; + + /* + * If stalled on SMMU fault, we could trip the GPU's hang detection, + * but the fault handler will trigger the devcore dump, and we want + * to otherwise resume normally rather than killing the submit, so + * just bail. + */ + if (gpu_read(gpu, REG_A8XX_RBBM_MISC_STATUS) & A8XX_RBBM_MISC_STATUS_SMMU= _STALLED_ON_FAULT) + return; + + /* + * Force the GPU to stay on until after we finish + * collecting information + */ + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + + DRM_DEV_ERROR(&gpu->pdev->dev, + "gpu fault ring %d fence %x status %8.8X gfx_status %8.8X\n", + ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, + gpu_read(gpu, REG_A8XX_RBBM_STATUS), gpu_read(gpu, REG_A8XX_RBBM_GFX_STA= TUS)); + + a8xx_aperture_acquire(gpu, PIPE_BR, &flags); + + DRM_DEV_ERROR(&gpu->pdev->dev, + "BR: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x= ib3 %16.16llX/%4.4x\n", + gpu_read(gpu, REG_A8XX_RBBM_GFX_BR_STATUS), + gpu_read(gpu, REG_A6XX_CP_RB_RPTR), + gpu_read(gpu, REG_A6XX_CP_RB_WPTR), + gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET), + gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET), + gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET)); + + a8xx_aperture_release(gpu, flags); + a8xx_aperture_acquire(gpu, PIPE_BV, &flags); + + DRM_DEV_ERROR(&gpu->pdev->dev, + "BV: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x= ib3 %16.16llX/%4.4x\n", + gpu_read(gpu, REG_A8XX_RBBM_GFX_BV_STATUS), + gpu_read(gpu, REG_A8XX_CP_RB_RPTR_BV), + gpu_read(gpu, REG_A6XX_CP_RB_WPTR), + gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET), + gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET), + gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO), + gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET)); + + a8xx_aperture_release(gpu, flags); + a8xx_aperture_clear(gpu); + + /* Turn off the hangcheck timer to keep it from bothering us */ + timer_delete(&gpu->hangcheck_timer); + + kthread_queue_work(gpu->worker, &gpu->recover_work); +} + +static void a8xx_sw_fuse_violation_irq(struct msm_gpu *gpu) +{ + u32 status; + + status =3D gpu_read(gpu, REG_A8XX_RBBM_SW_FUSE_INT_STATUS); + gpu_write(gpu, REG_A8XX_RBBM_SW_FUSE_INT_MASK, 0); + + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=3D%8.8x\n"= , status); + + /* + * Ignore FASTBLEND violations, because the HW will silently fall back + * to legacy blending. + */ + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { + timer_delete(&gpu->hangcheck_timer); + + kthread_queue_work(gpu->worker, &gpu->recover_work); + } +} + +irqreturn_t a8xx_irq(struct msm_gpu *gpu) +{ + struct msm_drm_private *priv =3D gpu->dev->dev_private; + u32 status =3D gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS); + + gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status); + + if (priv->disable_err_irq) + status &=3D A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; + + if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) + a8xx_fault_detect_irq(gpu); + + if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) { + u32 rl0, rl1; + + rl0 =3D gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0); + rl1 =3D gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1); + dev_err_ratelimited(&gpu->pdev->dev, + "CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1); + } + + if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) + a8xx_cp_hw_err_irq(gpu); + + if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) + dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); + + if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) + dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); + + if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) + dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); + + if (status & A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) + dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Trap interrupt\n"); + + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) + a8xx_sw_fuse_violation_irq(gpu); + + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { + msm_gpu_retire(gpu); + a6xx_preempt_trigger(gpu); + } + + if (status & A6XX_RBBM_INT_0_MASK_CP_SW) + a6xx_preempt_irq(gpu); + + return IRQ_HANDLED; +} + +void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu) +{ + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; + + if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { + u32 gpu_scid =3D llcc_get_slice_id(a6xx_gpu->llc_slice); + + gpu_scid &=3D GENMASK(5, 0); + + gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, + FIELD_PREP(GENMASK(29, 24), gpu_scid) | + FIELD_PREP(GENMASK(23, 18), gpu_scid) | + FIELD_PREP(GENMASK(17, 12), gpu_scid) | + FIELD_PREP(GENMASK(11, 6), gpu_scid) | + FIELD_PREP(GENMASK(5, 0), gpu_scid)); + + gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, + FIELD_PREP(GENMASK(27, 22), gpu_scid) | + FIELD_PREP(GENMASK(21, 16), gpu_scid) | + FIELD_PREP(GENMASK(15, 10), gpu_scid) | + BIT(8)); + } + + llcc_slice_activate(a6xx_gpu->htw_llc_slice); +} + +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) +#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 + +void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) +{ + struct msm_gpu *gpu =3D &adreno_gpu->base; + + if (gx_off) { + /* Halt the gx side of GBIF */ + gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 1); + spin_until(gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT_ACK) & 1); + } + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); + + /* The GBIF halt needs to be explicitly cleared */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); +} + +int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + /* Force the GPU power on so we can read this register */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); + + *value =3D gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER); + + a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + return 0; +} + +u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + u64 busy_cycles; + + /* 19.2MHz */ + *out_sample_rate =3D 19200000; + + busy_cycles =3D gmu_read64(&a6xx_gpu->gmu, + REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, + REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); + + return busy_cycles; +} + +bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + return true; +} diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index dfc1bf499b08..c496b63ffd41 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -88,6 +88,13 @@ struct adreno_reglist { u32 value; }; =20 +/* Reglist with pipe information */ +struct adreno_reglist_pipe { + u32 offset; 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Add support for loading the AQE firmware and initialize the necessary registers. Since AQE engine has dependency on preemption context records, expose Raytracing support to userspace only when preemption is enabled. Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 4 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 810b64b909f5..9a643bcccdcf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1118,6 +1118,23 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) } } =20 + if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) { + a6xx_gpu->aqe_bo =3D adreno_fw_create_bo(gpu, + adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova); + + if (IS_ERR(a6xx_gpu->aqe_bo)) { + int ret =3D PTR_ERR(a6xx_gpu->aqe_bo); + + a6xx_gpu->aqe_bo =3D NULL; + DRM_DEV_ERROR(&gpu->pdev->dev, + "Could not allocate AQE ucode: %d\n", ret); + + return ret; + } + + msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw"); + } + /* * Expanded APRIV and targets that support WHERE_AM_I both need a * privileged buffer to store the RPTR shadow @@ -2400,6 +2417,11 @@ static void a6xx_destroy(struct msm_gpu *gpu) drm_gem_object_put(a6xx_gpu->sqe_bo); } =20 + if (a6xx_gpu->aqe_bo) { + msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm); + drm_gem_object_put(a6xx_gpu->aqe_bo); + } + if (a6xx_gpu->shadow_bo) { msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm); drm_gem_object_put(a6xx_gpu->shadow_bo); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index e6218b0b9732..3a054fcdeb4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -59,6 +59,8 @@ struct a6xx_gpu { =20 struct drm_gem_object *sqe_bo; uint64_t sqe_iova; + struct drm_gem_object *aqe_bo; + uint64_t aqe_iova; =20 struct msm_ringbuffer *cur_ring; struct msm_ringbuffer *next_ring; diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index c9cd7546024a..e011e80ceb50 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -627,6 +627,9 @@ static int hw_init(struct msm_gpu *gpu) goto out; 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It comes in 2 variants with either 2 or 3 Slices. This is in addition to the SKUs supported based on the GPU FMAX. Add the necessary register configurations to the catalog and enable support for it. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 159 +++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 2 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + 5 files changed, 174 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 70433965c303..94ac792fb796 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1628,6 +1628,164 @@ static const struct adreno_info a7xx_gpus[] =3D { }; DECLARE_ADRENO_GPULIST(a7xx); =20 +static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + /* Disable Dead Draw Merge scheme on RB-HLSQ */ + { REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE)= }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* Disable mode_switch optimization in UMAS */ + { REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) }, + /* Disable LPAC large-LM mode */ + { REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) }, + /* Disable PS out of order retire */ + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + /* Disable SP2TP info attribute */ + { REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) }, + /* Ignore HLSQ shared constant feedback from SP */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) }, + /* Disable CS dead batch merge */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) }, + { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { }, +}; + +static const u32 a840_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x001b), + A6XX_PROTECT_NORDWR(0x00775, 0x000a), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_NORDWR(0x00c07, 0x0008), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x0009), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a840_protect, 15); + +static const struct adreno_info a8xx_gpus[] =3D { + { + .chip_ids =3D ADRENO_CHIP_IDS(0x44050a01), + .family =3D ADRENO_8XX_GEN2, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80200_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80200_gmu.bin", + [ADRENO_FW_AQE] =3D "gen80200_aqe.fw", + }, + .gmem =3D 18 * SZ_1M, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .funcs =3D &a8xx_gpu_funcs, + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &a840_protect, + .nonctxt_reglist =3D a840_nonctxt_regs, + .max_slices =3D 3, + .gmu_chipid =3D 0x8020100, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size =3D 19708 * SZ_1K, + } +}; + +DECLARE_ADRENO_GPULIST(a8xx); + static inline __always_unused void __build_asserts(void) { BUILD_BUG_ON(a630_protect.count > a630_protect.count_max); @@ -1635,4 +1793,5 @@ static inline __always_unused void __build_asserts(vo= id) BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); + BUILD_BUG_ON(a840_protect.count > a840_protect.count_max); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 5c30b3258165..d5e000676258 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -601,16 +601,22 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu) =20 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) { + struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + u32 bitmask =3D BIT(16); int ret; u32 val; =20 if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) return; =20 + if (adreno_is_a840(adreno_gpu)) + bitmask =3D BIT(30); + gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); =20 ret =3D gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, - val, val & (1 << 16), 100, 10000); + val, val & bitmask, 100, 10000); if (ret) DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 3a054fcdeb4a..0ec265d4b91a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -228,6 +228,7 @@ struct a7xx_cp_smmu_info { extern const struct adreno_gpu_funcs a6xx_gpu_funcs; extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs; extern const struct adreno_gpu_funcs a7xx_gpu_funcs; +extern const struct adreno_gpu_funcs a8xx_gpu_funcs; =20 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index cb4113612b82..554d746f115b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -34,6 +34,7 @@ extern const struct adreno_gpulist a4xx_gpulist; extern const struct adreno_gpulist a5xx_gpulist; extern const struct adreno_gpulist a6xx_gpulist; extern const struct adreno_gpulist a7xx_gpulist; +extern const struct adreno_gpulist a8xx_gpulist; =20 static const struct adreno_gpulist *gpulists[] =3D { &a2xx_gpulist, @@ -42,6 +43,7 @@ static const struct adreno_gpulist *gpulists[] =3D { &a5xx_gpulist, &a6xx_gpulist, &a7xx_gpulist, + &a8xx_gpulist, }; =20 static const struct adreno_info *adreno_info(uint32_t chip_id) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 0aca222c46bc..7a8cb1ea2a38 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_a840(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44050a01; +} + /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ #define ADRENO_VM_START 0x100000000ULL u64 adreno_private_vm_size(struct msm_gpu *gpu); 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So do CX GBIF configurations before GMU wakes up. This was not a problem so far, but A840 GPU is very sensitive to this requirement. Also, move these registers to the catalog. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 32 +++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ------- 5 files changed, 54 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 94ac792fb796..e0bb2c334301 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -672,6 +672,14 @@ static const u32 a690_protect_regs[] =3D { }; DECLARE_ADRENO_PROTECT(a690_protect, 48); =20 +static const struct adreno_reglist a640_gbif[] =3D { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 }, + { }, +}; + static const struct adreno_info a6xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x06010000), @@ -688,6 +696,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a612_hwcg, .protect =3D &a630_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020202, .prim_fifo_threshold =3D 0x00080000, }, @@ -894,6 +903,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a620_hwcg, .protect =3D &a650_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020200, .prim_fifo_threshold =3D 0x00010000, }, @@ -916,6 +926,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a650_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020200, .prim_fifo_threshold =3D 0x00010000, .bcms =3D (const struct a6xx_bcm[]) { @@ -998,6 +1009,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a650_hwcg, .protect =3D &a650_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020202, .prim_fifo_threshold =3D 0x00300200, }, @@ -1024,6 +1036,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, .protect =3D &a660_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020000, .prim_fifo_threshold =3D 0x00300200, }, @@ -1042,6 +1055,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a660_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020200, .prim_fifo_threshold =3D 0x00300200, }, @@ -1066,6 +1080,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, .protect =3D &a660_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020202, .prim_fifo_threshold =3D 0x00200200, }, @@ -1112,6 +1127,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a690_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020200, .prim_fifo_threshold =3D 0x00800200, }, @@ -1447,6 +1463,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a702_hwcg, .protect =3D &a650_protect, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020202, .prim_fifo_threshold =3D 0x0000c000, }, @@ -1474,6 +1491,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a730_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a640_gbif, .gmu_cgc_mode =3D 0x00020000, }, .preempt_record_size =3D 2860 * SZ_1K, @@ -1495,6 +1513,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7020100, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1529,6 +1548,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, + .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7050001, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1570,6 +1590,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, + .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x7090100, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1602,6 +1623,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a640_gbif, .gmu_chipid =3D 0x70f0000, .gmu_cgc_mode =3D 0x00020222, .bcms =3D (const struct a6xx_bcm[]) { @@ -1749,6 +1771,15 @@ static const u32 a840_protect_regs[] =3D { }; DECLARE_ADRENO_PROTECT(a840_protect, 15); =20 +static const struct adreno_reglist a840_gbif[] =3D { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, + { REG_A8XX_GBIF_CX_CONFIG, 0x20023000 }, + { }, +}; + static const struct adreno_info a8xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x44050a01), @@ -1766,6 +1797,7 @@ static const struct adreno_info a8xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .protect =3D &a840_protect, .nonctxt_reglist =3D a840_nonctxt_regs, + .gbif_cx =3D a840_gbif, .max_slices =3D 3, .gmu_chipid =3D 0x8020100, .bcms =3D (const struct a6xx_bcm[]) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index d5e000676258..5903cd891b49 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -894,7 +894,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) { struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; const struct a6xx_info *a6xx_info =3D adreno_gpu->info->a6xx; + const struct adreno_reglist *gbif_cx =3D a6xx_info->gbif_cx; u32 fence_range_lower, fence_range_upper; u32 chipid =3D 0; int ret; @@ -990,6 +992,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) gmu->log.iova | (gmu->log.size / SZ_4K - 1)); } =20 + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ + for (int i =3D 0; (gbif_cx && gbif_cx[i].offset); i++) + gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); + + if (adreno_is_a8xx(adreno_gpu)) { + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); + } + /* Set up the lowest idle level on the GMU */ a6xx_gmu_power_config(gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 9a643bcccdcf..4d6f47666ff6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1279,17 +1279,20 @@ static int hw_init(struct msm_gpu *gpu) /* enable hardware clockgating */ a6xx_set_hwcg(gpu, true); =20 - /* VBIF/GBIF start*/ - if (adreno_is_a610_family(adreno_gpu) || - adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here= */ + if (adreno_is_a610_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, - adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); + } + + if (adreno_is_a610_family(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || + adreno_is_a650_family(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); + } else if (adreno_is_a7xx(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 0ec265d4b91a..6820216ec5fc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,7 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist; + const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; u32 max_slices; u32 gmu_chipid; diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index e011e80ceb50..43b886ff576d 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -519,13 +519,6 @@ static int hw_init(struct msm_gpu *gpu) gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); =20 - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); - gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); - /* Make all blocks contribute to the GPU BUSY perf counter */ gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 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It is based on the new A8x slice architecture and features up to 4 slices. Due to the wider 12 channel DDR support, there is higher DDR bandwidth available than previous generation to improve performance. Add a new entry in the catalog along with the necessary register configurations to enable support for it. Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 132 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++ 3 files changed, 140 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index e0bb2c334301..29107b362346 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1650,6 +1650,108 @@ static const struct adreno_info a7xx_gpus[] =3D { }; DECLARE_ADRENO_GPULIST(a7xx); =20 +static const struct adreno_reglist_pipe x285_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + /* Disable CS dead batch merge */ + { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { }, +}; + +static const u32 x285_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00008, 0x039b), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x0082c, 0x0000), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), + A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), + A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), + A6XX_PROTECT_NORDWR(0x0af00, 0x027f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0507), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0385), + A6XX_PROTECT_NORDWR(0x27882, 0x000a), + A6XX_PROTECT_NORDWR(0x27c06, 0x0000), +}; + +DECLARE_ADRENO_PROTECT(x285_protect, 64); + static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -1782,6 +1884,36 @@ static const struct adreno_reglist a840_gbif[] =3D { =20 static const struct adreno_info a8xx_gpus[] =3D { { + .chip_ids =3D ADRENO_CHIP_IDS(0x44070001), + .family =3D ADRENO_8XX_GEN2, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80100_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80100_gmu.bin", + }, + .gmem =3D 21 * SZ_1M, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .funcs =3D &a8xx_gpu_funcs, + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &x285_protect, + .nonctxt_reglist =3D x285_nonctxt_regs, + .gbif_cx =3D a840_gbif, + .max_slices =3D 4, + .gmu_chipid =3D 0x8010100, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 16500000, + }, + { /* sentinel */ }, + }, + }, + }, { .chip_ids =3D ADRENO_CHIP_IDS(0x44050a01), .family =3D ADRENO_8XX_GEN2, .fw =3D { diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 43b886ff576d..30de078e9dfd 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -190,6 +190,9 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool sta= te) struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; u32 val; =20 + if (adreno_is_x285(adreno_gpu) && state) + gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 7a8cb1ea2a38..0f8d3de97636 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_x285(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44070001; +} + static inline int adreno_is_a840(struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x44050a01; --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46FD730E0ED for ; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index 89495f094d52..c9efdd1a6d1c 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -89,6 +89,8 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "ar= m,mmu-500" items: - enum: + - qcom,glymur-smmu-500 + - qcom,kaanapali-smmu-500 - qcom,milos-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E82732BF40 for ; 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Acked-by: Rob Herring (Arm) Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gmu.yaml | 30 ++++++++++++++++++= +++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index afc187935744..2ef8fd7e9f52 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -21,7 +21,7 @@ properties: compatible: oneOf: - items: - - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - items: - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$' @@ -299,6 +299,34 @@ allOf: required: - qcom,qmp =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-840.1 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: memnoc + - const: hub + - if: properties: compatible: --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D365C32D455 for ; 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It is very similar to Adreno 840 GMU with the additional requirement of RSCC HUB clock. Acked-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gmu.yaml | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index 2ef8fd7e9f52..e32056ae0f5d 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -327,6 +327,36 @@ allOf: - const: memnoc - const: hub =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-x285.1 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GMU RSCC HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: memnoc + - const: hub + - const: rscc + - if: properties: compatible: --=20 2.51.0 From nobody Tue Dec 2 02:43:43 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE27313E04 for ; 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Add support for this. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 30de078e9dfd..5a320f5bde41 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -276,6 +276,10 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) u8 uavflagprd_inv =3D 2; =20 switch (ubwc_version) { + case UBWC_6_0: + yuvnotcomptofc =3D true; + mode =3D 5; + break; case UBWC_5_0: amsbc =3D true; rgb565_predicator =3D true; --=20 2.51.0