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Tue, 18 Nov 2025 08:28:22 -0800 (PST) From: James Clark Date: Tue, 18 Nov 2025 16:27:59 +0000 Subject: [PATCH v5 09/13] coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-james-cs-syncfreq-v5-9-82efd7b1a751@linaro.org> References: <20251118-james-cs-syncfreq-v5-0-82efd7b1a751@linaro.org> In-Reply-To: <20251118-james-cs-syncfreq-v5-0-82efd7b1a751@linaro.org> To: Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan , Randy Dunlap Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Remove hard coded bitfield extractions and shifts and replace with ATTR_CFG_GET_FLD(). ETM4_CFG_BIT_BB was defined to give the register bit positions to userspace, TRCCONFIGR_BB should be used in the kernel so replace it. Reviewed-by: Leo Yan Signed-off-by: James Clark Reviewed-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 44 ++++++++++--------= ---- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 5d21af346799..c7208ffc9432 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -780,17 +781,17 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, goto out; =20 /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) { + if (ATTR_CFG_GET_FLD(attr, cycacc)) { config->cfg |=3D TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - cc_threshold =3D attr->config3 & ETM_CYC_THRESHOLD_MASK; + cc_threshold =3D ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold =3D ETM_CYC_THRESHOLD_DEFAULT; if (cc_threshold < drvdata->ccitmin) cc_threshold =3D drvdata->ccitmin; config->ccctlr =3D cc_threshold; } - if (attr->config & BIT(ETM_OPT_TS)) { + if (ATTR_CFG_GET_FLD(attr, timestamp)) { /* * Configure timestamps to be emitted at regular intervals in * order to correlate instructions executed on different CPUs @@ -810,17 +811,17 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, } =20 /* Only trace contextID when runs in root PID namespace */ - if ((attr->config & BIT(ETM_OPT_CTXTID)) && + if (ATTR_CFG_GET_FLD(attr, contextid1) && task_is_in_init_pid_ns(current)) /* bit[6], Context ID tracing bit */ config->cfg |=3D TRCCONFIGR_CID; =20 /* - * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID - * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the - * kernel is not running in EL2. + * If set bit contextid2 in perf config, this asks to trace VMID for + * recording CONTEXTIDR_EL2. Do not enable VMID tracing if the kernel + * is not running in EL2. */ - if (attr->config & BIT(ETM_OPT_CTXTID2)) { + if (ATTR_CFG_GET_FLD(attr, contextid2)) { if (!is_kernel_in_hyp_mode()) { ret =3D -EINVAL; goto out; @@ -831,26 +832,22 @@ static int etm4_parse_event_config(struct coresight_d= evice *csdev, } =20 /* return stack - enable if selected and supported */ - if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) + if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack) /* bit[12], Return stack enable bit */ config->cfg |=3D TRCCONFIGR_RS; =20 /* - * Set any selected configuration and preset. - * - * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_A= TTR(preset) - * in the perf attributes defined in coresight-etm-perf.c. - * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of att= r->config. - * A zero configid means no configuration active, preset =3D 0 means no p= reset selected. + * Set any selected configuration and preset. A zero configid means no + * configuration active, preset =3D 0 means no preset selected. */ - if (attr->config2 & GENMASK_ULL(63, 32)) { - cfg_hash =3D (u32)(attr->config2 >> 32); - preset =3D attr->config & 0xF; + cfg_hash =3D ATTR_CFG_GET_FLD(attr, configid); + if (cfg_hash) { + preset =3D ATTR_CFG_GET_FLD(attr, preset); ret =3D cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); } =20 /* branch broadcast - enable if selected and supported */ - if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { + if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { if (!drvdata->trcbb) { /* * Missing BB support could cause silent decode errors @@ -859,7 +856,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, ret =3D -EINVAL; goto out; } else { - config->cfg |=3D BIT(ETM4_CFG_BIT_BB); + config->cfg |=3D TRCCONFIGR_BB; } } =20 @@ -1083,11 +1080,8 @@ static int etm4_disable_perf(struct coresight_device= *csdev, return -EINVAL; =20 etm4_disable_hw(drvdata); - /* - * The config_id occupies bits 63:32 of the config2 perf event attr - * field. If this is non-zero then we will have enabled a config. - */ - if (attr->config2 & GENMASK_ULL(63, 32)) + /* If configid is non-zero then we will have enabled a config. */ + if (ATTR_CFG_GET_FLD(attr, configid)) cscfg_csdev_disable_active_config(csdev); =20 /* --=20 2.34.1