From nobody Tue Dec 2 02:42:37 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05BF03A79C0 for ; Tue, 18 Nov 2025 16:28:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763483311; cv=none; b=jGWb0dDE0AhGivp7FHrHpwPMZpsXCWYK9dqDzfg3g4S6eOT0cn0lTewPDSJPiUfzOYqKZpZIzkIG/dWlh4Xhaq3NaQUgTNnxOcGT69hInAKfBrIJPlX4//TzRrqB7JlRa+4VwSPoVOePF8nljQBO2N6w3vWZJVmngn1cBEE0z9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763483311; c=relaxed/simple; bh=NnmS95dIHybC4skUiX6A9lTrG4BjKAs84lg0zH2yXbs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BMXpohs86VlWFI80SC1FZHGxFmQivF+vV/4ZSEOKz5EF7j9zcpBn6W4KIQCFqq+l4aXHkecLWqjBkKXiMdLxgTLNNOxJoK/JufupuEyh3b9r/9T6ugGfm9rSZDg+Bb3NRNOK78PzTdEWMKvIb68I14xIKV59xjo7ob0W9COWE+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=MxUlGS6m; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MxUlGS6m" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4779adb38d3so26953215e9.2 for ; Tue, 18 Nov 2025 08:28:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1763483306; x=1764088106; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1J9cD8iib5vPgkzAOKKPeHwOoJIQqK3mSiazT8xg6Hc=; b=MxUlGS6mE16keqPdDSxl4+RyyAcKga4zCXeA6FpCcj7cLJ0F+mGZyGQnD5kJsFwKOD msTtkmdlBx4bdR3ytCJP0aogD9nvXomL+YPOU+11qwUgbPcJqFiA1rK+oB9yevSmhuW2 5bgrhmNiDQB0WqSZRhmrg9MGcNM5MhXPtqCEZB2PSKSq6pmfzfUVtJyFQLEppzOOO+3o sPSl/x0hPiHDGarWAaW7XkkLvrzq7IPQVt10J+bHi6JHQfJCnMBLl5w4A1BXJxfAFStK eVlmviCC3diLELUPrFHVMrZirIhObL42/z2dCe8ZnHhpt/mKRnsAfZ4xPkMxN6zLGgjD rs4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763483306; x=1764088106; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1J9cD8iib5vPgkzAOKKPeHwOoJIQqK3mSiazT8xg6Hc=; b=bWxoasg/KHCf2hQx/sOtRQVq2Iw6dsvSnG/HfQrOGaQ5lXzWpG6tkAYlIIGt5xbyba ZZtpl3tpra/K7lUJLlCXZF6QlMXaOc7GcVuteR/o2GlQuFbaaH686adj2YeeEhjHix+5 XlpwVltq5usXrssu6IlS+UEKbH6KrS+S20HEEOd1hr0fVz/GE8RBz9d7/mKi8vvuWtZp yeQ6KhrHbrtBin5Yc+Rc+4O2Q/95TD5QAA9Qm2P6EgjPuiY8yOT2giK+SE5KWGIhXOoZ DpzmPlNT3lmwzf10S7Es2eB7CEiT6ErOkkbOx0NBfLHNenUJl88qD/bdSH4KabhcEV5l SZ8w== X-Forwarded-Encrypted: i=1; AJvYcCWuDNnN4drxJ1H10Q8/q1SQ1cD8568V5NS/usOnhFLAzRoOIveirtLnwSsErZPQ+k+3oX2EvV/H6zJHNis=@vger.kernel.org X-Gm-Message-State: AOJu0YyZT/3ITCX9ta03W3D0+ROURr+/YY6f/p17S5up2kYNwjsRFIRN qLl45a4ugtWjE/ZcUwdNte5KJqUHfmZFGKrEFynlIK9p2AIQ8spu22zzNQt7GXlVzP8= X-Gm-Gg: ASbGncsJylyg1eud+QQuQUso96++iC8ZHkyAF00jcZUZqGHJIxYLR3s67X5HNWiGqbX volHcfEJlRfmcvjrMZPpIdEx8WG3+XaEd9wy0kiG6Fk1sYPW4yHlccvhXkDoRoDiZ4qHcJceLl2 T295uQ3c67MAZo7uz1W4f+OHeuQsWjDlzP3+cT+SHfuGGydfiF8gpHySiO65dUNQlEg7+N7uV12 QTL23JIspdF43oQxDMO0sLNaEfWgRUQMTEaSs0ngnq3r6d6NQA2KzYAZA2r2YzLbk9CmYVBd+s3 BLqdn69G8dpufRcS1orUwlQcLaCFZcCkUystiOd3h75Ciwb8334v0hY8mq4rmKaH7TgFGkUz+VD HkJRjh4JUNYwv6PZPefpVmBENczZcZ5QEff1j+Mylvdf9snR9Vb7uC1U7BDb2l2e1pQOQzal4A+ j3yEO7EUmdcBVWho/VLwBD5ktINrmLGLk= X-Google-Smtp-Source: AGHT+IEIHAY0ieYvrIgM/ktEZhU04EJXyQVK6L5dD7sCe4rwbzMBqRPJwRy/+JJXUFQoMVJ2eeuntA== X-Received: by 2002:a05:600c:3b19:b0:46e:4246:c90d with SMTP id 5b1f17b1804b1-4778fe68378mr157000715e9.11.1763483306313; Tue, 18 Nov 2025 08:28:26 -0800 (PST) Received: from ho-tower-lan.lan ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9dea7fcsm20369125e9.8.2025.11.18.08.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 08:28:25 -0800 (PST) From: James Clark Date: Tue, 18 Nov 2025 16:28:02 +0000 Subject: [PATCH v5 12/13] coresight: Allow setting the timestamp interval Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-james-cs-syncfreq-v5-12-82efd7b1a751@linaro.org> References: <20251118-james-cs-syncfreq-v5-0-82efd7b1a751@linaro.org> In-Reply-To: <20251118-james-cs-syncfreq-v5-0-82efd7b1a751@linaro.org> To: Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan , Randy Dunlap Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Timestamps are currently emitted at the maximum rate possible, which is much too frequent for most use cases. Set the interval using the value from the timestamp field. Granular control is not required, so save space in the config by interpreting it as 2 ^ timestamp. And then 4 bits (0 - 15) is enough to set the interval to be larger than the existing SYNC timestamp interval. No sysfs mode support is needed for this attribute because counter generated timestamps are only configured for Perf mode. Reviewed-by: Leo Yan Tested-by: Leo Yan Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm-perf.h | 1 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 28 +++++++++++++++---= ---- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwt= racing/coresight/coresight-etm-perf.h index 24d929428633..128f80bb1443 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_ETM_PERF_H #define _CORESIGHT_ETM_PERF_H =20 +#include #include #include "coresight-priv.h" =20 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index cfd6d2b7bc50..a91981a651e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -651,7 +651,7 @@ static void etm4_enable_sysfs_smp_call(void *info) * +--------------+ * | * +------v-------+ - * | Counter x | (reload to 1 on underflow) + * | Counter x | (reload to 2 ^ timestamp on underflow) * +--------------+ * | * +------v--------------+ @@ -662,11 +662,25 @@ static void etm4_enable_sysfs_smp_call(void *info) * | Timestamp Generator | (timestamp on resource y) * +----------------------+ */ -static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, + struct perf_event_attr *attr) { int ctridx; int rselector; struct etmv4_config *config =3D &drvdata->config; + struct perf_event_attr max_timestamp =3D { + .ATTR_CFG_FLD_timestamp_CFG =3D U64_MAX, + }; + + /* timestamp may be 0 if deprecated_timestamp is used, so make min 1 */ + u8 ts_level =3D max(1, ATTR_CFG_GET_FLD(attr, timestamp)); + + /* + * Disable counter generated timestamps when timestamp =3D=3D MAX. Leave + * only SYNC timestamps. + */ + if (ts_level =3D=3D ATTR_CFG_GET_FLD(&max_timestamp, timestamp)) + return 0; =20 /* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) @@ -704,12 +718,8 @@ static int etm4_config_timestamp_event(struct etmv4_dr= vdata *drvdata) return -ENOSPC; } =20 - /* - * Initialise original and reload counter value to the smallest - * possible value in order to get as much precision as we can. - */ - config->cntr_val[ctridx] =3D 1; - config->cntrldvr[ctridx] =3D 1; + /* Initialise original and reload counter value. */ + config->cntr_val[ctridx] =3D config->cntrldvr[ctridx] =3D 1 << (ts_level = - 1); =20 /* * Trace Counter Control Register TRCCNTCTLRn @@ -799,7 +809,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, * order to correlate instructions executed on different CPUs * (CPU-wide trace scenarios). */ - ret =3D etm4_config_timestamp_event(drvdata); + ret =3D etm4_config_timestamp_event(drvdata, attr); =20 /* * No need to go further if timestamp intervals can't --=20 2.34.1