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[104.155.83.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53e7ae16sm32728666f8f.3.2025.11.18.05.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 05:56:19 -0800 (PST) From: Tudor Ambarus Date: Tue, 18 Nov 2025 13:56:09 +0000 Subject: [PATCH v2 2/7] soc: samsung: exynos-chipid: add google,gs101-otp support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-gs101-chipid-v2-2-e9f1e7460e35@linaro.org> References: <20251118-gs101-chipid-v2-0-e9f1e7460e35@linaro.org> In-Reply-To: <20251118-gs101-chipid-v2-0-e9f1e7460e35@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Srinivas Kandagatla Cc: Krzysztof Kozlowski , semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763474177; l=5916; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=p4ZObKdORDPs9HTtQcCqfM4Dt9UYXjFKiNvgoGM8eUg=; b=LgZlOadmjkQB7OdfDpvgPkVbF7pYjTLOuPDsVJbWNZP7uMGPhhsOLuzdntKh28msuquJ/TRVv i0HyigF3mGIALH+Q3JnnxQb5bAsptf+gjuhHFJ+IHOd9/Zjx4XEZM4w X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= GS101 is different (but also e850 and autov9 I assume) from the SoCs that are currently handled by the exynos-chipid driver because the chip ID info is part of the OTP registers. GS101 OTP has a clock, an interrupt line, a register space (that contains product and chip ID, TMU data, ASV, etc) and a 32Kbit memory space that can be read/program/locked with specific commands. On GS101 the "ChipID block" is just an abstraction, it's not a physical device. When the power-on sequence progresses, the OTP chipid values are loaded to the OTP registers. Add the GS101 chip ID support. The support is intentionally added in the exynos-chipid driver, and not in a dedicated Exynos OTP driver, because we estimate that there will not be any OTP consumers in the kernel other than the chip ID/SoC interface. The downstream GS101 drivers confirm this supposition. Signed-off-by: Tudor Ambarus --- drivers/soc/samsung/exynos-chipid.c | 86 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 75 insertions(+), 11 deletions(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exyn= os-chipid.c index d3b4b5508e0c808ee9f7b0039073ef57915d60fc..8904ffdaf9a6f6d069cc6af18a2= 4dd00a2780892 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -13,8 +13,11 @@ */ =20 #include +#include #include -#include +#include +#include +#include #include #include #include @@ -27,9 +30,11 @@ #include "exynos-asv.h" =20 struct exynos_chipid_variant { - unsigned int rev_reg; /* revision register offset */ + unsigned int main_rev_reg; /* main revision register offset */ + unsigned int sub_rev_reg; /* sub revision register offset */ unsigned int main_rev_shift; /* main revision offset in rev_reg */ unsigned int sub_rev_shift; /* sub revision offset in rev_reg */ + bool efuse; }; =20 struct exynos_chipid_info { @@ -68,6 +73,8 @@ static const struct exynos_soc_id { { "EXYNOS990", 0xE9830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, { "EXYNOSAUTOV920", 0x0A920000 }, + /* Compatible with: google,gs101-otp */ + { "GS101", 0x9845000 }, }; =20 static const char *product_id_to_soc_id(unsigned int product_id) @@ -92,18 +99,52 @@ static int exynos_chipid_get_chipid_info(struct regmap = *regmap, return ret; soc_info->product_id =3D val & EXYNOS_MASK; =20 - if (data->rev_reg !=3D EXYNOS_CHIPID_REG_PRO_ID) { - ret =3D regmap_read(regmap, data->rev_reg, &val); + if (data->sub_rev_reg =3D=3D EXYNOS_CHIPID_REG_PRO_ID) { + /* exynos4210 case */ + main_rev =3D (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK; + sub_rev =3D (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK; + } else { + unsigned int val2; + + ret =3D regmap_read(regmap, data->sub_rev_reg, &val2); if (ret < 0) return ret; + + if (data->main_rev_reg =3D=3D EXYNOS_CHIPID_REG_PRO_ID) + /* gs101 case */ + main_rev =3D (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK; + else + /* exynos850 case */ + main_rev =3D (val2 >> data->main_rev_shift) & EXYNOS_REV_PART_MASK; + + sub_rev =3D (val2 >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK; } - main_rev =3D (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK; - sub_rev =3D (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK; + soc_info->revision =3D (main_rev << EXYNOS_REV_PART_SHIFT) | sub_rev; =20 return 0; } =20 +static struct regmap *exynos_chipid_get_efuse_regmap(struct platform_devic= e *pdev) +{ + struct resource *res; + void __iomem *base; + + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return ERR_CAST(base); + + const struct regmap_config reg_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .use_relaxed_mmio =3D true, + .max_register =3D (resource_size(res) - reg_config.reg_stride), + }; + + return devm_regmap_init_mmio(&pdev->dev, base, ®_config); +} + static int exynos_chipid_probe(struct platform_device *pdev) { const struct exynos_chipid_variant *drv_data; @@ -119,9 +160,23 @@ static int exynos_chipid_probe(struct platform_device = *pdev) if (!drv_data) return -EINVAL; =20 - regmap =3D device_node_to_regmap(dev->of_node); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + if (drv_data->efuse) { + struct clk *clk; + + regmap =3D exynos_chipid_get_efuse_regmap(pdev); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to get efuse regmap\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get clock\n"); + } else { + regmap =3D device_node_to_regmap(dev->of_node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + } =20 ret =3D exynos_chipid_get_chipid_info(regmap, drv_data, &soc_info); if (ret < 0) @@ -177,19 +232,28 @@ static void exynos_chipid_remove(struct platform_devi= ce *pdev) } =20 static const struct exynos_chipid_variant exynos4210_chipid_drv_data =3D { - .rev_reg =3D 0x0, .main_rev_shift =3D 4, .sub_rev_shift =3D 0, }; =20 static const struct exynos_chipid_variant exynos850_chipid_drv_data =3D { - .rev_reg =3D 0x10, + .main_rev_reg =3D 0x10, + .sub_rev_reg =3D 0x10, .main_rev_shift =3D 20, .sub_rev_shift =3D 16, }; =20 +static const struct exynos_chipid_variant gs101_chipid_drv_data =3D { + .sub_rev_reg =3D 0x10, + .sub_rev_shift =3D 16, + .efuse =3D true, +}; + static const struct of_device_id exynos_chipid_of_device_ids[] =3D { { + .compatible =3D "google,gs101-otp", + .data =3D &gs101_chipid_drv_data, + }, { .compatible =3D "samsung,exynos4210-chipid", .data =3D &exynos4210_chipid_drv_data, }, { --=20 2.52.0.rc1.455.g30608eb744-goog