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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-595804056c9sm4078452e87.90.2025.11.18.06.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 06:51:46 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 18 Nov 2025 16:51:41 +0200 Subject: [PATCH RESEND 2/2] drm/msm/dpu: use full scale alpha in _dpu_crtc_setup_blend_cfg() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251118-dpu-rework-alpha-v1-2-293d39402b59@oss.qualcomm.com> References: <20251118-dpu-rework-alpha-v1-0-293d39402b59@oss.qualcomm.com> In-Reply-To: <20251118-dpu-rework-alpha-v1-0-293d39402b59@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3889; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=S/lbDFYMKbt7kFl+fZ/HQH44YveonZFk8GY1SvQjVQA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpHIf8IzhHGPLjJDCmR05+bDOeqtvwIVJbo3ALS 0P22UCukleJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaRyH/AAKCRCLPIo+Aiko 1fRoCACxkXSaH5+XAmMiiWTq3dU4KIgsDLBneucVx2XWIFkRGccgto5n1NEa6bpGrG1Gh8hALED hiYud6oxNSdvONQm3DrKPIV0chib34A7uE6KmhqLtPiAqejt7mteS4ml8DHBdb9UYSoOlBgqzRJ YQtZGyzsjAtXrSldT7H8CQCyGY1TWGB9qwgY7gkJlbxeOhwKlz76T1wD9RzFNmNsmY4JGliNctw 8iKd9/mKQrBkOw59cSi9Q5P7/LzK36LXu4vm6FhwHPAgDhTdEV8kGfaWnS+3+9GnLTdilG9q4iB kfgHsgdwWsH9BHauqrgOQvVWt+3cgvQncB4vKa6hN7s+yjQ6 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: jgVMBnVFWt92bqXofl0zpUxGUD9wZbh4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDExOSBTYWx0ZWRfXwx2JUZo+fuw0 ig3omnRU09qFYtmrZkcD7E80K5HZWqEw6loARPdFw75lT9BX0/RaSSZf6OlFX92M/3XO49hmzOj KNcgm01j66BMV8m2+zOprTvtF4jtM1bP7UXMQBAD8vs+4oGamqwZLKMUG0glkximrYISnpdm+Xj /Cy2PadJngTrf1iHzz2LiZZguPSci6NvamadMrAsHALEABa1BYFbJfx4IzHNCrfSEYrSjwcODp6 nznDKGKPuaJykEriX5jkEtaVzoCcap1FA1HWOeDivV3u4qLyCY/Gnz86jdEakDeCSKdZYfHXryi uYjPL+SC1gdqTCLpXRy+u8aaz0Vy8Ukr4Z5qrLoG+WQrNtJhLTw3+61GI6y/3kUXtVf6SHH1+mL WmiOVg7cE53LTav0T9vGctBIHPBE7g== X-Authority-Analysis: v=2.4 cv=BYTVE7t2 c=1 sm=1 tr=0 ts=691c8805 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=QNru2a5V_XkHKSg3hPgA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: jgVMBnVFWt92bqXofl0zpUxGUD9wZbh4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-18_01,2025-11-18_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180119 Both _dpu_crtc_setup_blend_cfg() and setup_blend_config_alpha() callbacks embed knowledge about platform's alpha range (8-bit or 10-bit). Make _dpu_crtc_setup_blend_cfg() use full 16-bit values for alpha and reduce alpha only in DPU-specific callbacks. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 +++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 10 ++++++---- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 651159e8731194d75b52c05158bfd1c9bad8b10c..a280c136104added1dbb2b432f1= 5680bc1d5bd36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -326,26 +326,20 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, { struct dpu_hw_mixer *lm =3D mixer->hw_lm; u32 blend_op; - u32 fg_alpha, bg_alpha, max_alpha; + u32 fg_alpha, bg_alpha; =20 - if (mdss_ver->core_major_ver < 12) { - max_alpha =3D 0xff; - fg_alpha =3D pstate->base.alpha >> 8; - } else { - max_alpha =3D 0x3ff; - fg_alpha =3D pstate->base.alpha >> 6; - } + fg_alpha =3D pstate->base.alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !format->alpha_enable) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST; - bg_alpha =3D max_alpha - fg_alpha; + bg_alpha =3D DRM_BLEND_ALPHA_OPAQUE - fg_alpha; } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D max_alpha) { + if (fg_alpha !=3D DRM_BLEND_ALPHA_OPAQUE) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -357,7 +351,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, /* coverage blending */ blend_op =3D DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D max_alpha) { + if (fg_alpha !=3D DRM_BLEND_ALPHA_OPAQUE) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index e8a76d5192c230fd64d748634ca8574a59aac02c..fb8c94fdb829be6f89bfcc6c5a8= 3fdbd27778bf2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -139,7 +139,8 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha= (struct dpu_hw_mixer *ctx if (WARN_ON(stage_off < 0)) return; =20 - const_alpha =3D (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); + const_alpha =3D ((bg_alpha >> 8) & 0xff) | + (((fg_alpha >> 8) & 0xff) << 16); DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } @@ -160,7 +161,8 @@ dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct = dpu_hw_mixer *ctx, if (WARN_ON(stage_off < 0)) return; =20 - const_alpha =3D (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + const_alpha =3D ((bg_alpha >> 6) & 0x3ff) | + (((fg_alpha >> 6) & 0x3ff) << 16); DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } @@ -178,8 +180,8 @@ static void dpu_hw_lm_setup_blend_config(struct dpu_hw_= mixer *ctx, if (WARN_ON(stage_off < 0)) return; =20 - DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); + DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha >> 8); + DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha >> 8); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 --=20 2.47.3