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Peter Anvin" Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Waiman Long Subject: [PATCH tip] x86/microcode/AMD: Read from MSR_AMD64_PATCH_LEVEL to get base_rev if not defined Date: Mon, 17 Nov 2025 14:15:27 -0500 Message-ID: <20251117191527.1487774-1-longman@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" AMD microcode is being handled inconsistenly depending on whether the CONFIG_MICROCODE_DBG is on or off. Currently, the MSR_AMD64_PATCH_LEVEL MSR is being read in get_patch_level() to retrieve microcode revision when CONFIG_MICROCODE_DBG is off, but cpuid_to_ucode_rev(bsp_cpuid_1_eax) is used to get the revision with CONFIG_MICROCODE_DBG on if microcode_rev[cpu] hasn't been defined yet. On a test Genoa system with a relatively new BIOS/firmware, get_patch_level() returns 0xa101100 with cpuid_to_ucode_rev(), but 0x0a101158 when reading from MSR_AMD64_PATCH_LEVEL. It does look like bsp_cpuid_1_eax doesn't contain the right microcode revision for microcode embedded in the BIOS/firmware. This is problematic as need_sha_check() may return an incorrect result. To fix the inconsistency and provide a more correct result, always read from the MSR in get_patch_level() to get the microcode revision number. Fixes: 43181a47263d ("x86/microcode: Add microcode loader debugging functio= nality") Signed-off-by: Waiman Long --- arch/x86/kernel/cpu/microcode/amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index 3821a985f4ff..561630c017e2 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -327,7 +327,7 @@ static u32 get_patch_level(void) =20 if (!microcode_rev[cpu]) { if (!base_rev) - base_rev =3D cpuid_to_ucode_rev(bsp_cpuid_1_eax); + native_rdmsr(MSR_AMD64_PATCH_LEVEL, base_rev, dummy); =20 microcode_rev[cpu] =3D base_rev; =20 --=20 2.51.1