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Enable stage-2 in case the host puts an STE in bypass or stage-1. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 75 ++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index f0075f9a0947..3e451cef937c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -371,6 +371,46 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_devic= e *smmu) return 0; } =20 +static void smmu_attach_stage_2(struct arm_smmu_ste *ste) +{ + unsigned long vttbr; + unsigned long ts, sl, ic, oc, sh, tg, ps; + unsigned long cfg; + struct io_pgtable_cfg *pgt_cfg =3D &idmap_pgtable->cfg; + + cfg =3D FIELD_GET(STRTAB_STE_0_CFG, ste->data[0]); + if (!FIELD_GET(STRTAB_STE_0_V, ste->data[0]) || + (cfg =3D=3D STRTAB_STE_0_CFG_ABORT)) + return; + /* S2 is not advertised, that should never be attempted. */ + if (WARN_ON(cfg =3D=3D STRTAB_STE_0_CFG_NESTED)) + return; + vttbr =3D pgt_cfg->arm_lpae_s2_cfg.vttbr; + ps =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.ps; + tg =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.tg; + sh =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.sh; + oc =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.orgn; + ic =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.irgn; + sl =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.sl; + ts =3D pgt_cfg->arm_lpae_s2_cfg.vtcr.tsz; + + ste->data[1] |=3D FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOM= ING); + /* The host shouldn't write dwords 2 and 3, overwrite them. */ + ste->data[2] =3D FIELD_PREP(STRTAB_STE_2_VTCR, + FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, ps) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, tg) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, sh) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, oc) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, ic) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, sl) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, ts)) | + FIELD_PREP(STRTAB_STE_2_S2VMID, 0) | + STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2R; + ste->data[3] =3D vttbr & STRTAB_STE_3_S2TTB_MASK; + /* Convert S1 =3D> nested and bypass =3D> S2 */ + ste->data[0] |=3D FIELD_PREP(STRTAB_STE_0_CFG, cfg | BIT(1)); +} + /* Get an STE for a stream table base. */ static struct arm_smmu_ste *smmu_get_ste_ptr(struct hyp_arm_smmu_v3_device= *smmu, u32 sid, u64 *strtab) @@ -426,6 +466,15 @@ static void smmu_reshadow_ste(struct hyp_arm_smmu_v3_d= evice *smmu, u32 sid, bool u64 *hyp_ste_base =3D strtab_hyp_base(smmu); struct arm_smmu_ste *host_ste_ptr =3D smmu_get_ste_ptr(smmu, sid, host_st= e_base); struct arm_smmu_ste *hyp_ste_ptr =3D smmu_get_ste_ptr(smmu, sid, hyp_ste_= base); + struct arm_smmu_ste target =3D {}; + struct arm_smmu_cmdq_ent cfgi_cmd =3D { + .opcode =3D CMDQ_OP_CFGI_STE, + .cfgi =3D { + .sid =3D sid, + .leaf =3D true, + }, + }; + int i; =20 /* * Linux only uses leaf =3D 1, when leaf is 0, we need to verify that this @@ -441,8 +490,32 @@ static void smmu_reshadow_ste(struct hyp_arm_smmu_v3_d= evice *smmu, u32 sid, bool hyp_ste_ptr =3D smmu_get_ste_ptr(smmu, sid, hyp_ste_base); } =20 - smmu_copy_from_host(smmu, hyp_ste_ptr->data, host_ste_ptr->data, + smmu_copy_from_host(smmu, target.data, host_ste_ptr->data, STRTAB_STE_DWORDS << 3); + /* + * Typically, STE update is done as the following + * 1- Write last 7 dwords, while STE is invalid + * 2- CFGI + * 3- Write first dword, making STE valid + * 4- CFGI + * As the SMMU MUST at least load 64 bits atomically + * that gurantees that there is no race between writing + * the STE and the CFGI where the SMMU observes parts + * of the STE. + * In the shadow we update the STE to enable nested translation, + * which requires updating first 4 dwords. + * That is only done if the STE is valid and not in abort. + * Which means it happens at step 4) + * So we need to also write the last 7 dwords and send CFGI + * before writing the first dword. + * There is no need for last CFGI as it's done next. + */ + smmu_attach_stage_2(&target); + for (i =3D 1; i < STRTAB_STE_DWORDS; i++) + WRITE_ONCE(hyp_ste_ptr->data[i], target.data[i]); + + WARN_ON(smmu_send_cmd(smmu, &cfgi_cmd)); + WRITE_ONCE(hyp_ste_ptr->data[0], target.data[0]); } =20 static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu) --=20 2.52.0.rc1.455.g30608eb744-goog