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AJvYcCWiPHmu8VNlAeyWab2vOZA4j7Hg8LmKlv7VrmbQqWnLR65cq3VF5Gm5x5vJePeAXYTEMNtmLDPb+BjI90Y=@vger.kernel.org X-Gm-Message-State: AOJu0YwYAOAFuladNGcdTzos3imu96UmwfBA28MxSDT3HrfPKONRVdv1 KzMUY5RU6dPaHnNm3KHL/WZk/RCeyM77+iZLOPs1yZcw5zagvFQkNDIR6B5YMclllUe9qqdxkh1 cn0Dd/VTPNCFoRw== X-Google-Smtp-Source: AGHT+IHCWbQlr8o940tPX5ysnGCiRUYmATJoia86/TFJSTwquzFFs3l4nOHlPBVKTiqXidY7DwnVkD6YGitCIA== X-Received: from wrio1.prod.google.com ([2002:a5d:6481:0:b0:429:bf18:9f1]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:230d:b0:42b:2e94:5a8f with SMTP id ffacd0b85a97d-42b5939dc13mr12310824f8f.52.1763405324058; Mon, 17 Nov 2025 10:48:44 -0800 (PST) Date: Mon, 17 Nov 2025 18:48:05 +0000 In-Reply-To: <20251117184815.1027271-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251117184815.1027271-1-smostafa@google.com> X-Mailer: git-send-email 2.52.0.rc1.455.g30608eb744-goog Message-ID: <20251117184815.1027271-19-smostafa@google.com> Subject: [PATCH v5 18/27] iommu/arm-smmu-v3-kvm: Add MMIO emulation From: Mostafa Saleh To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jean-philippe@linaro.org, jgg@ziepe.ca, praan@google.com, danielmentz@google.com, mark.rutland@arm.com, qperret@google.com, tabba@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment most registers are just passthrough, then in the next patches CMDQ/STE emulation will be added which inserts logic to some register access. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 126 ++++++++++++++++++ .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 10 ++ 2 files changed, 136 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index e45b4e50b1e4..f0dae94daf89 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include "arm_smmu_v3.h" #include "../arm-smmu-v3.h" @@ -115,6 +116,7 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_devi= ce *smmu) ret =3D smmu_probe(smmu); if (ret) goto out_ret; + hyp_spin_lock_init(&smmu->lock); return 0; out_ret: smmu_deinit_device(smmu); @@ -140,6 +142,8 @@ static int smmu_init(void) goto out_reclaim_smmu; } =20 + BUILD_BUG_ON(sizeof(hyp_spinlock_t) !=3D sizeof(u32)); + return 0; =20 out_reclaim_smmu: @@ -150,6 +154,127 @@ static int smmu_init(void) return ret; } =20 +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, + struct user_pt_regs *regs, + u64 esr, u32 off) +{ + bool is_write =3D esr & ESR_ELx_WNR; + unsigned int len =3D BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); + int rd =3D (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; + const u64 read_write =3D -1ULL; + const u64 no_access =3D 0; + u64 mask =3D no_access; + const u64 read_only =3D is_write ? no_access : read_write; + u64 val =3D regs->regs[rd]; + + switch (off) { + case ARM_SMMU_IDR0: + /* Clear stage-2 support, hide MSI to avoid write back to cmdq */ + mask =3D read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP); + WARN_ON(len !=3D sizeof(u32)); + break; + /* Passthrough the register access for bisectiblity, handled later */ + case ARM_SMMU_CMDQ_BASE: + case ARM_SMMU_CMDQ_PROD: + case ARM_SMMU_CMDQ_CONS: + case ARM_SMMU_STRTAB_BASE: + case ARM_SMMU_STRTAB_BASE_CFG: + case ARM_SMMU_GBPA: + mask =3D read_write; + break; + case ARM_SMMU_CR0: + mask =3D read_write; + WARN_ON(len !=3D sizeof(u32)); + break; + case ARM_SMMU_CR1: { + /* Based on Linux implementation */ + u64 cr2_template =3D FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); + /* Don't mess with shareability/cacheability. */ + if (is_write) + WARN_ON(val !=3D cr2_template); + mask =3D read_write; + WARN_ON(len !=3D sizeof(u32)); + break; + } + /* + * These should be safe, just enforce RO or RW and size according to arch= itecture. + * There are some other registers that are not used by Linux as IDR2, IDR4 + * that won't be allowed. + */ + case ARM_SMMU_EVTQ_PROD + SZ_64K: + case ARM_SMMU_EVTQ_CONS + SZ_64K: + case ARM_SMMU_EVTQ_IRQ_CFG1: + case ARM_SMMU_EVTQ_IRQ_CFG2: + case ARM_SMMU_PRIQ_PROD + SZ_64K: + case ARM_SMMU_PRIQ_CONS + SZ_64K: + case ARM_SMMU_PRIQ_IRQ_CFG1: + case ARM_SMMU_PRIQ_IRQ_CFG2: + case ARM_SMMU_GERRORN: + case ARM_SMMU_GERROR_IRQ_CFG1: + case ARM_SMMU_GERROR_IRQ_CFG2: + case ARM_SMMU_IRQ_CTRLACK: + case ARM_SMMU_IRQ_CTRL: + case ARM_SMMU_CR0ACK: + case ARM_SMMU_CR2: + /* These are 32 bit registers. */ + WARN_ON(len !=3D sizeof(u32)); + fallthrough; + case ARM_SMMU_EVTQ_BASE: + case ARM_SMMU_EVTQ_IRQ_CFG0: + case ARM_SMMU_PRIQ_BASE: + case ARM_SMMU_PRIQ_IRQ_CFG0: + case ARM_SMMU_GERROR_IRQ_CFG0: + mask =3D read_write; + break; + case ARM_SMMU_IIDR: + case ARM_SMMU_IDR5: + case ARM_SMMU_IDR3: + case ARM_SMMU_IDR1: + case ARM_SMMU_GERROR: + WARN_ON(len !=3D sizeof(u32)); + mask =3D read_only; + }; + + if (WARN_ON(!mask)) + goto out_ret; + + if (is_write) { + if (len =3D=3D sizeof(u64)) + writeq_relaxed(regs->regs[rd] & mask, smmu->base + off); + else + writel_relaxed(regs->regs[rd] & mask, smmu->base + off); + } else { + if (len =3D=3D sizeof(u64)) + regs->regs[rd] =3D readq_relaxed(smmu->base + off) & mask; + else + regs->regs[rd] =3D readl_relaxed(smmu->base + off) & mask; + } + +out_ret: + return true; +} + +static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr) +{ + struct hyp_arm_smmu_v3_device *smmu; + bool ret; + + for_each_smmu(smmu) { + if (addr < smmu->mmio_addr || addr >=3D smmu->mmio_addr + smmu->mmio_siz= e) + continue; + hyp_spin_lock(&smmu->lock); + ret =3D smmu_dabt_device(smmu, regs, esr, addr - smmu->mmio_addr); + hyp_spin_unlock(&smmu->lock); + return ret; + } + return false; +} + static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int= prot) { } @@ -158,4 +283,5 @@ static void smmu_host_stage2_idmap(phys_addr_t start, p= hys_addr_t end, int prot) struct kvm_iommu_ops smmu_ops =3D { .init =3D smmu_init, .host_stage2_idmap =3D smmu_host_stage2_idmap, + .dabt_handler =3D smmu_dabt_handler, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index 3550fa695539..dfeaed728982 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -4,6 +4,10 @@ =20 #include =20 +#ifdef __KVM_NVHE_HYPERVISOR__ +#include +#endif + /* * Parameters from the trusted host: * @mmio_addr base address of the SMMU registers @@ -16,6 +20,7 @@ * @oas PA size * @pgsize_bitmap Supported page sizes * @sid_bits Max number of SID bits supported + * @lock Lock to protect SMMU */ struct hyp_arm_smmu_v3_device { phys_addr_t mmio_addr; @@ -26,6 +31,11 @@ struct hyp_arm_smmu_v3_device { unsigned long oas; unsigned long pgsize_bitmap; unsigned int sid_bits; +#ifdef __KVM_NVHE_HYPERVISOR__ + hyp_spinlock_t lock; +#else + u32 lock; +#endif }; =20 extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); --=20 2.52.0.rc1.455.g30608eb744-goog