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Mon, 17 Nov 2025 10:10:35 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 1/5] PCI: rockchip: Fix Link Control register offset and enable ASPM/CLKREQ Date: Mon, 17 Nov 2025 23:40:09 +0530 Message-ID: <20251117181023.482138-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per the RK3399 TRM (Part 2, 17.6.6.1.31), the Link Control register (RC_CONFIG_LC) resides at an offset of 0xd0 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes correct the register offset to use PCIE_RC_CONFIG_LC (0xd0) to configure link control. Additionally, this commit explicitly enables ASPM (Active State Power Management) control and the CLKREQ# (Clock Request) mechanism as part of the Link Control register programming when enabling bandwidth notifications. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 15 ++++++++------- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index ee1822ca01db..f0de5b2590c4 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -32,18 +32,19 @@ static void rockchip_pcie_enable_bw_int(struct rockchip= _pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); - status |=3D (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCT= L); + status |=3D (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE | + PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCT= L); status |=3D (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockch= ip) @@ -306,9 +307,9 @@ static int rockchip_pcie_host_init_port(struct rockchip= _pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); =20 /* Set RC's RCB to 128 */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCT= L); status |=3D PCI_EXP_LNKCTL_RCB; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LC + PCI_EXP_LNKCTL); =20 /* Enable Gen1 training */ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 3e82a69b9c00..5d8a3ae38599 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -157,6 +157,7 @@ #define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) +#define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) --=20 2.50.1 From nobody Mon Feb 9 07:19:39 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2871C31196F for ; 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Mon, 17 Nov 2025 10:10:42 -0800 (PST) Received: from rockpi-5b ([45.112.0.172]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm147237955ad.32.2025.11.17.10.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 10:10:41 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 2/5] PCI: rockchip: Fix Device Control register offset for Max payload size Date: Mon, 17 Nov 2025 23:40:10 +0530 Message-ID: <20251117181023.482138-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per 17.6.6.1.29 PCI Express Device Capabilities Register (PCIE_RC_CONFIG_DC) reside at offset 0xc8 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes corrects the register offset to use PCIE_RC_CONFIG_DC (0xc8) to configure Max Payload Size. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++-- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index f0de5b2590c4..d51780f4a254 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -382,10 +382,10 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP= ); } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCT= L); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DC + PCI_EXP_DEVCT= L); status &=3D ~PCI_EXP_DEVCTL_PAYLOAD; status |=3D PCI_EXP_DEVCTL_PAYLOAD_256B; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DC + PCI_EXP_DEVCTL); =20 return 0; err_power_off_phy: diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 5d8a3ae38599..c0ec6c32ea16 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -157,6 +157,7 @@ #define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) +#define PCIE_RC_CONFIG_DC (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) --=20 2.50.1 From nobody Mon Feb 9 07:19:39 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01F1330B520 for ; Mon, 17 Nov 2025 18:10:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 17 Nov 2025 10:10:48 -0800 (PST) Received: from rockpi-5b ([45.112.0.172]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm147237955ad.32.2025.11.17.10.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 10:10:47 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 3/5] PCI: rockchip: Fix Slot Capability Register offset for slot power limit Date: Mon, 17 Nov 2025 23:40:11 +0530 Message-ID: <20251117181023.482138-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per 17.6.6.1.32 Slot Capability Register (PCIE_RC_CONFIG_SR) reside at offset 0xd4 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes corrects the register offset to use PCIE_RC_CONFIG_SR (0xd4) to configure Slot Power Limit value. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++-- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index d51780f4a254..d77403bbb81d 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -271,10 +271,10 @@ static void rockchip_pcie_set_power_limit(struct rock= chip_pcie *rockchip) power =3D power / 10; } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCA= P); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_SR + PCI_EXP_DEVCA= P); status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_SR + PCI_EXP_DEVCAP); } =20 /** diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index c0ec6c32ea16..4ba07ff3a3cf 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -159,6 +159,7 @@ #define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) #define PCIE_RC_CONFIG_DC (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_SR (PCIE_RC_CONFIG_BASE + 0xd4) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) --=20 2.50.1 From nobody Mon Feb 9 07:19:39 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE8A3148DD for ; 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Mon, 17 Nov 2025 10:10:54 -0800 (PST) Received: from rockpi-5b ([45.112.0.172]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm147237955ad.32.2025.11.17.10.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 10:10:53 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 4/5] PCI: rockchip: Fix Link Control and Status Register 2 for target link speed Date: Mon, 17 Nov 2025 23:40:12 +0530 Message-ID: <20251117181023.482138-5-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per 17.6.4.5.11 Link Control and Status Register 2 (PCIE_RC_CONFIG_LC2) reside at offset 0xf0 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes corrects the register offset to use PCIE_RC_CONFIG_LC2 (0xf0) to configure target like speed. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++-- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index d77403bbb81d..b3c9b9cbeb8d 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -334,10 +334,10 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) * Enable retrain for gen2. This should be configured only after * gen1 finished. */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL2); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LC2 + PCI_EXP_LNK= CTL2); status &=3D ~PCI_EXP_LNKCTL2_TLS; status |=3D PCI_EXP_LNKCTL2_TLS_5_0GT; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= 2); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LC2 + PCI_EXP_LNKCT= L2); status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); status |=3D PCI_EXP_LNKCTL_RL; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 4ba07ff3a3cf..a83ce7787466 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -160,6 +160,7 @@ #define PCIE_RC_CONFIG_DC (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_SR (PCIE_RC_CONFIG_BASE + 0xd4) +#define PCIE_RC_CONFIG_LC2 (PCIE_RC_CONFIG_BASE + 0xf0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) --=20 2.50.1 From nobody Mon Feb 9 07:19:39 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74418273D84 for ; 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Mon, 17 Nov 2025 10:10:59 -0800 (PST) Received: from rockpi-5b ([45.112.0.172]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c245ecdsm147237955ad.32.2025.11.17.10.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 10:10:59 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 5/5] PCI: rockchip: Fix Linkwidth Control Register offset for Retrain Link Date: Mon, 17 Nov 2025 23:40:13 +0530 Message-ID: <20251117181023.482138-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per 17.6.7.1.21 Linkwidth Control Register (PCIE_RC_CONFIG_LWC) reside at offset 0x50 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes corrects the register offset to use PCIE_RC_CONFIG_LWC (0x50) to configure Retrain link. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++-- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index b3c9b9cbeb8d..aae3def64bf0 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -338,9 +338,9 @@ static int rockchip_pcie_host_init_port(struct rockchip= _pcie *rockchip) status &=3D ~PCI_EXP_LNKCTL2_TLS; status |=3D PCI_EXP_LNKCTL2_TLS_5_0GT; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LC2 + PCI_EXP_LNKCT= L2); - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LWC + PCI_EXP_LNK= CTL); status |=3D PCI_EXP_LNKCTL_RL; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LWC + PCI_EXP_LNKCT= L); =20 err =3D readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, status, PCIE_LINK_IS_GEN2(status), 20, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index a83ce7787466..5bcaef7bba4c 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -160,6 +160,7 @@ #define PCIE_RC_CONFIG_DC (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_SR (PCIE_RC_CONFIG_BASE + 0xd4) +#define PCIE_RC_CONFIG_LWC (PCIE_RC_CONFIG_BASE + 0x50) #define PCIE_RC_CONFIG_LC2 (PCIE_RC_CONFIG_BASE + 0xf0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) --=20 2.50.1