From nobody Mon Feb 9 19:53:44 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 40B9232E13F; Mon, 17 Nov 2025 17:01:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763398911; cv=none; b=tsUnZ8r7NlhD8trYjQKASFQiP+gUA33X62Wp+v3XnbuvICPp1W7WT2Kxcqu2fE8LPcmxK5ROoQkVQzre+of7ogHQ5NacPm0ErQ7PGojHmOTSwRMs7Q/mZACNL22OsGHeiDN2mCBwskqtZ5JdXrlAX1rbz3N7jz59305dzTMCWY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763398911; c=relaxed/simple; bh=vx5WZxzySbc/2dj79e83pQbECQQKNIxngl45D6s2AlU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HJQ5umHciBDGorghHPNI9mpaL/etVOlZtE5ORQdPgHiE7ywLwQ8K6fNTERaMlYLIxSttCy9TTav4XOgI8OrrQAg6tQqFpkn55/eCwOgpDTftnQc871XOaCi4R9cvIkNG9euYTZBuUTZJhYJVen/oT4PhnkvMRn2etBW3vus+xWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C5C3FEC; Mon, 17 Nov 2025 09:01:42 -0800 (PST) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BE4143F66E; Mon, 17 Nov 2025 09:01:44 -0800 (PST) From: Ben Horgan To: james.morse@arm.com Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com, baolin.wang@linux.alibaba.com, bobo.shaobowang@huawei.com, carl@os.amperecomputing.com, catalin.marinas@arm.com, dakr@kernel.org, dave.martin@arm.com, david@redhat.com, dfustini@baylibre.com, fenghuay@nvidia.com, gregkh@linuxfoundation.org, gshan@redhat.com, guohanjun@huawei.com, jeremy.linton@arm.com, jonathan.cameron@huawei.com, kobak@nvidia.com, lcherian@marvell.com, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, lpieralisi@kernel.org, peternewman@google.com, quic_jiles@quicinc.com, rafael@kernel.org, robh@kernel.org, rohit.mathew@arm.com, scott@os.amperecomputing.com, sdonthineni@nvidia.com, sudeep.holla@arm.com, tan.shaopeng@fujitsu.com, will@kernel.org, xhao@linux.alibaba.com, Shaopeng Tan , Zeng Heng , Ben Horgan Subject: [PATCH v5 15/34] arm_mpam: Add helpers for managing the locking around the mon_sel registers Date: Mon, 17 Nov 2025 16:59:54 +0000 Message-ID: <20251117170014.4113754-16-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251117170014.4113754-1-ben.horgan@arm.com> References: <20251117170014.4113754-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Morse The MSC MON_SEL register needs to be accessed from hardirq for the overflow interrupt, and when taking an IPI to access these registers on platforms where MSC are not accessible from every CPU. This makes an irqsave spinlock the obvious lock to protect these registers. On systems with SCMI or PCC mailboxes it must be able to sleep, meaning a mutex must be used. The SCMI or PCC platforms can't support an overflow interrupt, and can't access the registers from hardirq context. Clearly these two can't exist for one MSC at the same time. Add helpers for the MON_SEL locking. For now, use a irqsave spinlock and only support 'real' MMIO platforms. In the future this lock will be split in two allowing SCMI/PCC platforms to take a mutex. Because there are contexts where the SCMI/PCC platforms can't make an access, mpam_mon_sel_lock() needs to be able to fail. Do this now, so that all the error handling on these paths is present. This allows the relevant paths to fail if they are needed on a platform where this isn't possible, instead of having to make explicit checks of the interface type. Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan Reviewed-by: Shaopeng Tan Reviewed-by: Fenghua Yu Tested-by: Fenghua Yu Tested-by: Shaopeng Tan Tested-by: Peter Newman Tested-by: Carl Worth Tested-by: Gavin Shan Tested-by: Zeng Heng Signed-off-by: James Morse Signed-off-by: Ben Horgan --- Changes since v3: use devm_mutex_init() include tiying stray comma (Jonathan) --- drivers/resctrl/mpam_devices.c | 2 ++ drivers/resctrl/mpam_internal.h | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index ac1c770cea35..b0374dea1727 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -740,6 +741,7 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct pl= atform_device *pdev) if (err) return ERR_PTR(err); =20 + mpam_mon_sel_lock_init(msc); msc->id =3D pdev->id; msc->pdev =3D pdev; INIT_LIST_HEAD_RCU(&msc->all_msc_list); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 768a58a3ab27..b62ee55e1ed5 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -10,6 +10,7 @@ #include #include #include +#include #include =20 #define MPAM_MSC_MAX_NUM_RIS 16 @@ -65,12 +66,50 @@ struct mpam_msc { */ struct mutex part_sel_lock; =20 + /* + * mon_sel_lock protects access to the MSC hardware registers that are + * affected by MPAMCFG_MON_SEL, and the mbwu_state. + * Access to mon_sel is needed from both process and interrupt contexts, + * but is complicated by firmware-backed platforms that can't make any + * access unless they can sleep. + * Always use the mpam_mon_sel_lock() helpers. + * Accesses to mon_sel need to be able to fail if they occur in the wrong + * context. + * If needed, take msc->probe_lock first. + */ + raw_spinlock_t _mon_sel_lock; + unsigned long _mon_sel_flags; + void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; =20 struct mpam_garbage garbage; }; =20 +/* Returning false here means accesses to mon_sel must fail and report an = error. */ +static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) +{ + WARN_ON_ONCE(msc->iface !=3D MPAM_IFACE_MMIO); + + raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); + return true; +} + +static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) +{ + raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); +} + +static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) +{ + lockdep_assert_held_once(&msc->_mon_sel_lock); +} + +static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) +{ + raw_spin_lock_init(&msc->_mon_sel_lock); +} + struct mpam_class { /* mpam_components in this class */ struct list_head components; --=20 2.43.0