From nobody Tue Dec 2 02:59:32 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674093346AA; Mon, 17 Nov 2025 13:49:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763387368; cv=none; b=YninR+VENHeFSevS7UEn57QIbRapkFITBDwECzEeqGfmhX09I0GytQ9qhNpi/w0v/31Dv1AvQ/qjOlXvRmMY8XbbYRS0EnAkj5ecNxIiGej/XIWQZKF0+FOkH1f1Icg0FHBeA9d+gJR/hkR+KhYkdZOpZSMuxgDdeo0/Lcbc0xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763387368; c=relaxed/simple; bh=b2oHtswzOIbKJMZuKbKUfiuFrIl0WBhel79tguh0j1o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fNa26RQ47aP++VMNp2l05Stcm2TybOuDcRVmWTNlQRxjzmvuBuEAaBQVpejZkrKCCG0YKLpHanLaTJwq8Gx7KURa9GWdrjapO5zkWSbnxxj0k0isRIwU+tjSAXSZ08YZwq/EuUNTzFA096I0ax8c+Jz9EgrSlMSJFdL+igcax7g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Jx25tXO2; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Jx25tXO2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763387367; x=1794923367; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b2oHtswzOIbKJMZuKbKUfiuFrIl0WBhel79tguh0j1o=; b=Jx25tXO25tWevc67hKGJpPHLSc0DUjf23NDiZWRxPuKX01PYrRcqy+9C rzC1M5Wy4wS606eVkMvAjaUn/OpcLfzRz1ThUiSQWZpqLU6Gt8EhIAs6E 965w1g22RDPiOv6UwMkLZ+IIYeLcK3aGAr4P1PPt8nsC3HIZhX9VPXOZi gA1xpVchaO1DFt8eY7sFb4wJ1uTwoXV76luecuTztqJ2UxlHnYw0FlUh7 AxxoCKGZj++S8v6IoUvCO3zII6xBZJh9EWSjvWGFtNRv03NnwzpAN+5tP ug17emBQtPGEf5Unb0Mnedg2JZsaDOPg8lMtFnI9TP53qTkqmVELAwBkv A==; X-CSE-ConnectionGUID: UNLb1qawTfyUrfZKV31KIw== X-CSE-MsgGUID: dPDOeJTFR06z/zd5Bn5xuA== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="65266959" X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="65266959" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 05:49:26 -0800 X-CSE-ConnectionGUID: u2oNzo1hS12ze9JABI5ThA== X-CSE-MsgGUID: ZDvWQzTIT+i0qFXTPUoCPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="190684006" Received: from irvmail002.ir.intel.com ([10.43.11.120]) by fmviesa008.fm.intel.com with ESMTP; 17 Nov 2025 05:49:20 -0800 Received: from mglak.igk.intel.com (mglak.igk.intel.com [10.237.112.146]) by irvmail002.ir.intel.com (Postfix) with ESMTP id 520AD37E3A; Mon, 17 Nov 2025 13:49:18 +0000 (GMT) From: Larysa Zaremba To: intel-wired-lan@lists.osuosl.org, Tony Nguyen Cc: aleksander.lobakin@intel.com, sridhar.samudrala@intel.com, "Singhai, Anjali" , Michal Swiatkowski , Larysa Zaremba , "Fijalkowski, Maciej" , Emil Tantilov , Madhu Chittim , Josh Hay , "Keller, Jacob E" , jayaprakash.shanmugam@intel.com, natalia.wochtman@intel.com, Jiri Pirko , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Richard Cochran , Przemek Kitszel , Andrew Lunn , netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Phani R Burra Subject: [PATCH iwl-next v5 03/15] libie: add PCI device initialization helpers to libie Date: Mon, 17 Nov 2025 14:48:43 +0100 Message-ID: <20251117134912.18566-4-larysa.zaremba@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20251117134912.18566-1-larysa.zaremba@intel.com> References: <20251117134912.18566-1-larysa.zaremba@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Phani R Burra Add memory related support functions for drivers to access MMIO space and allocate/free dma buffers. Reviewed-by: Maciej Fijalkowski Signed-off-by: Phani R Burra Co-developed-by: Victor Raj Signed-off-by: Victor Raj Co-developed-by: Sridhar Samudrala Signed-off-by: Sridhar Samudrala Co-developed-by: Pavan Kumar Linga Signed-off-by: Pavan Kumar Linga Co-developed-by: Larysa Zaremba Signed-off-by: Larysa Zaremba --- drivers/net/ethernet/intel/libie/Kconfig | 6 + drivers/net/ethernet/intel/libie/Makefile | 4 + drivers/net/ethernet/intel/libie/pci.c | 187 ++++++++++++++++++++++ include/linux/intel/libie/pci.h | 56 +++++++ 4 files changed, 253 insertions(+) create mode 100644 drivers/net/ethernet/intel/libie/pci.c create mode 100644 include/linux/intel/libie/pci.h diff --git a/drivers/net/ethernet/intel/libie/Kconfig b/drivers/net/etherne= t/intel/libie/Kconfig index 70831c7e336e..500a95c944a8 100644 --- a/drivers/net/ethernet/intel/libie/Kconfig +++ b/drivers/net/ethernet/intel/libie/Kconfig @@ -23,3 +23,9 @@ config LIBIE_FWLOG for it. Firmware logging is using admin queue interface to communicate with the device. Debugfs is a user interface used to config logging and dump all collected logs. + +config LIBIE_PCI + tristate + help + Helper functions for management of PCI resources belonging + to networking devices. diff --git a/drivers/net/ethernet/intel/libie/Makefile b/drivers/net/ethern= et/intel/libie/Makefile index db57fc6780ea..a28509cb9086 100644 --- a/drivers/net/ethernet/intel/libie/Makefile +++ b/drivers/net/ethernet/intel/libie/Makefile @@ -12,3 +12,7 @@ libie_adminq-y :=3D adminq.o obj-$(CONFIG_LIBIE_FWLOG) +=3D libie_fwlog.o =20 libie_fwlog-y :=3D fwlog.o + +obj-$(CONFIG_LIBIE_PCI) +=3D libie_pci.o + +libie_pci-y :=3D pci.o diff --git a/drivers/net/ethernet/intel/libie/pci.c b/drivers/net/ethernet/= intel/libie/pci.c new file mode 100644 index 000000000000..50d8d296476d --- /dev/null +++ b/drivers/net/ethernet/intel/libie/pci.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2025 Intel Corporation */ + +#include + +/** + * libie_find_mmio_region - find if MMIO region is present in the list + * @mmio_list: list that contains MMIO region info + * @offset: MMIO region start offset + * @bar_idx: BAR index where the offset to search + * + * Return: MMIO region pointer or NULL if the region info is not present. + */ +static struct libie_pci_mmio_region * +libie_find_mmio_region(const struct list_head *mmio_list, + resource_size_t offset, int bar_idx) +{ + struct libie_pci_mmio_region *mr; + + list_for_each_entry(mr, mmio_list, list) + if (mr->bar_idx =3D=3D bar_idx && mr->offset =3D=3D offset) + return mr; + + return NULL; +} + +/** + * __libie_pci_get_mmio_addr - get the MMIO virtual address + * @mmio_info: contains list of MMIO regions + * @offset: register offset of find + * @num_args: number of additional arguments present + * + * This function finds the virtual address of a register offset by iterati= ng + * through the non-linear MMIO regions that are mapped by the driver. + * + * Return: valid MMIO virtual address or NULL. + */ +void __iomem *__libie_pci_get_mmio_addr(struct libie_mmio_info *mmio_info, + resource_size_t offset, + int num_args, ...) +{ + struct libie_pci_mmio_region *mr; + int bar_idx =3D 0; + va_list args; + + if (num_args) { + va_start(args, num_args); + bar_idx =3D va_arg(args, int); + va_end(args); + } + + list_for_each_entry(mr, &mmio_info->mmio_list, list) + if (bar_idx =3D=3D mr->bar_idx && offset >=3D mr->offset && + offset < mr->offset + mr->size) { + offset -=3D mr->offset; + + return mr->addr + offset; + } + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(__libie_pci_get_mmio_addr, "LIBIE_PCI"); + +/** + * __libie_pci_map_mmio_region - map PCI device MMIO region + * @mmio_info: struct to store the mapped MMIO region + * @offset: MMIO region start offset + * @size: MMIO region size + * @num_args: number of additional arguments present + * + * Return: true on success, false on memory map failure. + */ +bool __libie_pci_map_mmio_region(struct libie_mmio_info *mmio_info, + resource_size_t offset, + resource_size_t size, int num_args, ...) +{ + struct pci_dev *pdev =3D mmio_info->pdev; + struct libie_pci_mmio_region *mr; + resource_size_t pa; + void __iomem *va; + int bar_idx =3D 0; + va_list args; + + if (num_args) { + va_start(args, num_args); + bar_idx =3D va_arg(args, int); + va_end(args); + } + + mr =3D libie_find_mmio_region(&mmio_info->mmio_list, offset, bar_idx); + if (mr) { + pci_warn(pdev, "Mapping of BAR%u with offset %llu already exists\n", + bar_idx, (unsigned long long)offset); + return true; + } + + pa =3D pci_resource_start(pdev, bar_idx) + offset; + va =3D ioremap(pa, size); + if (!va) { + pci_err(pdev, "Failed to map BAR%u region\n", bar_idx); + return false; + } + + mr =3D kvzalloc(sizeof(*mr), GFP_KERNEL); + if (!mr) { + iounmap(va); + return false; + } + + mr->addr =3D va; + mr->offset =3D offset; + mr->size =3D size; + mr->bar_idx =3D bar_idx; + + list_add_tail(&mr->list, &mmio_info->mmio_list); + + return true; +} +EXPORT_SYMBOL_NS_GPL(__libie_pci_map_mmio_region, "LIBIE_PCI"); + +/** + * libie_pci_unmap_fltr_regs - unmap selected PCI device MMIO regions + * @mmio_info: contains list of MMIO regions to unmap + * @fltr: returns true, if region is to be unmapped + */ +void libie_pci_unmap_fltr_regs(struct libie_mmio_info *mmio_info, + bool (*fltr)(struct libie_mmio_info *mmio_info, + struct libie_pci_mmio_region *reg)) +{ + struct libie_pci_mmio_region *mr, *tmp; + + list_for_each_entry_safe(mr, tmp, &mmio_info->mmio_list, list) { + if (!fltr(mmio_info, mr)) + continue; + iounmap(mr->addr); + list_del(&mr->list); + kfree(mr); + } +} +EXPORT_SYMBOL_NS_GPL(libie_pci_unmap_fltr_regs, "LIBIE_PCI"); + +/** + * libie_pci_unmap_all_mmio_regions - unmap all PCI device MMIO regions + * @mmio_info: contains list of MMIO regions to unmap + */ +void libie_pci_unmap_all_mmio_regions(struct libie_mmio_info *mmio_info) +{ + struct libie_pci_mmio_region *mr, *tmp; + + list_for_each_entry_safe(mr, tmp, &mmio_info->mmio_list, list) { + iounmap(mr->addr); + list_del(&mr->list); + kfree(mr); + } +} +EXPORT_SYMBOL_NS_GPL(libie_pci_unmap_all_mmio_regions, "LIBIE_PCI"); + +/** + * libie_pci_init_dev - enable and reserve PCI regions of the device + * @pdev: PCI device information + * + * Return: %0 on success, -%errno on failure. + */ +int libie_pci_init_dev(struct pci_dev *pdev) +{ + int err; + + err =3D pcim_enable_device(pdev); + if (err) + return err; + + for (int bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) + if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) + pcim_request_region(pdev, bar, pci_name(pdev)); + + err =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (err) + return err; + + pci_set_master(pdev); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(libie_pci_init_dev, "LIBIE_PCI"); + +MODULE_DESCRIPTION("Common Ethernet PCI library"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/intel/libie/pci.h b/include/linux/intel/libie/pc= i.h new file mode 100644 index 000000000000..d3129f1023b7 --- /dev/null +++ b/include/linux/intel/libie/pci.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2025 Intel Corporation */ + +#ifndef __LIBIE_PCI_H +#define __LIBIE_PCI_H + +#include + +/** + * struct libie_pci_mmio_region - structure for MMIO region info + * @list: used to add a MMIO region to the list of MMIO regions in + * libie_mmio_info + * @addr: virtual address of MMIO region start + * @offset: start offset of the MMIO region + * @size: size of the MMIO region + * @bar_idx: BAR index to which the MMIO region belongs to + */ +struct libie_pci_mmio_region { + struct list_head list; + void __iomem *addr; + resource_size_t offset; + resource_size_t size; + u16 bar_idx; +}; + +/** + * struct libie_mmio_info - contains list of MMIO regions + * @pdev: PCI device pointer + * @mmio_list: list of MMIO regions + */ +struct libie_mmio_info { + struct pci_dev *pdev; + struct list_head mmio_list; +}; + +#define libie_pci_map_mmio_region(mmio_info, offset, size, ...) \ + __libie_pci_map_mmio_region(mmio_info, offset, size, \ + COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__) + +#define libie_pci_get_mmio_addr(mmio_info, offset, ...) \ + __libie_pci_get_mmio_addr(mmio_info, offset, \ + COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__) + +bool __libie_pci_map_mmio_region(struct libie_mmio_info *mmio_info, + resource_size_t offset, resource_size_t size, + int num_args, ...); +void __iomem *__libie_pci_get_mmio_addr(struct libie_mmio_info *mmio_info, + resource_size_t region_offset, + int num_args, ...); +void libie_pci_unmap_all_mmio_regions(struct libie_mmio_info *mmio_info); +void libie_pci_unmap_fltr_regs(struct libie_mmio_info *mmio_info, + bool (*fltr)(struct libie_mmio_info *mmio_info, + struct libie_pci_mmio_region *reg)); +int libie_pci_init_dev(struct pci_dev *pdev); + +#endif /* __LIBIE_PCI_H */ --=20 2.47.0