From nobody Tue Dec 2 02:59:04 2025 Received: from mail.tuxedocomputers.com (mail.tuxedocomputers.com [157.90.84.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7475B32C333; Mon, 17 Nov 2025 13:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=157.90.84.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763385948; cv=none; b=OXw5j7UgmHotMV11W+ffQbCt3UyLNMgvmsUs4KZ5Sjj6pzbIN2+U16T7z0tWgm1bisvWm9fq+ga/V5nIJQ4keEUFZExWWER7K2zvWLA7omGLyuvAuhdEOEEVkIKgG6EVp5IZKvIgTZcRM+o9eYIN2ln1rd8HUJ/EBWNxeel/FPM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763385948; c=relaxed/simple; bh=EX+FMJnlta2cX2nu/mMkQn/QmagNkH6hE8AMx2GEcpg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jn/bCsVpmcJwmZfNL5P2pq3N86oWZgFCQSZHgtNE1wsEnqOC3aY/u1hU/nUgukd6M7w/OlhWKitQXvnmLpFybYMorJYNiZNF+j8mKtUfh82kq0Q7H17C0aF3LksdM8C9MdA/829aLAz81iHjCkBB8inpdksMbGgq9FpgpHN8nFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tuxedocomputers.com; spf=pass smtp.mailfrom=tuxedocomputers.com; dkim=pass (1024-bit key) header.d=tuxedocomputers.com header.i=@tuxedocomputers.com header.b=DecLh4Us; arc=none smtp.client-ip=157.90.84.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tuxedocomputers.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxedocomputers.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=tuxedocomputers.com header.i=@tuxedocomputers.com header.b="DecLh4Us" Received: from wse-pc.fritz.box (pd9e597c7.dip0.t-ipconnect.de [217.229.151.199]) (Authenticated sender: wse@tuxedocomputers.com) by mail.tuxedocomputers.com (Postfix) with ESMTPA id 4EB132FC0052; Mon, 17 Nov 2025 14:25:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxedocomputers.com; s=default; t=1763385939; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FyM8xaGa9jOCk3Zx1E9YVuruBYLwmd3NYzb+o2Oe+2s=; b=DecLh4UsKF9Ip3W9vkMg5X26Ue1C3rKy/R4+y71dKeZTAzZFMdmzsXQeo0rbKOWcnXp9vG HWQbQSnZPZi5ROzRmutZdeti0e3ylk9Ub87L9pRfXQGpHhOh9MPCB7TheUN2AMUkh+t8KS r4MNedCXPvPjAHnCN/id9ywFk1SA6mM= Authentication-Results: mail.tuxedocomputers.com; auth=pass smtp.auth=wse@tuxedocomputers.com smtp.mailfrom=wse@tuxedocomputers.com From: Werner Sembach To: W_Armin@gmx.de, hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Werner Sembach Subject: [PATCH 3/6] platform/x86/uniwill: Implement cTGP setting Date: Mon, 17 Nov 2025 14:24:00 +0100 Message-ID: <20251117132530.32460-4-wse@tuxedocomputers.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251117132530.32460-1-wse@tuxedocomputers.com> References: <20251117132530.32460-1-wse@tuxedocomputers.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Uniwill offers user setable cTGP for their EC on devices using NVIDIA 3000 Series and newer GPUs. This patch implements this setting as a sysfs attribute. Signed-off-by: Werner Sembach --- drivers/platform/x86/uniwill/uniwill-acpi.c | 110 +++++++++++++++++++- 1 file changed, 107 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/uniwill/uniwill-acpi.c b/drivers/platform= /x86/uniwill/uniwill-acpi.c index 0cb86a701b2e1..de3417d9d1ac0 100644 --- a/drivers/platform/x86/uniwill/uniwill-acpi.c +++ b/drivers/platform/x86/uniwill/uniwill-acpi.c @@ -122,11 +122,11 @@ #define CTGP_DB_DB_ENABLE BIT(1) #define CTGP_DB_CTGP_ENABLE BIT(2) =20 -#define EC_ADDR_CTGP_OFFSET 0x0744 +#define EC_ADDR_CTGP_DB_CTGP_OFFSET 0x0744 =20 -#define EC_ADDR_TPP_OFFSET 0x0745 +#define EC_ADDR_CTGP_DB_TPP_OFFSET 0x0745 =20 -#define EC_ADDR_MAX_TGP 0x0746 +#define EC_ADDR_CTGP_DB_DB_OFFSET 0x0746 =20 #define EC_ADDR_LIGHTBAR_AC_CTRL 0x0748 #define LIGHTBAR_APP_EXISTS BIT(0) @@ -317,6 +317,7 @@ #define UNIWILL_FEATURE_LIGHTBAR BIT(3) #define UNIWILL_FEATURE_BATTERY BIT(4) #define UNIWILL_FEATURE_HWMON BIT(5) +#define UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL BIT(6) =20 struct uniwill_data { struct device *dev; @@ -498,6 +499,10 @@ static bool uniwill_writeable_reg(struct device *dev, = unsigned int reg) case EC_ADDR_LIGHTBAR_BAT_RED: case EC_ADDR_LIGHTBAR_BAT_GREEN: case EC_ADDR_LIGHTBAR_BAT_BLUE: + case EC_ADDR_CTGP_DB_CTRL: + case EC_ADDR_CTGP_DB_CTGP_OFFSET: + case EC_ADDR_CTGP_DB_TPP_OFFSET: + case EC_ADDR_CTGP_DB_DB_OFFSET: return true; default: return false; @@ -531,6 +536,10 @@ static bool uniwill_readable_reg(struct device *dev, u= nsigned int reg) case EC_ADDR_LIGHTBAR_BAT_RED: case EC_ADDR_LIGHTBAR_BAT_GREEN: case EC_ADDR_LIGHTBAR_BAT_BLUE: + case EC_ADDR_CTGP_DB_CTRL: + case EC_ADDR_CTGP_DB_CTGP_OFFSET: + case EC_ADDR_CTGP_DB_TPP_OFFSET: + case EC_ADDR_CTGP_DB_DB_OFFSET: return true; default: return false; @@ -786,6 +795,68 @@ static ssize_t breathing_in_suspend_show(struct device= *dev, struct device_attri =20 static DEVICE_ATTR_RW(breathing_in_suspend); =20 +static ssize_t ctgp_offset_store(struct device *dev, struct device_attribu= te *attr, + const char *buf, size_t count) +{ + struct uniwill_data *data =3D dev_get_drvdata(dev); + unsigned int value; + int ret; + + ret =3D kstrtouint(buf, 0, &value); + if (ret < 0) + return ret; + + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, value); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t ctgp_offset_show(struct device *dev, struct device_attribut= e *attr, + char *buf) +{ + struct uniwill_data *data =3D dev_get_drvdata(dev); + unsigned int value; + int ret; + + ret =3D regmap_read(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, &value); + if (ret < 0) + return ret; + + return sysfs_emit(buf, "%u\n", value); +} + +DEVICE_ATTR_RW(ctgp_offset); + +static int uniwill_nvidia_ctgp_init(struct uniwill_data *data) +{ + int ret; + + if (!(supported_features & UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL)) + return 0; + + ret =3D regmap_update_bits(data->regmap, EC_ADDR_CTGP_DB_CTRL, + CTGP_DB_GENERAL_ENABLE | CTGP_DB_DB_ENABLE | CTGP_DB_CTGP_ENABLE, + CTGP_DB_GENERAL_ENABLE | CTGP_DB_DB_ENABLE | CTGP_DB_CTGP_ENABLE); + if (ret < 0) + return ret; + + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, 0); + if (ret < 0) + return ret; + + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_TPP_OFFSET, 255); + if (ret < 0) + return ret; + + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_DB_OFFSET, 25); + if (ret < 0) + return ret; + + return 0; +} + static struct attribute *uniwill_attrs[] =3D { /* Keyboard-related */ &dev_attr_fn_lock_toggle_enable.attr, @@ -794,6 +865,8 @@ static struct attribute *uniwill_attrs[] =3D { /* Lightbar-related */ &dev_attr_rainbow_animation.attr, &dev_attr_breathing_in_suspend.attr, + /* Power-management-related */ + &dev_attr_ctgp_offset.attr, NULL }; =20 @@ -820,6 +893,11 @@ static umode_t uniwill_attr_is_visible(struct kobject = *kobj, struct attribute *a return attr->mode; } =20 + if (attr =3D=3D &dev_attr_ctgp_offset.attr) { + if (supported_features & UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL) + return attr->mode; + } + return 0; } =20 @@ -1371,6 +1449,10 @@ static int uniwill_probe(struct platform_device *pde= v) if (ret < 0) return ret; =20 + ret =3D uniwill_nvidia_ctgp_init(data); + if (ret < 0) + return ret; + return uniwill_input_init(data); } =20 @@ -1547,6 +1629,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "PHxTQx1"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO InfinityBook Pro 14/16 Gen7 Intel", @@ -1554,6 +1637,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "PHxARX1_PHxAQF1"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO InfinityBook Pro 16 Gen7 Intel/Commodore Omnia-Book P= ro Gen 7", @@ -1561,6 +1645,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH6AG01_PH6AQ71_PH6AQI1"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO InfinityBook Pro 14/16 Gen8 Intel/Commodore Omnia-Boo= k Pro Gen 8", @@ -1575,6 +1660,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH4PG31"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO InfinityBook Pro 16 Gen8 Intel", @@ -1582,6 +1668,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH6PG01_PH6PG71"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO InfinityBook Pro 14/15 Gen9 AMD", @@ -1694,6 +1781,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxMGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Polaris 15/17 Gen2 Intel", @@ -1701,6 +1789,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxNGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen3 AMD", @@ -1708,6 +1797,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxZGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen3 Intel", @@ -1715,6 +1805,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxTGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen4 AMD", @@ -1722,6 +1813,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxRGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 15 Gen4 Intel", @@ -1729,6 +1821,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxAGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Polaris 15/17 Gen5 AMD", @@ -1736,6 +1829,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxXGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen5 AMD", @@ -1743,6 +1837,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6XGxX"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16/17 Gen5 Intel/Commodore ORION Gen 5", @@ -1750,6 +1845,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxPXxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris Slim 15 Gen6 AMD", @@ -1757,6 +1853,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxHGxx"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris Slim 15 Gen6 Intel/Commodore ORION Slim 15 = Gen6", @@ -1764,6 +1861,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM5IXxA"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen6 Intel/Commodore ORION 16 Gen6", @@ -1771,6 +1869,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6IXxB_MB1"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen6 Intel/Commodore ORION 16 Gen6", @@ -1778,6 +1877,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6IXxB_MB2"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 17 Gen6 Intel/Commodore ORION 17 Gen6", @@ -1785,6 +1885,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM7IXxN"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen7 AMD", @@ -1792,6 +1893,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6FR5xxY"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen7 Intel", @@ -1799,6 +1901,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6AR5xxY"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Stellaris 16 Gen7 Intel", @@ -1806,6 +1909,7 @@ static const struct dmi_system_id uniwill_dmi_table[]= __initconst =3D { DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6AR5xxY_mLED"), }, + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), }, { .ident =3D "TUXEDO Pulse 14 Gen1 AMD", --=20 2.43.0