From nobody Tue Dec 2 03:00:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D76632E720; Mon, 17 Nov 2025 12:41:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763383304; cv=none; b=WxhiR4wgCuMEvcKRr/WdragPkbW0Jod8p2AFlizo356mvT6wTzCCaK33CytZgI/I+dS69qXjUN/JJq/EC2O+zrd2UfqggZ+nkDt37zfJLE5KopVrCQlySevQ826juwcnPjB1RFQyYVCakApIiAvNCHgWXyFcSqqyEXhmlCTw4jE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763383304; c=relaxed/simple; bh=EtgjniBI1ey4qVAAv41BTEGXtgpXYBGSNtFMyDswsbg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZPE2JZp2L86CCUOoHTutaHhLdl3XS+csyH4bowbx0wL20L+u+QarGlb1oDT6iEfJYufSVYYZjquMFfEfR2TjWUs3ggoNYL65MWNMB74hL/WkM8sNsGNNPCfZHD+iiElsG0Zek3VOm4kZnGD7+FZA6n8ZyD2lcqwML3VNihLY/oM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MXA6wu5w; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MXA6wu5w" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 998AFC4CEF1; Mon, 17 Nov 2025 12:41:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763383304; bh=EtgjniBI1ey4qVAAv41BTEGXtgpXYBGSNtFMyDswsbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MXA6wu5wx2ej8t6FINgPibq+mMXWALYZvYku0YTe4HwG2qlKv/Lo/8XIW8Kvpb0UH xiBvp0q8tHvEGdE+bGEI0KJPl0UPuPIOy8bzVq7ONKaLN7Xml3cHlmGhvnvsZ9+QXV mCwA3RZsYG1zhSUowtWoFoWfLKbtkgZ1B0HwUIPNpgLt5Abvk7VdQ/YEE7aA3kPIjp J3NCl+P6lt17CsOMD4jCRnS/FV0auD16IRpTbscOfmNUQjrQbPmcztrKYhM4jBN+UI T0p4CcPrX5GC6yBwYvmy7jqslB85ulDMdSquVdoodBWHD982zs8r5bRuLNYVeO34WP kuA6IHN+NAZZg== From: Jiri Olsa To: Oleg Nesterov , Masami Hiramatsu , Peter Zijlstra , Andrii Nakryiko Cc: bpf@vger.kernel.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, x86@kernel.org, Song Liu , Yonghong Song , John Fastabend , Steven Rostedt , Ingo Molnar , David Laight Subject: [RFC PATCH 3/8] uprobe/x86: Add support to emulate mov reg,reg instructions Date: Mon, 17 Nov 2025 13:40:52 +0100 Message-ID: <20251117124057.687384-4-jolsa@kernel.org> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251117124057.687384-1-jolsa@kernel.org> References: <20251117124057.687384-1-jolsa@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding support to emulate mov reg to reg instructions, because it's often part of the function prologue. Signed-off-by: Jiri Olsa --- arch/x86/include/asm/uprobes.h | 5 +++ arch/x86/kernel/uprobes.c | 61 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h index 819e35aa61c4..e6fd87a1cbc3 100644 --- a/arch/x86/include/asm/uprobes.h +++ b/arch/x86/include/asm/uprobes.h @@ -44,6 +44,11 @@ struct arch_uprobe_xol { u8 reg_offset; /* to the start of pt_regs */ u8 ilen; } push; + struct { + u16 src; /* to the start of pt_regs */ + u16 dst; /* to the start of pt_regs */ + u8 ilen; + } mov; }; }; =20 diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 7d7a5e677472..5c44c4b84e99 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 /* Post-execution fixups. */ =20 @@ -1414,6 +1415,19 @@ static void branch_clear_offset(struct arch_uprobe *= auprobe, struct insn *insn) 0, insn->immediate.nbytes); } =20 +static bool mov_emulate_op(struct arch_uprobe *auprobe, struct arch_uprobe= _xol *xol, + struct pt_regs *regs) +{ + unsigned long *dst, *src; + + dst =3D (void *) regs + xol->mov.dst; + src =3D (void *) regs + xol->mov.src; + *dst =3D *src; + + regs->ip +=3D xol->mov.ilen; + return true; +} + static const struct uprobe_xol_ops branch_xol_ops =3D { .emulate =3D branch_emulate_op, .post_xol =3D branch_post_xol_op, @@ -1423,6 +1437,10 @@ static const struct uprobe_xol_ops push_xol_ops =3D { .emulate =3D push_emulate_op, }; =20 +static const struct uprobe_xol_ops mov_xol_ops =3D { + .emulate =3D mov_emulate_op, +}; + /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *= insn) { @@ -1560,6 +1578,45 @@ static int push_setup_xol_ops(struct arch_uprobe_xol= *xol, struct insn *insn) return 0; } =20 +#ifdef CONFIG_X86_64 +/* Returns -ENOSYS if mov_xol_ops doesn't handle this insn */ +static int mov_setup_xol_ops(struct arch_uprobe_xol *xol, struct insn *ins= n) +{ + u8 opc1 =3D OPCODE1(insn); + int off_src, off_dst; + + /* validate opcode */ + if (opc1 !=3D 0x89) + return -ENOSYS; + if (insn->rex_prefix.nbytes !=3D 1 || + insn->rex_prefix.bytes[0] !=3D 0x48) + return -ENOSYS; + + /* only register operands */ + if (X86_MODRM_MOD(insn->modrm.value) !=3D 3) + return -ENOSYS; + + /* get registers offset */ + off_src =3D insn_get_modrm_reg_off(insn); + if (off_src < 0) + return off_src; + off_dst =3D insn_get_modrm_rm_off(insn); + if (off_dst < 0) + return off_dst; + + xol->mov.src =3D off_src; + xol->mov.dst =3D off_dst; + xol->mov.ilen =3D insn->length; + xol->ops =3D &mov_xol_ops; + return 0; +} +#else +static int mov_setup_xol_ops(struct arch_uprobe_xol *xol, struct insn *ins= n) +{ + return -ENOSYS; +} +#endif + /** * arch_uprobe_analyze_insn - instruction analysis including validity and = fixups. * @auprobe: the probepoint information. @@ -1588,6 +1645,10 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *aup= robe, struct mm_struct *mm, if (ret !=3D -ENOSYS) return ret; =20 + ret =3D mov_setup_xol_ops(&auprobe->xol, &insn); + if (ret !=3D -ENOSYS) + return ret; + /* * Figure out which fixups default_post_xol_op() will need to perform, * and annotate defparam->fixups accordingly. --=20 2.51.1