From nobody Tue Dec 2 02:58:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BC27302CD8; Mon, 17 Nov 2025 16:53:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763398420; cv=none; b=gmhgAm1tYwinEDvpXUsCutatf3cVlzP7Yx3MVI+ULPYNJjTxIBZwoZwb+N+syGx27is/CB1P51oGd2F7fwjpCWw3xbl2p4xFmuClgfe5Ghg87ClDZOmxNtEqzDU87+j9TC1wFQxe2WM6x8Q4viDbPmSZtsnvr28e7JJuqHQZqbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763398420; c=relaxed/simple; bh=q7TV7YcxO4HOBHpwalJWuQ9R+xLm/zrs6LRfhYBIcnk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FXem3xUyfmVmsVScgLUVJW/M+YksQ84Gh1oWHtttN4Y8rbzssPN0trIXfmeaAkwHcEoViOijcxHetv6S+FxSVR4nVt47izZO41TrLG7ujWXj6z3RCusOIFNoWk/kmMxgFiBnbglrg1N1DdWufR95pBGhPMQBwUI5aJjByg9/xCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DEpGf8wV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DEpGf8wV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E53A0C116B1; Mon, 17 Nov 2025 16:53:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763398419; bh=q7TV7YcxO4HOBHpwalJWuQ9R+xLm/zrs6LRfhYBIcnk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DEpGf8wVKwaZcZhEpI3dhgyAr9cZKVfAPWhwYiPcR0azQWLDaPt6K3TUWL2Tm3Z4V 9aDVC8kUeuOtXXnY3oCYhcXaxKNrgKfdDmL1P8YD451+77fRgRKiq3imSSpxthHfIa W1xBzx4NLaRZxJKyzDhQDTGBsZAUbBzANzut20OJ1rEdJwgxIeyZ0PxxOwa0km/1r2 kvRfbAOM3ZBGJn5tC2emXxxTs6ZUFxP+AdxJSwGVAGr7swb3BRpc2302HuS/7F0B8z yy+dEx1HIKtr/VZk5hep8p17TaA+cI370TZDvjgTyKsREO5XN9nFyV1QpiWxg9lZLY men5JIJO3CneA== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Pierre-Henry Moussay Subject: [PATCH v3 2/3] riscv: dts: microchip: add pic64gx and its curiosity kit Date: Mon, 17 Nov 2025 16:53:23 +0000 Message-ID: <20251117-try-shallow-76b7c5753a66@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251117-paprika-tipping-e7bb3e211d6f@spud> References: <20251117-paprika-tipping-e7bb3e211d6f@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=27324; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=bUnInxNdhJyrNcft2XwTYaSCwtTeqOL05Jz7DBTNaq8=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJnSQf9PMqZITz3hZz8hRDf3Vfuq3ZIM0cbHtfi00hofJ CpnsTl2lLIwiHExyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCInbjD8d2erU1lQsPFxPB9v 0af27cZTyvrSFq9RX5K5+rkQe+b2Swz/FEry71/68MzI8HRKZ7uSi9KH6rLqT5OqDl2bs30zx7e XPAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pierre-Henry Moussay The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000. Features include: - 1 GB DDR4 SDRAM - Gigabit Ethernet - microSD-card slot note: due to issue on some board, the SDHCI is limited to HS (High speed mode, with a clock of 50MHz and 3.3V signals). Signed-off-by: Pierre-Henry Moussay Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/pic64gx-curiosity-kit.dts | 165 +++++ .../boot/dts/microchip/pic64gx-pinctrl.dtsi | 178 +++++ arch/riscv/boot/dts/microchip/pic64gx.dtsi | 630 ++++++++++++++++++ 4 files changed, 974 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts create mode 100644 arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/microchip/pic64gx.dtsi diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 345ed7a48cc1..3ff4a4f67dc4 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp= .dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-tysom-m.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) +=3D pic64gx-curiosity-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch= /riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts new file mode 100644 index 000000000000..2f2ccd77af30 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the PIC64GX Curiosity Kit + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Pierre-Henry Moussay + * + * The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC + * prototyping board featuring a Microchip PIC64GX SoC + * PIC64GX-1000. Features include: + * - 1 GB DDR4 SDRAM + * - Gigabit Ethernet + * - microSD-card slot + * + * https://www.microchip.com/en-us/development-tool/curiosity-pic64gx1000-= kit-es + */ + +/dts-v1/; + +#include "pic64gx.dtsi" +#include "pic64gx-pinctrl.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Microchip PIC64GX Curiosity Kit"; + compatible =3D "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + aliases { + ethernet0 =3D &mac0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss: hss-buffer@bfc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&gpio0 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + status =3D"okay"; + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "", "", "", "MIPI_CAM_RESET", "MIPI_CAM_STANDBY"; +}; + +&gpio1 { + interrupts =3D <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status =3D"okay"; + gpio-line-names =3D + "", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6", + "LED7", "LED8", "", "", "", "", "", "", + "", "", "", "", "HDMI_HPD", "", "", "GPIO_1_23"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>, + <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>; + status =3D"okay"; + gpio-line-names =3D + "", "", "", "", "", "", "SWITCH2", "USR_IO12", + "DIP1", "DIP2", "", "DIP3", "USR_IO1", "USR_IO2", "USR_IO7", "USR_IO8", + "USR_IO3", "USR_IO4", "USR_IO5", "USR_IO6", "", "", "USR_IO9", "USR_IO10= ", + "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_default>; + + phy0: ethernet-phy@b { + reg =3D <0xb>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + sdhci-caps-mask =3D <0x00000007 0x00000000>; + status =3D "okay"; +}; + +&mmuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_fio>; + status =3D "okay"; +}; + +&mmuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_default>; + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi b/arch/risc= v/boot/dts/microchip/pic64gx-pinctrl.dtsi new file mode 100644 index 000000000000..319daee04755 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&iomux0 { + spi0_fio: mux-spi0-fabric { + function =3D "spi0"; + groups =3D "spi0_fabric"; + }; + + spi1_mssio: mux-spi1-mssio { + function =3D "spi1"; + groups =3D "spi1_mssio"; + }; + + i2c0_mssio: mux-i2c0-mssio { + function =3D "i2c0"; + groups =3D "i2c0_mssio"; + }; + + i2c1_mssio: mux-i2c1-mssio { + function =3D "i2c1"; + groups =3D "i2c1_mssio"; + }; + + can0_fio: mux-can0-fabric { + function =3D "can0"; + groups =3D "can0_fabric"; + }; + + can1_fio: mux-can1-fabric { + function =3D "can1"; + groups =3D "can1_fabric"; + }; + + qspi_fio: mux-qspi-fabric { + function =3D "qspi"; + groups =3D "qspi_fabric"; + }; + + uart0_mssio: mux-uart0-mssio { + function =3D "uart0"; + groups =3D "uart0_mssio"; + }; + + uart1_fio: mux-uart1-fabric { + function =3D "uart1"; + groups =3D "uart1_fabric"; + }; + + uart2_fio: mux-uart2-fabric { + function =3D "uart2"; + groups =3D "uart2_fabric"; + }; + + uart3_fio: mux-uart3-fabric { + function =3D "uart3"; + groups =3D "uart3_fabric"; + }; + + uart4_fio: mux-uart4-fabric { + function =3D "uart4"; + groups =3D "uart4_fabric"; + }; + + mdio0_fio: mux-mdio0-fabric { + function =3D "mdio0"; + groups =3D "mdio0_fabric"; + }; + + mdio1_fio: mux-mdio1-fabric { + function =3D "mdio1"; + groups =3D "mdio1_fabric"; + }; +}; + +&gpio2_pinctrl { + //TODO rethink the labels, since a bunch of these are not defaults or + //just outright remove the non-default groups + mdio0_default: mux-mac0 { + function =3D "mdio0"; + groups =3D "mdio0"; + }; + + mdio0_gpio: mux-mac0-gpio2 { + function =3D "gpio"; + groups =3D "gpio_mdio0"; + }; + + mdio1_default: mux-mac1 { + function =3D "mdio1"; + groups =3D "mdio1"; + }; + + mdio1_gpio: mux-mac1-gpio2 { + function =3D "gpio"; + groups =3D "gpio_mdio1"; + }; + + spi0_default: mux-spi0 { + function =3D "spi0"; + groups =3D "spi0"; + }; + + spi0_gpio: mux-spi0-gpio2 { + function =3D "gpio"; + groups =3D "gpio_spi0"; + }; + + can0_default: mux-can0 { + function =3D "can0"; + groups =3D "can0"; + }; + + can0_gpio: mux-can0-gpio2 { + function =3D "gpio"; + groups =3D "gpio_can0"; + }; + + pcie_default: mux-pcie { + function =3D "pcie"; + groups =3D "pcie"; + }; + + pcie_gpio: mux-pcie-gpio2 { + function =3D "gpio"; + groups =3D "gpio_pcie"; + }; + + qspi_default: mux-qspi { + function =3D "qspi"; + groups =3D "qspi"; + }; + + qspi_gpio: mux-qspi-gpio2 { + function =3D "gpio"; + groups =3D "gpio_qspi"; + }; + + uart3_default: mux-uart3 { + function =3D "uart3"; + groups =3D "uart3"; + }; + + uart3_gpio: mux-uart3-gpio2 { + function =3D "gpio"; + groups =3D "gpio_uart3"; + }; + + uart4_default: mux-uart4 { + function =3D "uart4"; + groups =3D "uart4"; + }; + + uart4_gpio: mux-uart4-gpio2 { + function =3D "gpio"; + groups =3D "gpio_uart4"; + }; + + can1_default: mux-can1 { + function =3D "can1"; + groups =3D "can1"; + }; + + can1_gpio: mux-can1-gpio2 { + function =3D "gpio"; + groups =3D "gpio_can1"; + }; + + uart2_default: mux-uart2 { + function =3D "uart2"; + groups =3D "uart2"; + }; + + uart2_gpio: mux-uart2-gpio2 { + function =3D "gpio"; + groups =3D "gpio_uart2"; + }; +}; + diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/d= ts/microchip/pic64gx.dtsi new file mode 100644 index 000000000000..c164d7bc270a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the PIC64GX SoCs + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Pierre-Henry Moussay + * + * PIC64GX is a series RISC-V multicore SoCs: + * https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pi= c64gx + */ + +/dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Microchip PIC64GX SoC"; + compatible =3D "microchip,pic64gx"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + clocks =3D <&clkcfg CLK_CPU>; + status =3D "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks =3D <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache =3D <&cctrllr>; + status =3D "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks =3D <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache =3D <&cctrllr>; + status =3D "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks =3D <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache =3D <&cctrllr>; + status =3D "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks =3D <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache =3D <&cctrllr>; + status =3D "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + }; + }; + }; + + scbclk: clock-80000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <80000000>; + }; + + refclk: mssrefclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + axiclk: axi-aclk0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + videoclk: video-aclk0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + syscontroller: syscontroller { + compatible =3D "microchip,pic64gx-sys-controller"; + mboxes =3D <&mbox 0>; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + clint: clint@2000000 { + compatible =3D "microchip,pic64gx-clint", "sifive,clint0"; + reg =3D <0x0 0x2000000 0x0 0xC000>; + interrupts-extended =3D <&cpu0_intc 0xffffffff>, <&cpu0_intc 0xffffffff= >, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + cctrllr: cache-controller@2010000 { + compatible =3D "microchip,pic64gx-ccache", "microchip,mpfs-ccache", + "sifive,fu540-c000-ccache", "cache"; + reg =3D <0x0 0x2010000 0x0 0x1000>; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic>; + interrupts =3D <1>, <3>, <4>, <2>; + }; + + pdma: dma-controller@3000000 { + compatible =3D "microchip,pic64gx-pdma", "microchip,mpfs-pdma", + "sifive,pdma0"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic>; + interrupts =3D <5 6>, <7 8>, <9 10>, <11 12>; + #dma-cells =3D <1>; + }; + + plic: interrupt-controller@c000000 { + compatible =3D "microchip,pic64gx-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev =3D <186>; + }; + + mmuart0: serial@20000000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20000000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <90>; + current-speed =3D <115200>; + clocks =3D <&clkcfg CLK_MMUART0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_mssio>; + status =3D "disabled"; /* Reserved for the HSS */ + }; + + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,pic64gx-mss-top-sysreg", + "microchip,mpfs-mss-top-sysreg", + "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #reset-cells =3D <1>; + + iomux0: pinctrl@200 { + compatible =3D "microchip,pic64gx-pinctrl-iomux0", + "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + pinctrl-use-default; + }; + + mssio: pinctrl@204 { + compatible =3D "microchip,pic64gx-pinctrl-mssio", + "microchip,mpfs-pinctrl-mssio"; + reg =3D <0x204 0x7c>; + /* on icicle ref design at least */ + pinctrl-use-default; + }; + }; + + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,pic64gx-sysreg-scb", + "microchip,mpfs-sysreg-scb", + "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + + /* Common node entry for emmc/sd */ + mmc: mmc@20008000 { + compatible =3D "microchip,pic64gx-sd4hc", "cdns,sd4hc"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <88>; + clocks =3D <&clkcfg CLK_MMC>; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + + mmuart1: serial@20100000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20100000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <91>; + current-speed =3D <115200>; + clocks =3D <&clkcfg CLK_MMUART1>; + status =3D "disabled"; + }; + + mmuart2: serial@20102000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20102000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <92>; + current-speed =3D <115200>; + clocks =3D <&clkcfg CLK_MMUART2>; + status =3D "disabled"; + }; + + mmuart3: serial@20104000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20104000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <93>; + current-speed =3D <115200>; + clocks =3D <&clkcfg CLK_MMUART3>; + status =3D "disabled"; + }; + + mmuart4: serial@20106000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x20106000 0x0 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <94>; + clocks =3D <&clkcfg CLK_MMUART4>; + current-speed =3D <115200>; + status =3D "disabled"; + }; + + spi0: spi@20108000 { + compatible =3D "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x20108000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <54>; + clocks =3D <&clkcfg CLK_SPI0>; + status =3D "disabled"; + }; + + spi1: spi@20109000 { + compatible =3D "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x20109000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <55>; + clocks =3D <&clkcfg CLK_SPI1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_mssio>; + status =3D "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible =3D "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; + reg =3D <0x0 0x2010a000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <58>; + clocks =3D <&clkcfg CLK_I2C0>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_mssio>; + status =3D "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible =3D "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; + reg =3D <0x0 0x2010b000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <61>; + clocks =3D <&clkcfg CLK_I2C1>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_mssio>; + status =3D "disabled"; + }; + + can0: can@2010c000 { + compatible =3D "microchip,pic64gx-can", "microchip,mpfs-can"; + reg =3D <0x0 0x2010c000 0x0 0x1000>; + clocks =3D <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; + interrupt-parent =3D <&plic>; + interrupts =3D <56>; + resets =3D <&mss_top_sysreg CLK_CAN0>; + status =3D "disabled"; + }; + + can1: can@2010d000 { + compatible =3D "microchip,pic64gx-can", "microchip,mpfs-can"; + reg =3D <0x0 0x2010d000 0x0 0x1000>; + clocks =3D <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; + interrupt-parent =3D <&plic>; + interrupts =3D <57>; + resets =3D <&mss_top_sysreg CLK_CAN1>; + status =3D "disabled"; + }; + + mac0: ethernet@20110000 { + compatible =3D "microchip,pic64gx-macb", "microchip,mpfs-macb", + "cdns,macb"; + reg =3D <0x0 0x20110000 0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <64>, <65>, <66>, <67>, <68>, <69>; + /* Filled in by a bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names =3D "pclk", "hclk"; + resets =3D <&mss_top_sysreg CLK_MAC0>; + status =3D "disabled"; + }; + + mac1: ethernet@20112000 { + compatible =3D "microchip,pic64gx-macb", "microchip,mpfs-macb", + "cdns,macb"; + reg =3D <0x0 0x20112000 0x0 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&plic>; + interrupts =3D <70>, <71>, <72>, <73>, <74>, <75>; + /* Filled in by a bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names =3D "pclk", "hclk"; + resets =3D <&mss_top_sysreg CLK_MAC1>; + status =3D "disabled"; + }; + + gpio0: gpio@20120000 { + compatible =3D "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg =3D <0x0 0x20120000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <14>; + status =3D "disabled"; + }; + + gpio1: gpio@20121000 { + compatible =3D "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg =3D <0x0 0x20121000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <24>; + status =3D "disabled"; + }; + + gpio2: gpio@20122000 { + compatible =3D "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg =3D <0x0 0x20122000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupt-controller; + #interrupt-cells =3D <1>; + clocks =3D <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + status =3D "disabled"; + }; + + rtc: rtc@20124000 { + compatible =3D "microchip,pic64gx-rtc", "microchip,mpfs-rtc"; + reg =3D <0x0 0x20124000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <80>, <81>; + clocks =3D <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names =3D "rtc", "rtcref"; + status =3D "disabled"; + }; + + usb: usb@20201000 { + compatible =3D "microchip,pic64gx-musb", "microchip,mpfs-musb"; + reg =3D <0x0 0x20201000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <86>, <87>; + clocks =3D <&clkcfg CLK_USB>; + interrupt-names =3D "dma", "mc"; + status =3D "disabled"; + }; + + qspi: spi@21000000 { + compatible =3D "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x21000000 0x0 0x1000>; + interrupt-parent =3D <&plic>; + interrupts =3D <85>; + clocks =3D <&clkcfg CLK_QSPI>; + status =3D "disabled"; + }; + + control_scb: syscon@37020000 { + compatible =3D "microchip,pic64gx-control-scb", + "microchip,mpfs-control-scb", + "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + syscontroller_qspi: spi@37020100 { + compatible =3D "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x37020100 0x0 0x100>; + interrupt-parent =3D <&plic>; + interrupts =3D <110>; + clocks =3D <&scbclk>; + status =3D "disabled"; + }; + + mbox: mailbox@37020800 { + compatible =3D "microchip,pic64gx-mailbox", "microchip,mpfs-mailbox"; + reg =3D <0x0 0x37020800 0x0 0x100>; + interrupt-parent =3D <&plic>; + interrupts =3D <96>; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + ccc_se: clock-controller@38010000 { + compatible =3D "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible =3D "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg =3D <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + + ccc_nw: clock-controller@38100000 { + compatible =3D "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg =3D <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible =3D "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg =3D <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,pic64gx-clkcfg", "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; + + gpio2_pinctrl: pinctrl@41000000 { + compatible =3D "microchip,pic64gx-pinctrl-gpio2"; + reg =3D <0x0 0x41000000 0x0 0x4>; + pinctrl-use-default; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_fio>, <&mdio1_fio>, <&spi0_fio>, <&qspi_fio>, + <&uart3_fio>, <&uart4_fio>, <&can1_fio>, <&can0_fio>, + <&uart2_fio>; + }; + }; +}; --=20 2.51.0