From nobody Tue Dec 2 02:51:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52920272E43; Mon, 17 Nov 2025 15:36:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763393764; cv=none; b=oPT4OQszQmjhIse21eSnsTZJKMDNBFO62KKBMzcYe4snKXpqiVo/g/nWOoYDsxdlM31/Onn9y21HABheAyOt5cd4apfNvLJRS8w4TihQ96ZZbVW6MWl2Dz/ygJtapqvpzfhfzaD8/fkzmLbL9UAlSuqaCDPA4X/epAPBES0Hi60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763393764; c=relaxed/simple; bh=Ngz4pYB+tJwskK/2e2v6SrMSgYaik/dmE+6l4zJ63mw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GaHEhOrozP+KpfpQfnuAgDX/K3ugk4ND7If8auHvf8sYSgOh0q4+nPlqT6rPGHbmo6eFOeZTXbegg8AyxvvXLORNUaOwM7BvDtMnWepLZxK0nl6NUWcljFFU2PXFduHWuLFI0BxkSz7tKWiHfcsjxIYhEJI7EMxi3aoEqmaDSvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VM8x3CbH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VM8x3CbH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58490C4CEF1; Mon, 17 Nov 2025 15:36:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763393763; bh=Ngz4pYB+tJwskK/2e2v6SrMSgYaik/dmE+6l4zJ63mw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VM8x3CbHTupXwTr57Eb8p21yqdbvluqHmz5mDdB2hX+xxlkninb9c7D3PrDrM3rLm fze9QkI5seDqXbzfhqfYv+iGsv8orJQB50B3k0CAmZS8CEuseJQUQQ1WNS8rT/j/ai ++AZC8OH8V9D7laBkKZaqBbNTVh3IjSWnHxLMkr6arTpoOq+6ZsiOu18cEZ2uNoVlQ Qe2lYbBGQxNmPgZbZo9+u0lnq7fIWz+vs9mmoqTw4bC0YCnz5DawVQh0U8hskNy/MQ re7VeFXf8V9XtpNA0uDKEST3dJ8N2NhUYAppATvlYpqCMTo+uteJ1SNFG97UJHA3Oh z4D1myf/1eU8w== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Claudiu Beznea Subject: [PATCH v1 1/3] clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE Date: Mon, 17 Nov 2025 15:35:18 +0000 Message-ID: <20251117-bulgur-wildfire-a8c5a2b417dc@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251117-shadow-police-56aba5d855a3@spud> References: <20251117-shadow-police-56aba5d855a3@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=867; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=twE2/xw0EdY4lCByaHHfukqX9Ahnfe+zRoGGS/KLfAU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJnSDlt+5p1jdy4VaS085if53oWrI7LwVNDUOSfkTD5G3 T6SWdnQUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgImkrGBk2H0v7uWtzlC/l4HJ n8yPad+8aBo+tcd1onRE9HF+hyVbXzEyfHbbvnLtm/AJgUs/byk59uZ00IqNhSmWP3QCOSfdiE7 5yQ4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley This driver is used by non-polarfire devices now, and the ARCH_MICROCHIP symbol has been defined for some time on RISCV so drop it without any functional change. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index cab9a909893b..a0ef14310417 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -5,8 +5,8 @@ config COMMON_CLK_PIC32 =20 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" - depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST - default ARCH_MICROCHIP_POLARFIRE + depends on ARCH_MICROCHIP || COMPILE_TEST + default y depends on MFD_SYSCON select AUXILIARY_BUS select COMMON_CLK_DIVIDER_REGMAP --=20 2.51.0 From nobody Tue Dec 2 02:51:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4801C275B15; Mon, 17 Nov 2025 15:36:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 17 Nov 2025 15:36:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763393766; bh=/v1QAlCCWNbMx8wdrlD6B9enfAEnlVlEnoMDUomq2iQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iqbogmmP3g3V+qa77+i8GG9erc9ZF2tJnX3QDpaiw/uJxk5fh7C8vGLyLNsqwk3IX zZXQMYlKhdgPcFpTE5EM6YEuHFYnrx7NOZ0E5YIKpgFN56LBXfhxnRMzcyLYmf7DaS 9Csy/UC+pXDB4JlT2q1c7EV+TRE6pCIGN8KozlVql04Pb275gfESTedP3Na61t+7E3 us+822vPug1aJ/gBXbeMJXbHrv93N7XQdkg2JqSvyx71rco75Amtj2cBxAZK0xZ7JM wwd9nSkqXVVSMkfGiJVxHXPgFHYSqhTDiNiR9APVT8sgATFkC1i7ulE75Sh6Qo8Vys 75ULQZeOZZH8Q== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Claudiu Beznea , Pierre-Henry Moussay Subject: [PATCH v1 2/3] dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility Date: Mon, 17 Nov 2025 15:35:19 +0000 Message-ID: <20251117-mocha-shelter-4d9aa88e34b5@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251117-shadow-police-56aba5d855a3@spud> References: <20251117-shadow-police-56aba5d855a3@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1011; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=6u/MVsorAWOBiuYW/sM6Lc9tNpUToYIrlt3K2vcU0zQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJnSDlusVvftkHSbI/m754E088HkidUdItfEpF5f+V5VL 2zZ3re3o5SFQYyLQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABN5+ZqR4c6ZvLOPar/VzKzT sd6fnbzU7qJDl9rllttumRelXixtecjI8Lluutw2H93TGrbeBhOrT+1sNy0PSPs3983v5fr33KM 4eQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pierre-Henry Moussay pic64gx SoC Clock Conditioning Circuitry is compatibles with the Polarfire SoC Signed-off-by: Pierre-Henry Moussay Acked-by: Conor Dooley Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yam= l b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml index f1770360798f..9a6b50527c42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -17,7 +17,11 @@ description: | =20 properties: compatible: - const: microchip,mpfs-ccc + oneOf: + - items: + - const: microchip,pic64gx-ccc + - const: microchip,mpfs-ccc + - const: microchip,mpfs-ccc =20 reg: items: --=20 2.51.0 From nobody Tue Dec 2 02:51:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D64527A477; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GmLKt3O9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 316CAC19424; Mon, 17 Nov 2025 15:36:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763393769; bh=pB0/QFXI5t2Hw+5qhGB5FGEiMP1+/MSOOtSe9mwKqU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GmLKt3O9GluH2JCDClqfyVVbozY56xU8N3PrQMMZP+p2nNCG7KXH4CT/5Qq6crEuN kBMKxSO3+EXbpCtDjOuay8xqcnK5qmdsfjsQSbTG4ffYiy4cKBUOmyRPJxTRIR+/vG 6JWfrl9EwmYP34Kcsniswxm7ktPbzQiGDUjqDtnpSROAdwOyTjN5s/WDK4s81i6HEH /0OjETijdTwHs4kDPU4BGQdTpXbvgJpM1RY6mXqvbrF95TXRtQL0n5x6ZrpNSPdmLE Ytoku7Fg3td/BOyBDc54tdKsXf/r1GrOQllSbvJTPZ8voeqZTonZvVRCfZMCAjML9Y 9bj6M2EJpgxiA== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Claudiu Beznea , Pierre-Henry Moussay Subject: [PATCH v1 3/3] dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility Date: Mon, 17 Nov 2025 15:35:20 +0000 Message-ID: <20251117-depth-sage-ee0829c71c25@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251117-shadow-police-56aba5d855a3@spud> References: <20251117-shadow-police-56aba5d855a3@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1355; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=awEf+2y/PPPNa2uwhs4VTzsAEfJWcc8DTYHHNv4fdl0=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJnSDlsuJ/xiPbid7V/MKQGOogOqL4+diLvR9ebqxqUrJ waXbetl6ihlYRDjYpAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBE8sQZGc6cOLY35m36o5P/ 4q5ckmJl83/HG9Ezb4Pmgcni0et3Odsx/NPYsTe6g+vh5nwx2Yvu8kcvRnovbIhKCuqV3H3OPUA yihcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pierre-Henry Moussay pic64gx has a clock controller compatible with mpfs-clkcfg. Don't permit the deprecated configuration that was never supported for this SoC. Signed-off-by: Pierre-Henry Moussay Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index ee4f31596d97..f111bed16f15 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -19,7 +19,11 @@ description: | =20 properties: compatible: - const: microchip,mpfs-clkcfg + oneOf: + - items: + - const: microchip,pic64gx-clkcfg + - const: microchip,mpfs-clkcfg + - const: microchip,mpfs-clkcfg =20 reg: oneOf: @@ -69,6 +73,15 @@ required: - clocks - '#clock-cells' =20 +if: + properties: + compatible: + contains: + const: microchip,pic64gx-clkcfg +then: + reg: + maxItems: 1 + additionalProperties: false =20 examples: --=20 2.51.0