From nobody Tue Dec 2 02:58:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAF8B33EAE6; Mon, 17 Nov 2025 17:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399049; cv=none; b=WDxeEJ8IkCw5/ej6bAw4PcxT5Anx4bZLOvO3hYnNRyIDiDs1CxIs9Iz8kh48cHWx2gKkQkRP80TCJ/YcyODjRO7cJ9FWdJnRWIjMDvaKYNaPt8Ter9rz8RrYudM/GIDUwtUk5Z4oN6gM65EJcvqZu1uYhBY04ioSJXg7q+CqLgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399049; c=relaxed/simple; bh=WIzwNdd1k37krjUiu8/Ta0AQITLv5kmAZxs0W5086ng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Md83fk2GGwreWg3GzbNnDPKHL1wlnB7vePZ0IiMVetw286BlJtGN+OHG6YEnDxs9v8SBMmyuHuxy31YHKtH35sxLeC/ggDnUuGpuolCNZw0RN0BdqD98BibhTOkdFIZINCpWS2xKdEZJ9wfSNkX9XgP8nD2kKPDI7R2nIS5wwwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L5G5aiRH; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L5G5aiRH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399048; x=1794935048; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=WIzwNdd1k37krjUiu8/Ta0AQITLv5kmAZxs0W5086ng=; b=L5G5aiRH/giyGqU4iHJxZvlbXqFGb6EX8I48UdEX+0iuXevBNY7KfpKq xMUFyQUT4zh5vN8UmTwKG7Vw1+B1lzyclx8Sn3sz8bu2kCy0Pw4ahp1fs qSf0a47RWNFjQW/JxecLPh4rtCd9D+VivZa4av4+Tm3MfLJG5yOckewTq VPOZjhIatNzXYlj0H9NpSJSezEGS2z3EHMs0h7IRakR0jr9BP2pFmSWIm OtLp2PdMc8vG1KEo62dEyHociyqCoOPSKpYGfpsocZQyqkySYqIWwUSMk vdMgJ6m4bqkQlfqfKZTmKIVIR+C6eQef8kZZIhb3jr/wmm3GJBz7jXyaB A==; X-CSE-ConnectionGUID: Cier9dDfQwKhMAOggTDO+Q== X-CSE-MsgGUID: 6cskIBPuRRylkFL13tME4g== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253664" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253664" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: dnQSBHdGQyiIU3gz28Geuw== X-CSE-MsgGUID: WPVJXmpPTXaBBH1+yrAx9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445187" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:51 -0800 Subject: [PATCH v7 5/9] x86/realmode: Make the location of the trampoline configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-5-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=3966; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=9qtzvjq4P38gArQTG47VaprUXyQQsZXUwrC2UT2WtRQ=; b=WzLtBWZxcFe/Oa8jx8shc1chTZemiELarjyTDcaS43VC8vR8cPh0TUVpXMI6Gl9YnGxJhzETy VVU70GgkEcSCNbl7ae7JE37/QN6HyD9gYcfe10mWcfpcBmqlZFJNV07 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses a 1MB address space. The trampoline must reside below this 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such a mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction on locating the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation below 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Preserve the default upper bound of 1MB to conserve the current behavior. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes in v2: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 36698cc9fb44..e770ce507a87 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode tra= mpoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; =20 /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata =3D { .reserve_resources =3D reserve_standard_io_resources, .memory_setup =3D e820__memory_setup_default, .dmi_setup =3D dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit =3D SZ_1M, }, =20 .mpparse =3D { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 88be32026768..694d80a5c68e 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) =20 void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit =3D x86_init.resources.realmode_limit; size_t size =3D real_mode_size_needed(); =20 if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) =20 WARN_ON(slab_is_available()); =20 - /* Has to be under 1M so we can execute real-mode AP code. */ - mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); =20 --=20 2.43.0