From nobody Tue Dec 2 03:00:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48E1130DD16; Mon, 17 Nov 2025 17:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399047; cv=none; b=Q3PUxpo52dsUIXDOsaLeIox92dhmmFSy1jVMzFuKWJIUImMLVNEmCcY3RlwUym9B5PKeQpAxuFMChKibSo3iHFoD3+v/KAjh1EsZPrLf6QzpgFu/E++a4F8pOJcGAc8QrudvtaS7Kxp3Bw34DmUtEHngBX3QBGcqo6vic62z+1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399047; c=relaxed/simple; bh=zRO1wpf2tqsGNKVdWvJ6T8jv4jp8KUw+R7a2Geq4m+c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ogkECoE3u+9ZNLtRnhNke1aFFeiYUEVxYneTI+H8QQBH1Nd6XoVIuf/xV5+ixmELEltN5tiBEZMEFPjvllp8oaYC4LuWc2xugP0ZsAgmoQiSBjt4pSYG9VIQBU2uoLSqcr7uTQ7nLvbyCcZyTNOD4CH2swR0YSv1F+q6YSFu6hQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BVkfdz1m; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BVkfdz1m" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399045; x=1794935045; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=zRO1wpf2tqsGNKVdWvJ6T8jv4jp8KUw+R7a2Geq4m+c=; b=BVkfdz1m6Fx2Gn612V7mBenp8W7EHeechnl5avFN/rg1BGgKJ5AYNREX U4Wkrs/uGwY7YSvOzigPs02XbEeU6H1iyhMHpWyariLnFUIDYdgKpak50 BFhV4gUaq53nnAwoNzQ3sMUCc9J30PTSCD/9mGKzBc2RUUpn/o4JBYXhO QpdMgdZEE5kZaViTaiWGNSJYwsF43UNQmxMkwUXypQ3X9E2BYQjEbfILx x3ZZ7dPPDSWSZwsBxDQVQVZjiWBTGzzLZYxj5RJoyAKDjHS7NF10SNju6 Zqf6RFMIhKHoJ10ysUJ01XVJdm/Oa9Yc5W6DNNMVHP4LFqNO+SvMTiTEA w==; X-CSE-ConnectionGUID: 0eX37WGTQPCUwWgnGWJwTQ== X-CSE-MsgGUID: l9HPjPg2TGuWGL9BvwyaBw== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253644" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253644" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 X-CSE-ConnectionGUID: InwnFxShTuew2hOxuxYd7Q== X-CSE-MsgGUID: WwsUpf13RhaXiiGq1K+v5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445173" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:48 -0800 Subject: [PATCH v7 2/9] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-2-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , "Rafael J. Wysocki (Intel)" , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=5163; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=zRO1wpf2tqsGNKVdWvJ6T8jv4jp8KUw+R7a2Geq4m+c=; b=AmzH2HciZW+UBU6ZitpvczwSwWnrU/d1aliqYKXnAzrauBsPX6mXozGsDiaS2zPaCgukhwzCo /yLh2qhfL1fBkjLPXA7+eMsZvEdRb/zj9l7DsDY5BRqSa4/x0DvpqKO X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of the same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin-table, it would require specifying a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox are described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Nodes that want to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Instead, add a `compatible` property that the operating system can use to discover the mailbox. Reviewed-by: Dexuan Cui Reviewed-by: Rob Herring (Arm) Acked-by: Rafael J. Wysocki (Intel) Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - Fixed Acked-by tag from Rafael to include the "(Intel)" suffix. Changes in v6: - Reworded the changelog for clarity. - Added Acked-by tag from Rafael. Thanks! - Added Reviewed-by tag from Rob. Thanks! - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - Specified the version and section of the ACPI spec in which the wakeup mailbox is defined. (Rafael) - Fixed a warning from yamllint about line lengths of URLs. Changes in v4: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes in v3: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes in v2: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 50 ++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup= -mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wak= eup-mailbox.yaml new file mode 100644 index 000000000000..a80d3bac44c2 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbo= x.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake= up + secondary CPUs on Intel processors. It is an alternative to the INIT-!IN= IT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiproc= essor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19= [1]. + + The implementation of the mailbox in platform firmware is described in t= he + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.ht= ml#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-= tdx-virtual-firmware-design-guide.html + + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + + wakeup-mailbox@ffff0000 { + compatible =3D "intel,wakeup-mailbox"; + reg =3D <0x0 0xffff0000 0x1000>; + }; + }; --=20 2.43.0