From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04DBE30C603; Mon, 17 Nov 2025 17:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399045; cv=none; b=M/waY4dXPDW0Ee2KfQ8t2zjHyGlK3zot1AIXFGKaHZYtsv+ImnptM2MxKE/54x4BVJ1scNlBOJWa0poOi7oAB1dWqjrYlp7dXIOOXo/iqW+puDca8LIffromHM6dAk019VxEC7ouWZ40sAAzOcSu5tp1yKykBkinR3Bye2CWcCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399045; c=relaxed/simple; bh=jfDFGm1JQBFAv0lknTiR+fGMBLG9xKp8BRi0BuGqsT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K7bJf7dnurT201R70eEUwkZJd9PwBitW4Nsn863V73vDmqSpXv9BP3LyhTRM7AsjVsoAeXJzT1Swh/+OToqOZtnGw3GCpY9YijCA7GeLv3Xf2ew8lKU/CLFPwMqsXEVMQcpvovgoF1flGx2lpkYaXXRwtY7xZHz48sOC5uOXtuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=d2usAj6e; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="d2usAj6e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399043; x=1794935043; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=jfDFGm1JQBFAv0lknTiR+fGMBLG9xKp8BRi0BuGqsT8=; b=d2usAj6e9u7vaDZHzjSigPVD0ImlEs+kv8nIQfgmL1fpwNBVCIVNrP6Z PPPqsALpBC/Yw7Ps7T1AqbZx3YM5mJ8oAHDzx323cSoqbC9hEAtJjrmgb w0Wj+kagq4IFCxGZk9VjB0g4WWBAhqdTosWbJA7+xQluaOFlfweCVQ9Xe 0hQOl3SZMqme9WPmPlfpHnEWuV0clks2vhGlWAR5St1BhbdSq8psZX1dk cyQaLwiHSdodmrWOvcAcfwa2HXIhSG7i7tkAN/H4gyeRmaoNXXlNJkAk7 W5zBAwOcARn7hJpbCbum+8NEyv9KdZQbwCRqv+Ys7GH728JVWUwLE+H0f A==; X-CSE-ConnectionGUID: 3tbYLBpRSeabCXhyHOX8Mg== X-CSE-MsgGUID: nniIbfeaSQiLKWNiYRs58A== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253638" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253638" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 X-CSE-ConnectionGUID: iOXDyFimQ5aKT7QpxKhLEg== X-CSE-MsgGUID: 5qYTIB5RSGyiZK7crcLciA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445170" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:47 -0800 Subject: [PATCH v7 1/9] x86/acpi: Add functions to setup and access the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-1-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=3044; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=jfDFGm1JQBFAv0lknTiR+fGMBLG9xKp8BRi0BuGqsT8=; b=ZUmWD/ItY6KcHAS/APAhvjsEjKEZ1u4qaM7PMQCgP4XSBeF6kD+8KE9YC0Yp0paICrGY5ZfoV s4hV1mE9LTUCvLMxQAjiJeTRk4dE8BjQU9iBoNkitYWvqdeaXkvzhUc X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Systems that describe hardware using DeviceTree graphs may enumerate and implement the wakeup mailbox as defined in the ACPI specification but do not otherwise depend on ACPI. Expose functions to setup and access the location of the wakeup mailbox from outside ACPI code. The function acpi_setup_mp_wakeup_mailbox() stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. The function acpi_madt_multiproc_wakeup_mailbox() returns a pointer to the mailbox. Signed-off-by: Ricardo Neri Acked-by: Rafael J. Wysocki (Intel) --- Changes in v7: - Moved function declarations to arch/x86/include/asm/acpi.h - Added stubs for !CONFIG_ACPI. - Do not use these new functions in madt_wakeup.c. - Dropped Acked-by and Reviewed-by tags from Rafael and Dexuan as this patch changed. Changes in v6: - Fixed grammar error in the subject of the patch. (Rafael) - Added Acked-by tag from Rafael. Thanks! - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Squashed the two first patches of the series into one, both introduce helper functions. (Rafael) - Renamed setup_mp_wakeup_mailbox() as acpi_setup_mp_wakeup_mailbox(). (Rafael) - Dropped the function prototype for !CONFIG_X86_64. (Rafael) Changes in v3: - Introduced this patch. Changes in v2: - N/A --- arch/x86/include/asm/acpi.h | 10 ++++++++++ arch/x86/kernel/acpi/madt_wakeup.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index a03aa6f999d1..820df375df79 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -182,6 +182,9 @@ void __iomem *x86_acpi_os_ioremap(acpi_physical_address= phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap #endif =20 +void acpi_setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); + #else /* !CONFIG_ACPI */ =20 #define acpi_lapic 0 @@ -200,6 +203,13 @@ static inline u64 x86_default_get_root_pointer(void) return 0; } =20 +static inline void acpi_setup_mp_wakeup_mailbox(u64 addr) { } + +static inline struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeu= p_mailbox(void) +{ + return NULL; +} + #endif /* !CONFIG_ACPI */ =20 #define ARCH_HAS_POWER_INIT 1 diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 6d7603511f52..82caf44b45e3 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -247,3 +247,14 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, =20 return 0; } + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr =3D mailbox_paddr; + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} + +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; +} --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48E1130DD16; Mon, 17 Nov 2025 17:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399047; cv=none; b=Q3PUxpo52dsUIXDOsaLeIox92dhmmFSy1jVMzFuKWJIUImMLVNEmCcY3RlwUym9B5PKeQpAxuFMChKibSo3iHFoD3+v/KAjh1EsZPrLf6QzpgFu/E++a4F8pOJcGAc8QrudvtaS7Kxp3Bw34DmUtEHngBX3QBGcqo6vic62z+1Q= ARC-Message-Signature: i=1; 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d="scan'208";a="195445173" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:48 -0800 Subject: [PATCH v7 2/9] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-2-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , "Rafael J. Wysocki (Intel)" , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=5163; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=zRO1wpf2tqsGNKVdWvJ6T8jv4jp8KUw+R7a2Geq4m+c=; b=AmzH2HciZW+UBU6ZitpvczwSwWnrU/d1aliqYKXnAzrauBsPX6mXozGsDiaS2zPaCgukhwzCo /yLh2qhfL1fBkjLPXA7+eMsZvEdRb/zj9l7DsDY5BRqSa4/x0DvpqKO X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of the same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin-table, it would require specifying a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox are described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Nodes that want to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Instead, add a `compatible` property that the operating system can use to discover the mailbox. Reviewed-by: Dexuan Cui Reviewed-by: Rob Herring (Arm) Acked-by: Rafael J. Wysocki (Intel) Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - Fixed Acked-by tag from Rafael to include the "(Intel)" suffix. Changes in v6: - Reworded the changelog for clarity. - Added Acked-by tag from Rafael. Thanks! - Added Reviewed-by tag from Rob. Thanks! - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - Specified the version and section of the ACPI spec in which the wakeup mailbox is defined. (Rafael) - Fixed a warning from yamllint about line lengths of URLs. Changes in v4: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes in v3: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes in v2: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 50 ++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup= -mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wak= eup-mailbox.yaml new file mode 100644 index 000000000000..a80d3bac44c2 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbo= x.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake= up + secondary CPUs on Intel processors. It is an alternative to the INIT-!IN= IT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiproc= essor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19= [1]. + + The implementation of the mailbox in platform firmware is described in t= he + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.ht= ml#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-= tdx-virtual-firmware-design-guide.html + + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + + wakeup-mailbox@ffff0000 { + compatible =3D "intel,wakeup-mailbox"; + reg =3D <0x0 0xffff0000 0x1000>; + }; + }; --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2ADD33E358; Mon, 17 Nov 2025 17:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399048; cv=none; b=U7y46W49CW4eKr62e8EqMtAX6ft0iUNMmQ1fp7AQ8bdyBQkfQ6Thk+CcMZeyDk/ovtV/iVqEwuW+D3//Y7tRD6tSy7/LNh0/KKF3ZJoP0NHycCOndLh2d/bM91Wr7pgb/91DPcHcd6PlpQ5LsypKRB6uxEZVaQugHoiTGPDrbbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399048; c=relaxed/simple; bh=hImYegn89ks6oWTxTrLfTgc/HpXwNha69JCDIRS8ZHc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OvlNZmfI5I40JZOGlDsw+yLULlaOIhArddBpIK10rBqH43VA+qiij+Y8pTxWFpqRPMDRNTXeSqY2n8EAeKMtJFHq1NLD++m9monifp/dquy5y3SL/RckGorXBHWEyTTGVA6jVshOGjb4KnExI/4TiFqffad39m29SXrn4VEvAMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nFBOpUTv; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nFBOpUTv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399047; x=1794935047; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=hImYegn89ks6oWTxTrLfTgc/HpXwNha69JCDIRS8ZHc=; b=nFBOpUTvf6aw4ygLdUaHp95IINswcnKMHd5k06opCMntpGBtq4CujfDT T3WP2yYXNnPGLnzi9qRA8plJpMljV0qzRJfwlHSh/7Q0+TNInMEBgBSUc 6pnPu7fb2+cb/MR9+DOw1k6Nv2aylTyh878toHtM7+bzyPdgI/oQYkqn7 gwxS6w6PPwAp8mVFIpIxIS/JypnJ1tHVCNv+vnjaB0hVZBUD0lupNkAn/ 3KvuCKSTVQBs28mb0U6qjB921f9T6M350p/BTMCKjALj3rydxd/EousET auxRyd6EJZLU45B433FrzbqmSFw2KufS3kJKProazCXcEHmIMpyXZClGZ g==; X-CSE-ConnectionGUID: 1DBmwSx+SiCyrqI2uoW+Fw== X-CSE-MsgGUID: T4nuJtAhS6GmiI178tKOmg== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253651" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253651" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: NRjEOdRxTzy38IdDuGoL5g== X-CSE-MsgGUID: qkf7fg0jRQyqBV5ng7YGkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445178" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:49 -0800 Subject: [PATCH v7 3/9] x86/dt: Parse the Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-3-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=4499; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=hImYegn89ks6oWTxTrLfTgc/HpXwNha69JCDIRS8ZHc=; b=mpyyVT5T0Qbr5QjBwb6+sOXPJC302LOKfEzLeXAWzi2jSvWG1UL4DOa6DbMavx8jclMDaUucb +IX4141YFV+Dy5E6ijif5pvWSLXhTlRLzHr/h00k/qEfFp678cxqLTk X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The Wakeup Mailbox is a mechanism to boot secondary CPUs on systems that do not want or cannot use the INIT + StartUp IPI messages. The platform firmware is expected to implement the mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. It is also expected to publish the mailbox to the operating system as described in the corresponding DeviceTree schema that accompanies the documentation of the Linux kernel. Reuse the existing functionality to set the memory location of the mailbox and update the wakeup_secondary_cpu_64() APIC callback. Make this functionality available to DeviceTree-based systems by making CONFIG_X86_ MAILBOX_WAKEUP depend on either CONFIG_OF or CONFIG_ACPI_MADT_WAKEUP. do_boot_cpu() uses wakeup_secondary_cpu_64() when set. It will be set if a wakeup mailbox is enumerated via an ACPI table or a DeviceTree node. For cases in which this behavior is not desired, this APIC callback can be updated later during boot using platform-specific hooks. Reviewed-by: Dexuan Cui Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - #included asm/acpi.h to reflect the updated declaration of the needed functions. - (Kept Reviewed-by tag from Dexuan, as this single change is trivial.) Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - Made CONFIG_X86_MAILBOX_WAKEUP depend on CONFIG_OF or CONFIG_ACPI_ MADT_WAKEUP. Changes in v4: - Look for the wakeup mailbox unconditionally, regardless of whether cpu@N nodes have an `enable-method` property. - Add a reference to the ACPI specification. (Rafael) Changes in v3: - Added extra sanity checks when parsing the mailbox node. - Probe the mailbox using its `compatible` property - Setup the Wakeup Mailbox if the `enable-method` is found in the CPU nodes. - Cleaned up unneeded ifdeffery. - Clarified the mechanisms used to override the wakeup_secondary_64() callback to not use the mailbox when not desired. (Michael) - Edited the commit message for clarity. Changes in v2: - Disabled CPU offlining. - Modified dtb_parse_mp_wake() to return the address of the mailbox. --- arch/x86/kernel/devicetree.c | 47 ++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index dd8748c45529..318acaecb5ca 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -18,6 +18,7 @@ #include #include =20 +#include #include #include #include @@ -125,6 +126,51 @@ static void __init dtb_setup_hpet(void) #endif } =20 +#if defined(CONFIG_X86_64) && defined(CONFIG_SMP) + +#define WAKEUP_MAILBOX_SIZE 0x1000 +#define WAKEUP_MAILBOX_ALIGN 0x1000 + +/** dtb_wakeup_mailbox_setup() - Parse the wakeup mailbox from the device = tree + * + * Look for the presence of a wakeup mailbox in the DeviceTree. The mailbo= x is + * expected to follow the structure and operation described in the Multipr= ocessor + * Wakeup Structure of the ACPI specification. + */ +static void __init dtb_wakeup_mailbox_setup(void) +{ + struct device_node *node; + struct resource res; + + node =3D of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox"); + if (!node) + return; + + if (of_address_to_resource(node, 0, &res)) + goto done; + + /* The mailbox is a 4KB-aligned region.*/ + if (res.start & (WAKEUP_MAILBOX_ALIGN - 1)) + goto done; + + /* The mailbox has a size of 4KB. */ + if (res.end - res.start + 1 !=3D WAKEUP_MAILBOX_SIZE) + goto done; + + /* Not supported when the mailbox is used. */ + cpu_hotplug_disable_offlining(); + + acpi_setup_mp_wakeup_mailbox(res.start); +done: + of_node_put(node); +} +#else /* !CONFIG_X86_64 || !CONFIG_SMP */ +static inline int dtb_wakeup_mailbox_setup(void) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_X86_64 && CONFIG_SMP */ + #ifdef CONFIG_X86_LOCAL_APIC =20 static void __init dtb_cpu_setup(void) @@ -287,6 +333,7 @@ static void __init x86_dtb_parse_smp_config(void) =20 dtb_setup_hpet(); dtb_apic_setup(); + dtb_wakeup_mailbox_setup(); } =20 void __init x86_flattree_get_config(void) --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D779533E342; Mon, 17 Nov 2025 17:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399048; cv=none; b=XvZmZJxQvPOOafKGEzYkRL3yytO9/zVD08+CJSJsYgEVHaUp7rnehPw3pP7xFwvqywrNhR/0F1OBhrau9XQ8ek54is6+AYQa0fQu11JkoBRmUtcYP5XNm63gxGPo1aktSQJPaOdAUZ0VZnYrllM0mKx1GG5JBUZGu3BQIvR3r28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399048; c=relaxed/simple; bh=Ek8hMgumVPS1aDmufwBtX1sGfZaxTHAb1Zpjtl5/pno=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kk1HVQo08BHTq8LoCcAtD4WQBOGk/SdsSw2NEV+3InpEiJbot6UBssdXCOwru/+QdLbOsH6TFWB/5XgOt9/toDEEgKolX7kq7SN5GKi9m0Ezxe0ddQna7cvUo9LjCl1QCZEssstPuJ0eDY/PO2av/2tESgdEap/AnPBHdPLr228= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=V7tFJcr+; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V7tFJcr+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399046; x=1794935046; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Ek8hMgumVPS1aDmufwBtX1sGfZaxTHAb1Zpjtl5/pno=; b=V7tFJcr+icUkNTRzAfJFuFVVA9i35rUl9zdzGHZdPylSZ9u6vSFNQ6bM ZxlQv5eaT5EUeN7Yyy4PbKxkTQatiLFpxv/NcHBeF2fHNcxEhGWtGZ+Ub GhIHMqZfMCxkqMEuVSPS5w9j4i7xU5SsxISbm2qxU4cK2oqfdjYXQgqPp q31aiJAKPrz6egVw+boDVsz6lo1E3LcUjit0VEhmQb3+ATDjboy7xPVSQ gmaZkpT/ZwHYpr02/9HxPGnP4QvfAtBiprBAroyulDc1chadt85QpLGSS RxFGAAYe2EYt1Lrz6ThJwetBKK7yXZ7DGvzlWo1D/yHZWCVZeGKZrEaHy w==; X-CSE-ConnectionGUID: fmAk7CZkSd201lhqFBtAcw== X-CSE-MsgGUID: C9DsS7qDQ/OpA5KfBN7HWw== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253658" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253658" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: sos+IfFoTjaOmMHs+wq49A== X-CSE-MsgGUID: XJwTCXvESEOOjDTTn6Fbdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445182" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:50 -0800 Subject: [PATCH v7 4/9] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-4-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=2310; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=M7UewUod3MOK5zJCQXv7Tn4QEwiTQKiYaOZWHnv+7es=; b=KyEQkku2t6wzyn+W+jpSOJ1YM3FCeR59qrAeQUBydFxp5iwYZuYjaZ7dY17Wb4wJQwOLnazf6 CHlJBdmoTBaCgtPJx0oeo7gjXI7QsJ571rIE4/HMrHl/O+wxFsss/Vo X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_init_platform() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the settings of real mode memory in two places. Also, both functions are called much earlier than x86_platform.realmode_init() (via an early_initcall), where the real_mode_header is needed. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX a environment. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - None Changes in v6: - Corrected reference to hv_vtl_init_platform() in the changelog. (Dexuan) - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Edited the commit message for clarity. Changes in v2: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 042e8712d8de..e10b63b7a49f 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -65,6 +65,7 @@ void __init hv_vtl_init_platform(void) =20 x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; @@ -244,7 +245,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - real_mode_header =3D &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); =20 return 0; --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAF8B33EAE6; Mon, 17 Nov 2025 17:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399049; cv=none; b=WDxeEJ8IkCw5/ej6bAw4PcxT5Anx4bZLOvO3hYnNRyIDiDs1CxIs9Iz8kh48cHWx2gKkQkRP80TCJ/YcyODjRO7cJ9FWdJnRWIjMDvaKYNaPt8Ter9rz8RrYudM/GIDUwtUk5Z4oN6gM65EJcvqZu1uYhBY04ioSJXg7q+CqLgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399049; c=relaxed/simple; bh=WIzwNdd1k37krjUiu8/Ta0AQITLv5kmAZxs0W5086ng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Md83fk2GGwreWg3GzbNnDPKHL1wlnB7vePZ0IiMVetw286BlJtGN+OHG6YEnDxs9v8SBMmyuHuxy31YHKtH35sxLeC/ggDnUuGpuolCNZw0RN0BdqD98BibhTOkdFIZINCpWS2xKdEZJ9wfSNkX9XgP8nD2kKPDI7R2nIS5wwwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L5G5aiRH; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L5G5aiRH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399048; x=1794935048; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=WIzwNdd1k37krjUiu8/Ta0AQITLv5kmAZxs0W5086ng=; b=L5G5aiRH/giyGqU4iHJxZvlbXqFGb6EX8I48UdEX+0iuXevBNY7KfpKq xMUFyQUT4zh5vN8UmTwKG7Vw1+B1lzyclx8Sn3sz8bu2kCy0Pw4ahp1fs qSf0a47RWNFjQW/JxecLPh4rtCd9D+VivZa4av4+Tm3MfLJG5yOckewTq VPOZjhIatNzXYlj0H9NpSJSezEGS2z3EHMs0h7IRakR0jr9BP2pFmSWIm OtLp2PdMc8vG1KEo62dEyHociyqCoOPSKpYGfpsocZQyqkySYqIWwUSMk vdMgJ6m4bqkQlfqfKZTmKIVIR+C6eQef8kZZIhb3jr/wmm3GJBz7jXyaB A==; X-CSE-ConnectionGUID: Cier9dDfQwKhMAOggTDO+Q== X-CSE-MsgGUID: 6cskIBPuRRylkFL13tME4g== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253664" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253664" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: dnQSBHdGQyiIU3gz28Geuw== X-CSE-MsgGUID: WPVJXmpPTXaBBH1+yrAx9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445187" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:01 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:51 -0800 Subject: [PATCH v7 5/9] x86/realmode: Make the location of the trampoline configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-5-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=3966; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=9qtzvjq4P38gArQTG47VaprUXyQQsZXUwrC2UT2WtRQ=; b=WzLtBWZxcFe/Oa8jx8shc1chTZemiELarjyTDcaS43VC8vR8cPh0TUVpXMI6Gl9YnGxJhzETy VVU70GgkEcSCNbl7ae7JE37/QN6HyD9gYcfe10mWcfpcBmqlZFJNV07 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses a 1MB address space. The trampoline must reside below this 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such a mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction on locating the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation below 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Preserve the default upper bound of 1MB to conserve the current behavior. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes in v2: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 36698cc9fb44..e770ce507a87 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode tra= mpoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; =20 /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata =3D { .reserve_resources =3D reserve_standard_io_resources, .memory_setup =3D e820__memory_setup_default, .dmi_setup =3D dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit =3D SZ_1M, }, =20 .mpparse =3D { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 88be32026768..694d80a5c68e 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) =20 void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit =3D x86_init.resources.realmode_limit; size_t size =3D real_mode_size_needed(); =20 if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) =20 WARN_ON(slab_is_available()); =20 - /* Has to be under 1M so we can execute real-mode AP code. */ - mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); =20 --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F32033EB0E; Mon, 17 Nov 2025 17:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; 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a="69253667" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253667" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: MjMaK/ANShSFMibi2N1gtA== X-CSE-MsgGUID: Ql4FIDwrRDilsS2B9CvApA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445191" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:52 -0800 Subject: [PATCH v7 6/9] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-6-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=2691; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=DbIhi3r9e2yQrYypAYPc0r2FmkGNsXGhWQfmQPK9E1c=; b=2dFxNnvnyBjABfQPzjg1b1dQC9Ee08wvBbR+W6iqs1oDzxAoYJxMJZ2KzWjSmAgHTKAFuEcDK 5KzvONI3ne/C964PsmtNaSiVhvg48C6T/hJHvfkO0NWiNk8Ptq91Jcc X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls nor the INIT assert, de-assert, plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes in v2: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index e10b63b7a49f..ca0d23206e67 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -63,9 +63,14 @@ void __init hv_vtl_init_platform(void) */ pr_info("Linux runs in Hyper-V Virtual Trust Level %d\n", ms_hyperv.vtl); =20 - x86_platform.realmode_reserve =3D x86_init_noop; - x86_platform.realmode_init =3D x86_init_noop; - real_mode_header =3D &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit =3D SZ_4G; + } else { + x86_platform.realmode_reserve =3D x86_init_noop; + x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E392A33F379; Mon, 17 Nov 2025 17:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399051; cv=none; b=YTSeUlxHycgDBioYN4lKL9f00qBZjkRcBGUYNw99gO3VuYREbqHU50O3Ly0sJfopDg8gqwXmTpR8vIHAt4onjEwAQjJcqO5y1YBj2PesCcCV+llZJNVeXhR3aB/Bl4shGwyZYdLlK/+9IFzLXpo80zjr5oAGJFNVptmIYV9pdfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399051; c=relaxed/simple; bh=4R7LgMkRG5wJg2Ahbn+7dl/q4jcDQhLIjGU3Bl7isGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X8wblRqXoqVuD94FsPmv0otv/el5Zqksq9lCkjK4Os5gspkwjpvY+b5UvHBKHGREPQTVeFqrKoef0HE9flvei5P7SzZYi4P0aYdCj4Dpc6AaFRvZ5spQ25WqtduZG4lNLDZuYNvacdRaCsl/JtWIs/5nBYTVif7doTJ/tPrWlbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nQqqhPrN; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nQqqhPrN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399049; x=1794935049; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=4R7LgMkRG5wJg2Ahbn+7dl/q4jcDQhLIjGU3Bl7isGo=; b=nQqqhPrNaljON2YGleFKPjQ4pEHuRRoPVBcVm4Z1UBnmmH9qzi1egKdH sNmQT4za8pCV5JdgPCNuqkBbLZpKv1y969QUdrmQDsUnfxfTPOZGWUtpT bLhLvOJcLkZeu8rv+T0ZITOm7m/cj9dAEieMyRh7HSFKtUAhmX+NZxDY4 4Nf2J58svGyrJlsR/ATPvj6z9UxG1ncbublT7Xk9f7Q3J+xDJBGvqlX1V u/9FjejCJS+n/RzcGfWgG1m+ivqNMKIvVWfNuPKtVm16JMF6EgAR99AP9 cpMsX6svehdddPm++kX9DuRggilQCxbnaEpUhJMqx5pPSSds4P0zzkz35 w==; X-CSE-ConnectionGUID: 3kXBKmNTQmWj0ycxSkhPBQ== X-CSE-MsgGUID: Mm4jk0BcQQiyx5nwgL4gAw== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253673" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253673" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 X-CSE-ConnectionGUID: NXq6yhtdTVW/kc9h/xYzUg== X-CSE-MsgGUID: xTZtYLSuQm2uFNfBPnVBCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445197" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:53 -0800 Subject: [PATCH v7 7/9] x86/acpi: Add a helper get the address of the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-7-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=2194; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=4R7LgMkRG5wJg2Ahbn+7dl/q4jcDQhLIjGU3Bl7isGo=; b=hwMPtBtasp6xE9Vp+UUnIulXQakGWFrUb5FM38R8iqAE+DKtlOv1kHREYb49rXuucnfflmWOE lCwileUX7EACqFuSqknGHHF/FOKluW2fVKOxdLc9/KYSWtt69wk6xDv X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= A Hyper-V VTL level 2 guest in a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function to retrieve the address. Suggested-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes in v7: - Moved the added function to arch/x86/kernel/acpi/madt_wakeup.c - Dropped Reviewed-by tags from Dexuan and Michael as this patch changed. Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Renamed function to acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Introduced this patch Changes in v2: - N/A --- arch/x86/include/asm/acpi.h | 6 ++++++ arch/x86/kernel/acpi/madt_wakeup.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 820df375df79..c4e6459bd56b 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -184,6 +184,7 @@ void __iomem *x86_acpi_os_ioremap(acpi_physical_address= phys, acpi_size size); =20 void acpi_setup_mp_wakeup_mailbox(u64 addr); struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); +u64 acpi_get_mp_wakeup_mailbox_paddr(void); =20 #else /* !CONFIG_ACPI */ =20 @@ -210,6 +211,11 @@ static inline struct acpi_madt_multiproc_wakeup_mailbo= x *acpi_get_mp_wakeup_mail return NULL; } =20 +static inline u64 acpi_get_mp_wakeup_mailbox_paddr(void) +{ + return 0; +} + #endif /* !CONFIG_ACPI */ =20 #define ARCH_HAS_POWER_INIT 1 diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 82caf44b45e3..48734e4a6e8f 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -258,3 +258,8 @@ struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_= wakeup_mailbox(void) { return acpi_mp_wake_mailbox; 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17 Nov 2025 09:04:02 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:54 -0800 Subject: [PATCH v7 8/9] x86/hyperv/vtl: Mark the wakeup mailbox page as private Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-8-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=2732; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=kZxiUfbccXocGJCMBY33QWQ1dcE/RS77GqicHi6UIZo=; b=Ey7LB6F8aVrJYDbalvaBYqqcH3QTS980cBALIfhJWRjoeWD60eBKHhkW487ecGUTuu27hYAub XGjDXH4L9zTA3WFzxGVtV7iGAdxagFkTcbzdwlEvzcV+KJ7eqZkjMW2 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changed since v7: - Dropped check for !CONFIG_X86_MAILBOX_WAKEUP. The symbol is no longer valid and now we have a stub for !CONFIG_ACPI. - Dropped Reviewed-by tags from Dexuan and Michael as this patch changed. Changes in v6: - Fixed a compile error with !CONFIG_X86_MAILBOX_WAKEUP. - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Updated to use the renamed function acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes in v2: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index ca0d23206e67..812d8a434966 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -6,6 +6,7 @@ * Saurabh Sengar */ =20 +#include #include #include #include @@ -54,6 +55,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unus= ed *cmd) hv_vtl_emergency_restart(); } =20 +static inline bool within_page(u64 addr, u64 start) +{ + return addr >=3D start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr =3D acpi_get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { /* @@ -66,6 +79,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit =3D SZ_4G; + x86_platform.hyper.is_private_mmio =3D hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; --=20 2.43.0 From nobody Tue Dec 2 02:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9BC340298; Mon, 17 Nov 2025 17:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399054; cv=none; b=EaCBbAXuwatyXZM/FD1f+nHAxbuvP1yQSoDz9D3X2nhGTqjAmYa4df35fL87lykXWUh9bSUnC0tKa2smOovDhU65zBELt7rsLpkuQEfjhwPHALR3oeFJHDTgFdSWxbf3EOcNOlRAycifVSsNmYP5NOriei5GZWAn5rDMbae0gf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763399054; c=relaxed/simple; bh=bf6T0fhOw4XHjcwb9k8rbX5w18M9RMmSiJbS2bAV1QA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PpOPn9vobC+6tlbtFMT7YhIMRciwemoT7p+GVCBjVRn+TWl55iIMc4FJLsSF9zDggJLhtwyTvd95yidYtIv6M4IvLKPpOMqXrTDpMWCI/6wTwqYx7yQuvAEpcquebYNnBLvA9K0ahpsJeUrzgHdmsymHuIu7cy0+V5Sg0HbP+QM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=i4r5D3aR; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="i4r5D3aR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763399051; x=1794935051; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=bf6T0fhOw4XHjcwb9k8rbX5w18M9RMmSiJbS2bAV1QA=; b=i4r5D3aRRsAP0ph2PG/Aurw/0QCevjkYngS2Bat+Rqe8R4MSUfN+ifKb a1c1bIJJ2bZmrl9+HvC21d4H0SmwsCXZMETdGZTVHmUVoyBvAO0NoK5iE d7rO3WrgUm6PzxgvjnRm/2XZi7Hza1zo58im/MR+YGr8uaTb/cBvI/+YR t07oVXN3QAGFiB1ZydN/GX8ujPQ0bstFJZqRh3NDSxFdE+d49Abqn/Qck dNla+CNRmcUunkXw5c/To/rBRdW0cskMy7w+3YgHcYmoJmUGFPx9wGXWj B5aSIusPcZ8ghoDyMDPoKt7eeOJ3Zt8clnb+4Lis1oqF+Ji7nnZYFap/4 Q==; X-CSE-ConnectionGUID: nF2q8AgcQuKkKEmRXVcSpA== X-CSE-MsgGUID: JMu5l8e4Rr2p4rQjbnEgBQ== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="69253679" X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="69253679" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:03 -0800 X-CSE-ConnectionGUID: OxyMCbJER6OSTQFsU+DbzA== X-CSE-MsgGUID: 5iLUmNrMTxGJsbZSGFxAtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,312,1754982000"; d="scan'208";a="195445206" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 09:04:02 -0800 From: Ricardo Neri Date: Mon, 17 Nov 2025 09:02:55 -0800 Subject: [PATCH v7 9/9] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251117-rneri-wakeup-mailbox-v7-9-4a8b82ab7c2c@linux.intel.com> References: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> In-Reply-To: <20251117-rneri-wakeup-mailbox-v7-0-4a8b82ab7c2c@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763398999; l=2005; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=bf6T0fhOw4XHjcwb9k8rbX5w18M9RMmSiJbS2bAV1QA=; b=kRyEvBJR2Vzl6/jihLmGUV2JKi2Su99AgObs1zV1rqoeh3e5TGl9RJSj7Xks4gOgIpVsZazyX 8OO6X+KgrElDAEY5WzNepJR7rj6coyiBwdIvvfjX2CfN6DR9nCHZVqL X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox. The firmware enumerates the mailbox via either an ACPI table or a DeviceTree node. If the wakeup mailbox is present, the kernel updates the APIC callback wakeup_secondary_cpu_64() to use it. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Unconditionally use the wakeup mailbox in a TDX confidential VM. (Michael). - Edited the commit message for clarity. Changes in v2: - None --- arch/x86/hyperv/hv_vtl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 812d8a434966..431218ad6624 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -265,7 +265,15 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); + /* + * TDX confidential VMs do not trust the hypervisor and cannot use it to + * boot secondary CPUs. Instead, they will be booted using the wakeup + * mailbox if detected during boot. See setup_arch(). + * + * There is no paravisor present if we are here. + */ + if (!hv_isolation_type_tdx()) + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cp= u); =20 return 0; } --=20 2.43.0