From nobody Mon Feb 9 01:21:26 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C35CB3019D6 for ; Sat, 15 Nov 2025 14:14:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216067; cv=none; b=oe5Df9sCAVabnFt3Dbjdb6nmH3mgV0A06PKFQaHVZsIIp9ao/BKHH8+GmRDK91yMPbS4aFJrZ2Sincvpezk6/aySBkTrIj1EXAHXJF7lccLhnACs+DX2gWMt4YxOTytqtJrnyfKOHckhATwy7N7gepDBP7jElPI8uMwZw6VTbH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216067; c=relaxed/simple; bh=ARCr2MF2PDcGudo+PTuVZew5/GiYdu3vBhL2diGFAU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C6xBIhQRO84B7triTGXH6kqtc/3rFfgRJnsmRPG56wUz+e0SUcg6bmhsPbzE3TkJJE9Bejug0QAX16Jg6xxkyqkDwBEOJKPSd0kJe24esRhAQ6eS0c3B8cTy62CZPwz0RpnsVbtFeLV3DYHTF47ycKjE3NxvjV57+MyvpqIWGIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MNfDnyqa; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MNfDnyqa" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-640bd9039fbso4934309a12.2 for ; Sat, 15 Nov 2025 06:14:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216063; x=1763820863; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SznPGrtr2XDooq13sk6Kgg+QMqAR2LlCpjlNsch42gA=; b=MNfDnyqa6QO/ei3ZP0C9QEyeeRYz7fM3j/5U2AMlPRPgw319DDNBk8A6uNNET9imrd CVuwhJvVvxlc+ymKmCcoJMkyZuQNsYDZlPBfWNEHVFLGPVQe7qeSepXzQznJayVuimFt Fg406QROOSMBHKn/lz7d3QoTJ1OQgcr8Mv9/m6Ft8JGbmdWzhjMxfNVT8cGE844vFETJ 7bcnZKDFznaTEzSxv2WYEbJ+aZijUg+LVkRMNxE5eqWZgVs5+86mmPCBun0JIurWzdc1 11fFp+BUw1HruJGC6bpBAZPSjxtn41hhvyxQOVKp6OxpXZCH3y/Pk4gLdDxxLcneL0Ga bXZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216063; x=1763820863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SznPGrtr2XDooq13sk6Kgg+QMqAR2LlCpjlNsch42gA=; b=bfOD+n0+gZZITBL80mW9lpZuCLTlZl+/1d7eaB6F0uxvfCOhw+UhoSLfGJghINx/A0 Mhv4DnVDNX0t9GWe0PfOaqcoCX6MPMGUMm8LgrWJ5gGWg9Bbq08PECMQV7lRaOJ6BukB BWvKjzk2Li++r1nzv1JtqPnXizq2WNn3Qinv5noY4AbKuz47JTV2PunoTQUH6zlw0fxN 5MeEziaIby5gELvlzMT8OKJoMospDHqIPliRHCTsHzWyz5d5mFuqhLxJL/vF94eQnnIW vQbjiAPI8xj87BFiNqzqmLCzmYclUryL6g0x2tBVMNi7YN2ksZVIyQU731gRmm6m7J4T fg7w== X-Forwarded-Encrypted: i=1; AJvYcCU1jHrZ2iRoHp9wS+c88M7pB3LWnWsYZvWtJurbUikxRGKJNEfNNXIN0/Kro0nLDEAoYcu1LZ18e5T6Yhw=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/knRnCksdPOWa86ErQaf5yWRJ3bv/xcxX63U0zfcCkHfqJb6R dwFnP/2xYNS+0+8jjG50SurLHTfyMrzO6v8GX3WyfZUDqELUNk2uOlZ7 X-Gm-Gg: ASbGncsruLZGuyZjdf1LBH+VQfgAenzibj2NLQUdOUMEH2vqhp20DN7vC/5vSSUZGVO puG4FB6kpLQd0ExY80lBtefTBgXY+rH9VwCMS+UIegaA3gN9gc6O7+ND+FFzZwNr4paH+vyLfTO felsG53J5QcUGkDqVXhvWsXyoCycik8cX01VAh4pRQZ4PqxEghFC0GR8SCzvFYRbeHr2si1vdPk kJ7hMhOYfrrDOwxjjNWpQrGYSqVPZAZOrRgJn8bBO+oejFbcVtZnqVPY4yKNn7Zu62MwUd2s12S +06SUY5HciNXVw2X654VQg44LTb0H+qW1JZ6HdK0lbH798InyQppopw9U2uewIj8nZ+haCCefUl CAINBE8aDBlIqQI75Glvl6udJMuDLpCUIMPbaDLl6LIm2dq3oCpdRS28cijfn7WuuPlTPSvNaB+ NRiEXYJB13lWgdyEU7vc1ItQhgOHTH/ndcBdB3AQhKXRRaud4f/MOHPA5K X-Google-Smtp-Source: AGHT+IGNZo/U7zY8Q07lDbxVpkIabIMsA3romzMD93FNBaHxF7DsQi/nyue3LGz4eYZpXchvaLYh/g== X-Received: by 2002:a17:907:3d0b:b0:b39:57ab:ec18 with SMTP id a640c23a62f3a-b736794a6b3mr650833866b.45.1763216062968; Sat, 15 Nov 2025 06:14:22 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:22 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 7/7] drm/sun4i: switch DE33 to new bindings Date: Sat, 15 Nov 2025 15:13:47 +0100 Message-ID: <20251115141347.13087-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that everything is in place, switch DE33 to new bindings. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 130 +++++++++++++++------------- drivers/gpu/drm/sun4i/sun8i_mixer.h | 10 +-- 2 files changed, 71 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index fde3b677e925..da213e54e653 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -24,6 +25,7 @@ #include =20 #include "sun4i_drv.h" +#include "sun50i_planes.h" #include "sun8i_mixer.h" #include "sun8i_ui_layer.h" #include "sun8i_vi_layer.h" @@ -256,7 +258,6 @@ static void sun8i_mixer_commit(struct sunxi_engine *eng= ine, { struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); u32 bld_base =3D sun8i_blender_base(mixer); - struct regmap *bld_regs =3D sun8i_blender_regmap(mixer); struct drm_plane_state *plane_state; struct drm_plane *plane; u32 route =3D 0, pipe_en =3D 0; @@ -293,16 +294,16 @@ static void sun8i_mixer_commit(struct sunxi_engine *e= ngine, route |=3D layer->index << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); pipe_en |=3D SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); =20 - regmap_write(bld_regs, + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), SUN8I_MIXER_COORD(x, y)); - regmap_write(bld_regs, + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), SUN8I_MIXER_SIZE(w, h)); } =20 - regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); - regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); =20 if (mixer->cfg->de_type !=3D SUN8I_MIXER_DE33) @@ -317,7 +318,6 @@ static struct drm_plane **sun8i_layers_init(struct drm_= device *drm, struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); int plane_cnt =3D mixer->cfg->ui_num + mixer->cfg->vi_num; enum drm_plane_type type; - unsigned int phy_index; int i; =20 planes =3D devm_kcalloc(drm->dev, plane_cnt, sizeof(*planes), GFP_KERNEL); @@ -332,12 +332,8 @@ static struct drm_plane **sun8i_layers_init(struct drm= _device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - phy_index =3D i; - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) - phy_index =3D mixer->cfg->map[i]; - layer =3D sun8i_vi_layer_init_one(drm, type, mixer->engine.regs, - i, phy_index, plane_cnt, + i, i, plane_cnt, &mixer->cfg->lay_cfg); if (IS_ERR(layer)) { dev_err(drm->dev, @@ -357,12 +353,8 @@ static struct drm_plane **sun8i_layers_init(struct drm= _device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - phy_index =3D index; - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) - phy_index =3D mixer->cfg->map[index]; - layer =3D sun8i_ui_layer_init_one(drm, type, mixer->engine.regs, - index, phy_index, plane_cnt, + index, index, plane_cnt, &mixer->cfg->lay_cfg); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize %s plane\n", @@ -376,16 +368,25 @@ static struct drm_plane **sun8i_layers_init(struct dr= m_device *drm, return planes; } =20 +static struct drm_plane **sun50i_layers_init(struct drm_device *drm, + struct sunxi_engine *engine) +{ + struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); + + if (IS_ENABLED(CONFIG_DRM_SUN50I_PLANES)) + return sun50i_planes_setup(mixer->planes_dev, drm, engine->id); + + return NULL; +} + static void sun8i_mixer_mode_set(struct sunxi_engine *engine, const struct drm_display_mode *mode) { struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); - struct regmap *bld_regs; u32 bld_base, size, val; bool interlaced; =20 bld_base =3D sun8i_blender_base(mixer); - bld_regs =3D sun8i_blender_regmap(mixer); interlaced =3D !!(mode->flags & DRM_MODE_FLAG_INTERLACE); size =3D SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); =20 @@ -397,14 +398,14 @@ static void sun8i_mixer_mode_set(struct sunxi_engine = *engine, else regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size); =20 - regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); =20 if (interlaced) val =3D SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; else val =3D 0; =20 - regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), + regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); =20 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", @@ -417,8 +418,14 @@ static const struct sunxi_engine_ops sun8i_engine_ops = =3D { .mode_set =3D sun8i_mixer_mode_set, }; =20 +static const struct sunxi_engine_ops sun50i_engine_ops =3D { + .commit =3D sun8i_mixer_commit, + .layers_init =3D sun50i_layers_init, + .mode_set =3D sun8i_mixer_mode_set, +}; + static const struct regmap_config sun8i_mixer_regmap_config =3D { - .name =3D "layers", + .name =3D "display", .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, @@ -433,14 +440,6 @@ static const struct regmap_config sun8i_top_regmap_con= fig =3D { .max_register =3D 0x3c, }; =20 -static const struct regmap_config sun8i_disp_regmap_config =3D { - .name =3D "display", - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D 0x20000, -}; - static int sun8i_mixer_of_get_id(struct device_node *node) { struct device_node *ep, *remote; @@ -463,17 +462,14 @@ static int sun8i_mixer_of_get_id(struct device_node *= node) =20 static void sun8i_mixer_init(struct sun8i_mixer *mixer) { - struct regmap *top_regs, *disp_regs; unsigned int base =3D sun8i_blender_base(mixer); + struct regmap *top_regs; int plane_cnt, i; =20 - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) top_regs =3D mixer->top_regs; - disp_regs =3D mixer->disp_regs; - } else { + else top_regs =3D mixer->engine.regs; - disp_regs =3D mixer->engine.regs; - } =20 /* Enable the mixer */ regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL, @@ -483,25 +479,25 @@ static void sun8i_mixer_init(struct sun8i_mixer *mixe= r) regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1); =20 /* Set background color to black */ - regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), SUN8I_MIXER_BLEND_COLOR_BLACK); =20 /* * Set fill color of bottom plane to black. Generally not needed * except when VI plane is at bottom (zpos =3D 0) and enabled. */ - regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); - regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), SUN8I_MIXER_BLEND_COLOR_BLACK); =20 plane_cnt =3D mixer->cfg->vi_num + mixer->cfg->ui_num; for (i =3D 0; i < plane_cnt; i++) - regmap_write(disp_regs, + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(base, i), SUN8I_MIXER_BLEND_MODE_DEF); =20 - regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); } =20 @@ -532,7 +528,6 @@ static int sun8i_mixer_bind(struct device *dev, struct = device *master, if (!mixer) return -ENOMEM; dev_set_drvdata(dev, mixer); - mixer->engine.ops =3D &sun8i_engine_ops; mixer->engine.node =3D dev->of_node; =20 if (of_property_present(dev->of_node, "iommus")) { @@ -562,6 +557,11 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, if (!mixer->cfg) return -EINVAL; =20 + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) + mixer->engine.ops =3D &sun50i_engine_ops; + else + mixer->engine.ops =3D &sun8i_engine_ops; + regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); @@ -584,17 +584,6 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, dev_err(dev, "Couldn't create the top regmap\n"); return PTR_ERR(mixer->top_regs); } - - regs =3D devm_platform_ioremap_resource_byname(pdev, "display"); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - mixer->disp_regs =3D devm_regmap_init_mmio(dev, regs, - &sun8i_disp_regmap_config); - if (IS_ERR(mixer->disp_regs)) { - dev_err(dev, "Couldn't create the disp regmap\n"); - return PTR_ERR(mixer->disp_regs); - } } =20 mixer->reset =3D devm_reset_control_get(dev, NULL); @@ -634,6 +623,33 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, =20 clk_prepare_enable(mixer->mod_clk); =20 + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + struct platform_device *pdev; + struct device_node *np; + void *data; + + np =3D of_parse_phandle(dev->of_node, "allwinner,planes", 0); + if (!np) { + ret =3D -ENODEV; + goto err_disable_mod_clk; + } + + pdev =3D of_find_device_by_node(np); + of_node_put(np); + if (!pdev) { + ret =3D -EPROBE_DEFER; + goto err_disable_mod_clk; + } + + data =3D platform_get_drvdata(pdev); + if (!data) { + put_device(&pdev->dev); + return -EPROBE_DEFER; + } + + mixer->planes_dev =3D &pdev->dev; + } + list_add_tail(&mixer->engine.list, &drv->engine_list); =20 /* Reset registers and disable unused sub-engines */ @@ -668,6 +684,8 @@ static int sun8i_mixer_bind(struct device *dev, struct = device *master, =20 return 0; =20 +err_disable_mod_clk: + clk_disable_unprepare(mixer->mod_clk); err_disable_bus_clk: clk_disable_unprepare(mixer->bus_clk); err_assert_reset: @@ -863,16 +881,8 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg =3D { - .lay_cfg =3D { - .de_type =3D SUN8I_MIXER_DE33, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 4096, - }, .de_type =3D SUN8I_MIXER_DE33, .mod_rate =3D 600000000, - .ui_num =3D 3, - .vi_num =3D 1, - .map =3D {0, 6, 7, 8}, }; =20 static const struct of_device_id sun8i_mixer_of_table[] =3D { diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/su= n8i_mixer.h index e2f83301aae8..7abc88c898d9 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -202,7 +202,6 @@ struct sun8i_mixer_cfg { int ui_num; unsigned int de_type; unsigned long mod_rate; - unsigned int map[6]; }; =20 struct sun8i_mixer { @@ -216,7 +215,7 @@ struct sun8i_mixer { struct clk *mod_clk; =20 struct regmap *top_regs; - struct regmap *disp_regs; + struct device *planes_dev; }; =20 enum { @@ -252,13 +251,6 @@ sun8i_blender_base(struct sun8i_mixer *mixer) return mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE3 ? DE3_BLD_BASE : DE2_BL= D_BASE; } =20 -static inline struct regmap * -sun8i_blender_regmap(struct sun8i_mixer *mixer) -{ - return mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33 ? - mixer->disp_regs : mixer->engine.regs; -} - static inline u32 sun8i_channel_base(struct sun8i_layer *layer) { --=20 2.51.2