From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE54F2F530A for ; Sat, 15 Nov 2025 14:14:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216058; cv=none; b=A6/Q3shciIi5MYAHR58NsJsp7fBaZScWXHtmNPFenSW3m9zpDnJq6GlhZfb1O9+3JUHK7eLNj57AFrKD/ryLMwCxVZFGnsPgP1tri/DP+kTYLrZUxrHxwPjgdBm0lT7PNiGDxM9KMiqNwAcWQgdG4l369gML9+276N4djemEPVY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216058; c=relaxed/simple; bh=aG0vNN2zVi7p1GToVdpDOjQmhx7Tshg7Tk0b4TzISHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cJzzntGULRWw8padCLj5G/nImN8g9PISe857pFuPLCShJfKYTienqYl0DbvrWzrWSG2DjXZjTnnhJEtSF9QtTCt7iWnRiV00O9Y0y+/pABRVJBJmDvcQKpkxvoNmJ47IPLcTmBkJ5t401hMd9xVugdE7J74G/8dEMwDCVxmqv+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y4vg6YTo; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y4vg6YTo" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-64080ccf749so4064447a12.2 for ; Sat, 15 Nov 2025 06:14:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216054; x=1763820854; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MocqCxWcaLZfsHWYqTZWM/wBzmMvMPkWJzIzBgPappQ=; b=Y4vg6YTob9b24D9POBdIUlohajimMBtbCB3j77g9JPri2BPFxE/jPxPc0NSk4Eq/VK /hit9RBAEeiC1mZX/2rFdLG95rt4p2e8VFG68Y46x25R1Q6p1M4oEeHh3/YfH/n0mqa8 vgZw0EDb9VSIkdyl4cRcH6tAi5NAPuEfug00LdgmeT5ZJqWn7bSG606oo7qp/6xWxU1s 8NpreEIkVMG7H3y3xcpKXYjYK0m1pWh1SUNDiU3oNry5rOItsaIvHmbN2EhJ4cMNOZrn c1nU8Bix7zxJKjqeh1k6ag4KqzksqtLmWMza7Z6GdHazHN3SnKhTG7bE+1rJHxDXZb47 H5cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216054; x=1763820854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MocqCxWcaLZfsHWYqTZWM/wBzmMvMPkWJzIzBgPappQ=; b=wXZiJFvNV0BL1UymsFnAZDb3gGDZN9Tg+01qvGxsGE4gxCcoUKG7UrV7Wjo0CIlNJW I0X9FkQhV6uzZftDfjFGZzePfA9zmyMwXqiJdo7ujgB4NRrCaapJzqNvrUhJs9t3xw2N znF27NkXaau2av20dSgaMGlXGX3Umg4lblzuCyHO98D5UVXXMIA4uuNXKc54JFevuzSI uVU7xj3L+yFJ/WuVYeqdg6ajiN7BPwegjDesgfAOxtEsTJ/J13smHbdyXlw5VpEtG259 J0yw/rPFqfFkcXtTaYvlXCJsqzmyBJvWDMirQyfcyc8abLMKcqq+sxv0n9N6L6Bxzmhz mDnA== X-Forwarded-Encrypted: i=1; AJvYcCXdo8rJw271Hn1TQG8aGz6uOCyJQhKJghF3lrXlxfDY7R2nQJh6zfrPdn2eGi26dtTpBkVi0JyP8dyO+9o=@vger.kernel.org X-Gm-Message-State: AOJu0YzEcxG5aEPJssHZeZFyyZyL4eI9HcMrMMFJVnn/QKzqvCQfzcCL 5Ai1R6rgy3Vrz16nyLoLEClYstCCtJjwizt3xdArZUGOEnaI4pGjM9eH X-Gm-Gg: ASbGncujhwLFFsH0Jz9FoMnfNBvgoAGLTH5cF9Q4h3R2gEqxDWaYYMOaK23DqGAioaO uRQTkLth8qJ5+H8FYgFGE1QojP3xU4c6lxycMVYbxrk2drCAUJTHXBhdNbe+2JszY33+gfa4y02 ecpKTxI0Ri8PA81XnGMTOMIivbA9eALkn0vauKcLx/cTkuTU2S3N+8u5W2z0x1kHLHFb/pEgYOG eujwauudZvAPXx5jIeTjgSffpnZCnJCftR64KHvD1CYA1CODNB3p0LAvBs4LGhR5NIObW+MFzUd Rik5DdwREMRB7J4ZDyMyypZ+/ynZzznMyJvhgp5txWz0KXTihP97m4kqJGaLXIg9OX8D9SBQTnD 2icXRnPHx1JJF4RRAKYLdGF9TAJiluGYPiVpWLIfZ3Xt3NV4fzYU/pMbCPcL9jcjrCAeL7uhAiF RjKdHfq43Gd2EZ4ryj99WIK1moeFAXJ5yQmz6ZeBtVmPrxnLwHw+o5fowK X-Google-Smtp-Source: AGHT+IFSj1aDwiro/wwK4L9h7pp1M9ctQw+POyBArF5AsNHZz7cGsgDc33Ii1wskS73N5JZnJxCpEQ== X-Received: by 2002:a17:906:f145:b0:b73:6d56:f3ff with SMTP id a640c23a62f3a-b736d573ee7mr440406566b.20.1763216054020; Sat, 15 Nov 2025 06:14:14 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:13 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 1/7] drm/sun4i: Add support for DE33 CSC Date: Sat, 15 Nov 2025 15:13:41 +0100 Message-ID: <20251115141347.13087-2-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DE33 has channel CSC units (for each plane separately) so pipeline can be configured to output in desired colorspace. Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun8i_csc.c | 71 +++++++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_csc.h | 5 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8= i_csc.c index ce81c12f511d..70fc9b017d17 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -205,6 +205,72 @@ static void sun8i_de3_ccsc_setup(struct regmap *map, i= nt layer, mask, val); } =20 +/* extract constant from high word and invert sign if necessary */ +static u32 sun8i_de33_ccsc_get_constant(u32 value) +{ + value >>=3D 16; + + if (value & BIT(15)) + return 0x400 - (value & 0x3ff); + + return value; +} + +static void sun8i_de33_convert_table(const u32 *src, u32 *dst) +{ + dst[0] =3D sun8i_de33_ccsc_get_constant(src[3]); + dst[1] =3D sun8i_de33_ccsc_get_constant(src[7]); + dst[2] =3D sun8i_de33_ccsc_get_constant(src[11]); + memcpy(&dst[3], src, sizeof(u32) * 12); + dst[6] &=3D 0xffff; + dst[10] &=3D 0xffff; + dst[14] &=3D 0xffff; +} + +static void sun8i_de33_ccsc_setup(struct regmap *map, int layer, + enum sun8i_csc_mode mode, + enum drm_color_encoding encoding, + enum drm_color_range range) +{ + u32 addr, val, base, csc[15]; + const u32 *table; + int i; + + table =3D yuv2rgb_de3[range][encoding]; + base =3D DE33_CCSC_BASE + layer * DE33_CH_SIZE; + + switch (mode) { + case SUN8I_CSC_MODE_OFF: + val =3D 0; + break; + case SUN8I_CSC_MODE_YUV2RGB: + val =3D SUN8I_CSC_CTRL_EN; + sun8i_de33_convert_table(table, csc); + regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15); + break; + case SUN8I_CSC_MODE_YVU2RGB: + val =3D SUN8I_CSC_CTRL_EN; + sun8i_de33_convert_table(table, csc); + for (i =3D 0; i < 15; i++) { + addr =3D SUN50I_CSC_COEFF(base, i); + if (i > 3) { + if (((i - 3) & 3) =3D=3D 1) + addr =3D SUN50I_CSC_COEFF(base, i + 1); + else if (((i - 3) & 3) =3D=3D 2) + addr =3D SUN50I_CSC_COEFF(base, i - 1); + } + regmap_write(map, addr, csc[i]); + } + break; + default: + val =3D 0; + DRM_WARN("Wrong CSC mode specified.\n"); + return; + } + + regmap_write(map, SUN8I_CSC_CTRL(base), val); +} + static u32 sun8i_csc_get_mode(struct drm_plane_state *state) { const struct drm_format_info *format; @@ -238,6 +304,11 @@ void sun8i_csc_config(struct sun8i_layer *layer, mode, state->color_encoding, state->color_range); return; + } else if (layer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + sun8i_de33_ccsc_setup(layer->regs, layer->channel, + mode, state->color_encoding, + state->color_range); + return; } =20 base =3D ccsc_base[layer->cfg->ccsc][layer->channel]; diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8= i_csc.h index 2a4b79599610..d2ba5f8611aa 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.h +++ b/drivers/gpu/drm/sun4i/sun8i_csc.h @@ -18,9 +18,14 @@ struct sun8i_layer; #define CCSC10_OFFSET 0xA0000 #define CCSC11_OFFSET 0xF0000 =20 +#define DE33_CCSC_BASE 0x800 + #define SUN8I_CSC_CTRL(base) ((base) + 0x0) #define SUN8I_CSC_COEFF(base, i) ((base) + 0x10 + 4 * (i)) =20 +#define SUN50I_CSC_COEFF(base, i) ((base) + 0x04 + 4 * (i)) +#define SUN50I_CSC_ALPHA(base) ((base) + 0x40) + #define SUN8I_CSC_CTRL_EN BIT(0) =20 void sun8i_csc_config(struct sun8i_layer *layer, --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63B432FD694 for ; Sat, 15 Nov 2025 14:14:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216059; cv=none; b=KjeEXSM0fconjLsfO24/oJtlD6sQkLwi/V4q1WB7EJ54reJerhyt7y+fTxQgR1QXOLiSXyse+2FA4jij6W8ggHHfXB1c4zkacTM8QOUQ455xcFrNOauudUssffhqoCnjTfk5FUSFAyvkvvQiBQoApW6WukQ/UAV0jI40EpEwFdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216059; c=relaxed/simple; bh=S0twu21aOxJ0VLQedxu7u559MvY/4tOCK9iLWkudnWI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t8imKS+Oar1u3q/ncbivC2DEt6bMRdg0BJo5KLl1A5/SLC+1ng29nZXxVgbVCY7sinrlUKH2A54M8zvm2QWZKEtmCFC2qVEUwrTDGC01wGsCkqCb1DijO5uV6kt61gHDGSNGVbbjco5uL2dD+nPPWFbhueCnfBr6pYYFRwwZq3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bGKTHkTS; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bGKTHkTS" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-640b0639dabso5066113a12.3 for ; Sat, 15 Nov 2025 06:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216056; x=1763820856; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TdxCYAFUxE8TEo/HdclUzBmM8/cH8lgIgGUaiseaWSY=; b=bGKTHkTSMmDreaLRKekZdXkPAu0VMx6SORhMdmq0/nSmU4i93rCk/bTMxpQV6P+gzu q774IWj9qyOphosXqov3uMd8ZR/0qrToRzCPclfVfExUXHOA2xMqM+tYmvFmF18ufhSv bIgvfK4smUSk6zr5xlbhb/wP3hhXjYY/XlxztYGS50cjQL8CyCs559PFr5TqD3+G2RNz 4o9C43drnPLHTrtuyTQCoCcAjUQXxFDgB6gUQ9532PsdsMghx0ZLWdW6tdih2vCe81He a8YFC7kosvDnfDtoFBmOr61o5xgoQFruZXuZjVPyG8ZhVuw571lVi+aRuC3g6rKaqlqt dDfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216056; x=1763820856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TdxCYAFUxE8TEo/HdclUzBmM8/cH8lgIgGUaiseaWSY=; b=BDubFPpT1GLmvvlJNp9dzpafzStg8idY+qFIRm99uei9bEGNNNChpAr2kc/Bh92OCE 4n2e5QzG5fDoCphzOtHluPiPzoW/AFdogBApmyyFkuogbGdCJCFz2i9+yySHzmq3PKde mKLU5dwF6sPAU8Y+ooK2UcQjuFazLo1pv0pNZzgW9b9opPdHxawt79Sdxfd9vpWNA0rq c9vHU61OdDd7GszZmsE3EVyfF71mJnXaTfgnQa0ys9CSMjgpxdeW/pNd7nSutGynF+3l bpaxIq9UgWMUJFjysQ74KTUmqEQFek/EpS8N1G0mTX1J4CJBrF42Mk1pIzKCN/BB9mkS V+sA== X-Forwarded-Encrypted: i=1; AJvYcCVLBEHg9emsGnnDVM/Y5pl62AdsmbJ29CVZ51wKNOxjRakjuth7V+AqAqHKBAgfi86Kw5/va0v8X9DBui4=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6U3NIcORYFsfiVh5odK6Q0uWq38jZdxl8BroT4j8Ipumpndaq aKJiFCdp5EZg6Ah22Hmb20zXxGObIb06hOflWyHTFXLbDPyNhfgbe20C X-Gm-Gg: ASbGncsyVTSnDj2jhiLxQToCywgc7a7Q8eVi+Ucf9O5lO+BBfTF6+cGChZkBxYB6VeX 6C6nnCz+NPV4Hmkm/mLOMdPAD1uafb5ML87FQw8uQ0ZqQAVvx+TR2RLpDR8iiS7Px2akZyvPJx3 m0zi1a+U5lANf+C2kkWvcBmL/gWG6u0k9uh/Njv/8VI5WYqY4B80UCczsugi/Eh3yGemHyQpwtq ud9VFZngObnB4BMlLho8Q4TzCOjC5AZU+NvLIGtwZED2/tP5c/SXNippyC8jhKNCW45mMcsX+UN ewvnN0V0t+29/U7/YO/70mX4whEiSGyUx47jKakK9VGZmz+J6vHH497Fm90mu8puN0M40trWQ0B TCpdUcfqMpgMC4VH8TrkoLfU1k3OapgL0EgnJAlDnR8aWG0joskHdsjXNANcl59HfNnB6XZSmU/ pPTmeR0+0aRDgqbbpD+vz54Uy02ew6dVH53AyRgDsgJEsYIQ== X-Google-Smtp-Source: AGHT+IFh8CjX1reglk+d9qFWiwVdzTnZZrgC6zCnkQGkRjSeca5TyFvpwvWCslriMZOQG7eYdwduUg== X-Received: by 2002:a17:907:7f05:b0:b73:880a:fdb7 with SMTP id a640c23a62f3a-b73880b0177mr94905066b.35.1763216055478; Sat, 15 Nov 2025 06:14:15 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:15 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 2/7] drm/sun4i: vi_layer: Limit formats for DE33 Date: Sat, 15 Nov 2025 15:13:42 +0100 Message-ID: <20251115141347.13087-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" YUV formats need scaler support due to chroma upscaling, but that's not yet supported in the driver. Remove them from supported list until DE33 scaler is properly supported. Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 36 +++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.c index 40008c38003d..baa240c4bb82 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -403,6 +403,37 @@ static const u32 sun8i_vi_layer_de3_formats[] =3D { DRM_FORMAT_YVU422, }; =20 +/* + * TODO: DE33 VI planes naturally support YUV formats but + * driver needs improvements in order to support them. + */ +static const u32 sun8i_vi_layer_de33_formats[] =3D { + DRM_FORMAT_ABGR1555, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_ABGR4444, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGR565, + DRM_FORMAT_BGR888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_BGRA4444, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_RGBA1010102, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, +}; + static const uint64_t sun8i_layer_modifiers[] =3D { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID @@ -432,7 +463,10 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm= _device *drm, layer->regs =3D regs; layer->cfg =3D cfg; =20 - if (layer->cfg->de_type >=3D SUN8I_MIXER_DE3) { + if (layer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + formats =3D sun8i_vi_layer_de33_formats; + format_count =3D ARRAY_SIZE(sun8i_vi_layer_de33_formats); + } else if (layer->cfg->de_type =3D=3D SUN8I_MIXER_DE3) { formats =3D sun8i_vi_layer_de3_formats; format_count =3D ARRAY_SIZE(sun8i_vi_layer_de3_formats); } else { --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F34B42FF644 for ; Sat, 15 Nov 2025 14:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216060; cv=none; b=WSosFQ32V5ikJT16LaSlRXwYdlm6doij6xN7AE6IXxxn4FWn65KiG518Bv8XTguLjzw6nOoKz47tlkFkQxiyhThM5/jXzgg+pXOVCfd4U+VcQHKHEPK7a3RzH4jad18MWuOvKvc0Psro9fawFnRPceezveHfRixpqU2iTRsJa7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216060; c=relaxed/simple; bh=GwnvL5vMWVsQ51UjbmyDs3QGAPhCZplv1N6Us1qfLHA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e6yrK9/5Yzrkr4lOp6Qov7i07nQ9y0HLJVbnWl6G+6OO/H8gRhZQcd29V1rvfCRML9k/VbKWHkbJkxD4PH4MPnYcDqFWdv6EA8A33ZqWadUJXlM/j/OxdmjxRL+pZyRXwZ0C1mRpRTaAXKce2bVpU7PzxFIwyMZEi/kGQb1GP0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aUW0NWkb; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aUW0NWkb" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-640a0812658so4713728a12.0 for ; Sat, 15 Nov 2025 06:14:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216057; x=1763820857; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UciMie+UNtQ6Be5Ygq/FZ+wB93JKP9NGMjXOu78hOHU=; b=aUW0NWkbYhHNof6Y4L6JNctvdn+3Wv8vaFSaScuL4M3TpyUj6D5/vFgDHW5RxCjeZA 8MYIoClQ62EZK6rUg6iOXV6VdpWayBEYqgY7KVHVE6qTNz82Zx0CdMZpEFGiXXjPhULp 2PPdVZMDE0xFwxdqa8OVzbEzd6k1BNdAB6XXw1+HsXnk2YJaTFcPpMs5CTVRyl2SBiCj A/hMKcPCTAMDtsbTckeui0ev41ppayE66NGfTRrDZ7E3txYNlctUCEpZ0QuhkCefY3zw 9246YuqKl505Hjz+TXZBuikXn/W0XJ0MD09UxCGbHqeEoLVWmyodBgcgRrlY2bwI4dKq 8Piw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216057; x=1763820857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UciMie+UNtQ6Be5Ygq/FZ+wB93JKP9NGMjXOu78hOHU=; b=ViTH3zn2osiilfBX9Tu6WlhAs9pdDBrG4PVxfxSpb9Ou9GSG9UQ1IGki6kWQKQVPWW flpFwgf8JSbxF2nyL25gQYOukCnC5a3FcS7dnMmmSA9EYRipDbL94ZFIzCPKBW666VNG 3PWyOEmyRlHC8Lh8Nmrc9GjuTiDAYY6d+iNcbkdSnGOMi1Nfw/1wq8YgEdNk+sotHccu eafAqagVgPu87dLn8Rb3i917pV+DerOZPxoEVUzp8VZXwi8g2qv4Nzw1DbSgsxadZnTC 8jaaVhZs0E0E1g2fA66E4wja+uTuPbdOL0PlHlOcxF2bH7kM2FiYGtPq3YUwl+bgg04u UkTg== X-Forwarded-Encrypted: i=1; AJvYcCU1SOfN0ArD2ERgezD1NPu1v855DQTEQ4QfWwgLLs3hfD1V3QysZuPLunwlqY8iJUI39MBQI6qZL/FIRak=@vger.kernel.org X-Gm-Message-State: AOJu0Yy1xdG7uTRtds4FfXRfpWWfEG1T6o4M/P7Eeb4nmA7OKVUivZRz 61A8qm+iDN6w+aYPmQlmfPRsTXnu2xnljsDSc9cyrZzalURyfJ2wjZsl X-Gm-Gg: ASbGnctvYx0sBZqBfck2XZupm88M66EowGDP4JTlryFc+44oQWDXtu+kc9ZaFixR+OX OSIW+4gYLa2FkFoDE9EVf7amL/PafTmQi5iAQG50sJQvpac5qxGB0oBHbQrvsqoJpBb/E6bfD2R EFjtP2t82l7zZ0l7Hs7ScVdiweedGjoboEQ+D7OuAhiyEPUIDpbIrhtGqGmF9x0ZCgzWnh4KNhk 7l8IyCp4BhDC7/OjOzU83ILilkIikz37nYEnjJ0gjz0hYEvjnpe/yauw+Cfwty7k6ijZRK8/DJ1 qbpO3qLu0U63UoCd23V7g/gEfTPDNyUBmrd+YYfiL7NcuxWb7LP+8TL0sTkMu8h4kt7pD2Wrk5o HzEesKyHgOb8fTYUvW5obwI5i4jT17gAOoSpXhDvzzgETuQ6FSKWwfalu5MDMVd+nF8DXkcqb8G XfJVcFA0RebKWrsOGm+ZIYqHGB/317PyF5Xv8YFwSGIa/SMs9Jyc7iR0qQ X-Google-Smtp-Source: AGHT+IHK6phfJOgzf+aqpzFKPTHMjqJZ4C/vVBwN+Y+khMKq+c5K63YPI1+yGx5o9/adAsErm3Oq3Q== X-Received: by 2002:a17:906:490c:b0:b73:6ca8:b81f with SMTP id a640c23a62f3a-b736ca8bbf7mr534553666b.51.1763216057167; Sat, 15 Nov 2025 06:14:17 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:16 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 3/7] clk: sunxi-ng: de2: Export register regmap for DE33 Date: Sat, 15 Nov 2025 15:13:43 +0100 Message-ID: <20251115141347.13087-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DE33 clock pre-set plane mapping, which is not something that we want from clock driver. Export registers instead, so DRM driver can set them properly. Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 ++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/cc= u-sun8i-de2.c index a6cd0f988859..2841ec922025 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include #include +#include #include =20 #include "ccu_common.h" @@ -250,6 +252,41 @@ static const struct sunxi_ccu_desc sun50i_h616_de33_cl= k_desc =3D { .num_resets =3D ARRAY_SIZE(sun50i_h5_de2_resets), }; =20 +/* + * Add a regmap for the DE33 plane driver to access plane + * mapping registers. + * Only these registers are allowed to be written, to prevent + * overriding clock and reset configuration. + */ + +#define SUN50I_DE33_CHN2CORE_REG 0x24 +#define SUN50I_DE33_PORT02CHN_REG 0x28 +#define SUN50I_DE33_PORT12CHN_REG 0x2c + +static bool sun8i_de2_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case SUN50I_DE33_CHN2CORE_REG: + case SUN50I_DE33_PORT02CHN_REG: + case SUN50I_DE33_PORT12CHN_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config sun8i_de2_ccu_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0xe0, + + /* other devices have no business accessing other registers */ + .readable_reg =3D sun8i_de2_ccu_regmap_accessible_reg, + .writeable_reg =3D sun8i_de2_ccu_regmap_accessible_reg, +}; + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct clk *bus_clk, *mod_clk; @@ -303,13 +340,23 @@ static int sunxi_de2_clk_probe(struct platform_device= *pdev) } =20 /* - * The DE33 requires these additional (unknown) registers set + * The DE33 requires these additional plane mapping registers set * during initialisation. */ if (of_device_is_compatible(pdev->dev.of_node, "allwinner,sun50i-h616-de33-clk")) { - writel(0, reg + 0x24); - writel(0x0000a980, reg + 0x28); + struct regmap *regmap; + + regmap =3D devm_regmap_init_mmio(&pdev->dev, reg, + &sun8i_de2_ccu_regmap_config); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); + goto err_assert_reset; + } + + ret =3D of_syscon_register_regmap(pdev->dev.of_node, regmap); + if (ret) + goto err_assert_reset; } =20 ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB6A2FFFA0 for ; Sat, 15 Nov 2025 14:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216062; cv=none; b=nkNBYogcHfU4YCkO0qToUqf4yPeU2WHPXphfQ7ZXqKk9Zz7oK/1VvmpTIlvzZWECgQDhjyvQW2QcZILEjzSV4dBAcJqKIG4+cwXtRTquW0BxKmWm0UzWlEI+VZqRZLDFrqs1jNgSgNs1sH6A+FtepbVg97PNnYg/NLnCJHJiDLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216062; c=relaxed/simple; bh=7MNfMigmcUs3aZfsMvXzfgbfkCinah3cgeYsqRMUe1I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bVbP/VwR2vYvxK1iraetrevXhOz1B+GTq8z6czI60aSO1F9YY8nxw7ow2PWSw8b/mxFidc5VTVb0QzpehvYUL7ONrnbklYZKeNdNsGB69c3qHmu4CwCuLgEELgsbl9NKWWLKuv0ktfBu9I9g87FyX6+3jk5immH/YA/hfx0k9zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Hi7NiGvz; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Hi7NiGvz" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-b73875aa527so32897266b.3 for ; Sat, 15 Nov 2025 06:14:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216059; x=1763820859; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JphR/yfHrqeoxGCFuZ74qbjmgj/bPrWp2+gxF4BO3oE=; b=Hi7NiGvzdjeiDhugfarIPnHjD5eifjUWgEaFTh12RB8lT7BCZ7DF+E3wVnMrK+45Mt hnAB1KUARFHzI+39TASRs/jeBR6xo8G4KC2nqQPYnO9WPKqrdLuvpqILYnfUaNZxbz7K asy5iMY4N6pQKrGWSiyVSeXBJSQx9s5y94kxJUIE87DPbJm8vEwiB+OUHTj5q0Si8qfH xjnG3juO3jGs8/4fDaM3dYRfOXgkbqlQ+vYZpWEbMVyKKXepNb8Poyj2T7TZJGdfJaZg 8TbHYOAHtmcwygzaL6F3gCy11cpdibqvLDns1PGo7/r8hs29U1nKSxj6pByrf5G1N6Hl LE5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216059; x=1763820859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JphR/yfHrqeoxGCFuZ74qbjmgj/bPrWp2+gxF4BO3oE=; b=Nqe7llXA5F+dsrPFGZni4FjZiuKjz5bdxyaS/qJeFHicbmPLGHEue7MxL4BM3pt1qC +9skIDrpcwu+GL41M16yAilLObOzcLR4Dqo8I7iFhuh79+aX4J4SzPrd/NnVc/CXnDS3 G/B0+MZeVVlRSpYjAUw00fe24P+RB3rj4j9S2s5omYxF4gaY5cyjSpC6K44XNuPfFT72 qnoFE3YZ79kaL8UBOeGStb6ZSxiIzUKbsKIk3cd+Ab92Fx8zzVlveL8DaUWvnl+GrtH3 5jhvLZ9bTw9bn9rndy+YtcUC748ruFxYetzq601jSEVCS3aKlbpJ1C+7JIGKUr3+Jpai 55YA== X-Forwarded-Encrypted: i=1; AJvYcCXi69i1GsNBmpepbCnmPhAS5krgvx548dL85xg52TCeijnHK/ypv3gordUdlMV9LcFJrO39hhqsj1yTFbY=@vger.kernel.org X-Gm-Message-State: AOJu0YzekXXRKW/kJASV48BaT7NcGbvGMMfZT2tpbP4JKGlGao3tc06I Nfl1q7x69K1dX8zsZihdLd6NTcBz+5xZyXKHqpFOh6AiGl44YwZAYp7J X-Gm-Gg: ASbGncugjuiDjZJwL/qlpdnwq1PlTDrGDEZdK2ULfIwXI5vJ55Rf7F0Ptzv58i6hAzM 6e5fld/sfy0fb7ppoe8y5i1epMIXLR3rTSZyW5xWIhIxrEw7fPbv16BzvlavQYlkCU3OahrF0HW G7zkn+TPFWp4lauBYg2MA62Zm+rpTuXG67Fy+/0leA4D7F00Ta5xuisLsE6IqXsxH/7TRPiaEpZ SvBv9p0Yb4bN8bCrKnPdP4ezdI2RIXTc+ROep3GY7SSBI6KoPtpqhrhNGyTLert4KARVZGyWWQ8 8ifA+FvOR7PpiEiUP4DUeLsjupesrQidLFrrBrfmEhlcCfa8EcENq+kw7epDwuml+Su/QvxRjSf Mx9iaLNfYfOTic3Ht0J5ohnUA6wtHc0/0ZSbHsYJH1e4qaf/s+CHohmXIgB5bZRpbXRGWd0iv3U KIdb9kHA4T0LXx9JOHx7YQT0cXkQ059h/pZG+P8Lhz+fYuog== X-Google-Smtp-Source: AGHT+IF/NKVfiJ7TrqEh+PcUiDYYnExZ1hICJ4keAyez444tuP7vZ12VBd4zl4CNGFC7PXxBkD/1Pw== X-Received: by 2002:a17:906:7304:b0:b72:a899:168d with SMTP id a640c23a62f3a-b73677edba0mr706079866b.13.1763216058665; Sat, 15 Nov 2025 06:14:18 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:18 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 4/7] dt-bindings: display: allwinner: Add DE33 planes Date: Sat, 15 Nov 2025 15:13:44 +0100 Message-ID: <20251115141347.13087-5-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner Display Engine 3.3 contains planes, which are shared resources between all mixers present in SoC. They can be assigned to specific mixer by using registers which reside in display clocks MMIO. Add a binding for them. Signed-off-by: Jernej Skrabec --- .../allwinner,sun50i-h616-de33-planes.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/allwinner,sun= 50i-h616-de33-planes.yaml diff --git a/Documentation/devicetree/bindings/display/allwinner,sun50i-h61= 6-de33-planes.yaml b/Documentation/devicetree/bindings/display/allwinner,su= n50i-h616-de33-planes.yaml new file mode 100644 index 000000000000..801e5068a6b5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/allwinner,sun50i-h616-de33-= planes.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/allwinner,sun50i-h616-de33-plan= es.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H616 Display Engine 3.3 planes + +maintainers: + - Jernej Skrabec + +description: | + Display Engine 3.3 planes are independent of mixers, contrary to + previous generations of Display Engine. Planes can be assigned to + mixers independently and even dynamically during runtime. + +properties: + compatible: + enum: + - allwinner,sun50i-h616-de33-planes + + reg: + maxItems: 1 + + allwinner,plane-mapping: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of Display Engine clock node + +required: + - compatible + - reg + - allwinner,plane-mapping + +additionalProperties: false + +examples: + - | + planes: planes@100000 { + compatible =3D "allwinner,sun50i-h616-de33-planes"; + reg =3D <0x100000 0x180000>; + allwinner,plane-mapping =3D <&display_clocks>; + }; + +... --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D055E2FBE12 for ; Sat, 15 Nov 2025 14:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216064; cv=none; b=PiJCjKQKtWV+YjAsWXv3rz0rYj38motbkh5V6rdLC0ZCv5PKtMpahu4pxXUV0JJ37OEi9A8jf4RfYqb96spzKUVpkqq0BJOSUyOtnLwSPu2HujbqmkIBERweyFgdAhjpjxjzaNsHOIFErGYpHojg1hK6QXzGasjTE+frhulJdE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216064; c=relaxed/simple; bh=JeJ/r3r6p1NeXChaBCcLY3ZUFPlKr1ccZPRTLmbzSzo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zlu0lnvzOlzYYsEt8CIFFCSdHTACHSt49RjsZL+RsCttWkzlnElLjMpEScquAFaoSRPobZdTyl2/tOIiEfg2mcdMNfWKlrn+LpozeWlQIjm8GnVdD53tR5bSIWZPOUrZXkdhAJoCnaIKecEQ6TJYStzpIVxPazyD695Pyly3V3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=m0MSamV7; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="m0MSamV7" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-b736cd741c1so254703466b.0 for ; Sat, 15 Nov 2025 06:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216060; x=1763820860; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pVbw8sqfmsGsfsXTGzKu/do/A1FF7lGaLVG/hAhMlcM=; b=m0MSamV7drvxla8xUISyjT4ZkpIIu2IC1y9dUDnIOwk3Ub9L9Ivds7BzCdcszrhtfW QHjbLySE4uNHlCYKyDQzp6Otya9rb9aMewukEz06wcKJQ+Ck2I16uW2Mn9CUTZLhhDOy CK5UjjU1UAaeFVHCLjAruefEgEVxB507BqerQky6iSViGOAx/uv9XyLQCLr5IpzTWR7Q C2fRDGwbuPFH1rDkRIOPNnEIX0lhCaRtw0x/dxgTD1H/DORgzBfEMJ5QBNSCV3jiZ4ZY dH+nXtHHCrxIiCpTGiOMRqAyncN/w76n+Fqup/drm5W74pR7hha8dVEsI80pXxL6NCMu 5M7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216060; x=1763820860; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pVbw8sqfmsGsfsXTGzKu/do/A1FF7lGaLVG/hAhMlcM=; b=VGlEsU67ATKLw50K1FEQ65eh9IPqEb4/eSr47ysF6Sd9pxvKFcxkB4LejQwXP1tVyg PhERXS9IVgnuhiX8ee5tjC2t3nOiAYrv3Aawlveul5eEEyns3SBY2RSv/y8ENVKFc13U prcbbdMN3NOpVvSOztRcwraUimDFUptiXBU4+xnrC1c0ctyxqnXq4BAiGv7j5WtnQGI9 MLi5+IAznb+Zz7kKwPmvRgM+koV8U4b0HKCji85tiMLWoPvegnSVg/qGtSUp8nBL8GWv RETU2Cor4r++uNoi4CwrT69RIwUQygeI+3WPZ+hI796Y9w5FhVw58JZeVlOSH6fOdeu7 oa6A== X-Forwarded-Encrypted: i=1; AJvYcCXMBqBONFed4FYNrN81AWtSXtxxD+EtbFPulVNCm4iPzUtLeaPKHnz/60DW0oB9ZWc/VtWmbgHHDug/EsE=@vger.kernel.org X-Gm-Message-State: AOJu0YzcU1x0rIHayoYys48oKr0w8ZN+yMIR4u0w1Jklg/jlcS5GOD9W rYO2f9I0gYCI/zLrO4MCMkzy/mGtIz50fjTdBEFqGLLeSOceaiPyqMXJ X-Gm-Gg: ASbGnctq2moPze4D/fssoq0UUe0QYyrie+hLYPAnaiJ3U/nyy/dewgwsjuew4sWYDz3 SpjgDqV+M7YuPSvOzfWgg7AWKyl9RHeI0JGnVOP4Dt3cQSLQj0xaH/++kgiMX9QMHV4txjIpCDk dueMi1JSXBIwgMyDL/E6TXpBtapDqj5759zXz0HFMSjFXaPZKS5CfAFxFw8S4pySkdYMaDo34mN ON79aQOABZ4EHDnHrZMa+YbrENqyhJ13E4MFMBI/+WLwooW3LM0oJEcoWAOqK8of3heL3qhoZp5 fNsM078SKVqlN57N4QIbkF1EObLOZ1dvvUPRlR29cHx6AtJZp+B3fB1v54mLBiJ7QNFSJ+Dx02J D2vC8QFfrKstv2MVe5orjJPlRAEx2JSEsJZdaHQ05kAUcmxFLloks/cwiaYt8oznItSQrpRGsY+ ZmxeC9OFAqd13t+J9PF2hBw+p1ep8bkqen+wwspZmQpInUPQ== X-Google-Smtp-Source: AGHT+IGbU8DEm/CCSleW/Yu4/6wA0uutVsxsCUAngp8FeQ9xWSzPAIlK7ahdDPBbaS4CEF2iCochtA== X-Received: by 2002:a17:906:d9b:b0:b73:68b3:bd2f with SMTP id a640c23a62f3a-b7368b3c0fdmr502509366b.40.1763216060152; Sat, 15 Nov 2025 06:14:20 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:19 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 5/7] drm/sun4i: Add planes driver Date: Sat, 15 Nov 2025 15:13:45 +0100 Message-ID: <20251115141347.13087-6-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This driver serves just as planes sharing manager, needed for Display Engine 3.3 and newer. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/Kconfig | 8 + drivers/gpu/drm/sun4i/Makefile | 1 + drivers/gpu/drm/sun4i/sun50i_planes.c | 205 ++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun50i_planes.h | 43 ++++++ 4 files changed, 257 insertions(+) create mode 100644 drivers/gpu/drm/sun4i/sun50i_planes.c create mode 100644 drivers/gpu/drm/sun4i/sun50i_planes.h diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index b56ba00aabca..946dd7606094 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -85,4 +85,12 @@ config DRM_SUN8I_TCON_TOP TCON TOP is responsible for configuring display pipeline for HDMI, TVE and LCD. =20 +config DRM_SUN50I_PLANES + tristate + default DRM_SUN4I if DRM_SUN8I_MIXER!=3Dn + help + Chose this option if you have an Allwinner Soc with the + Display Engine 3.3 or newer. Planes are shared resource + between multiple mixers. + endif diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index bad7497a0d11..03f002abef15 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_DRM_SUN6I_DSI) +=3D sun6i_mipi_dsi.o obj-$(CONFIG_DRM_SUN8I_DW_HDMI) +=3D sun8i-drm-hdmi.o obj-$(CONFIG_DRM_SUN8I_MIXER) +=3D sun8i-mixer.o obj-$(CONFIG_DRM_SUN8I_TCON_TOP) +=3D sun8i_tcon_top.o +obj-$(CONFIG_DRM_SUN50I_PLANES) +=3D sun50i_planes.o diff --git a/drivers/gpu/drm/sun4i/sun50i_planes.c b/drivers/gpu/drm/sun4i/= sun50i_planes.c new file mode 100644 index 000000000000..a99c01122990 --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun50i_planes.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2025 Jernej Skrabec */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sun50i_planes.h" +#include "sun8i_ui_layer.h" +#include "sun8i_vi_layer.h" + +static bool sun50i_planes_node_is_planes(struct device_node *node) +{ + return !!of_match_node(sun50i_planes_of_table, node); +} + +struct drm_plane ** +sun50i_planes_setup(struct device *dev, struct drm_device *drm, + unsigned int mixer) +{ + struct sun50i_planes *planes =3D dev_get_drvdata(dev); + const struct sun50i_planes_quirks *quirks; + struct drm_plane **drm_planes; + const struct default_map *map; + unsigned int i; + + if (!sun50i_planes_node_is_planes(dev->of_node)) { + dev_err(dev, "Device is not planes driver!\n"); + return NULL; + } + + if (!planes) { + dev_err(dev, "Planes driver is not loaded yet!\n"); + return NULL; + } + + if (mixer > 1) { + dev_err(dev, "Mixer index is too high!\n"); + return NULL; + } + + quirks =3D planes->quirks; + map =3D &quirks->def_map[mixer]; + + drm_planes =3D devm_kcalloc(drm->dev, map->num_ch + 1, + sizeof(*drm_planes), GFP_KERNEL); + if (!drm_planes) + return ERR_PTR(-ENOMEM); + + for (i =3D 0; i < map->num_ch; i++) { + unsigned int phy_ch =3D map->map[i]; + struct sun8i_layer *layer; + enum drm_plane_type type; + + if ((i =3D=3D 0 && map->num_ch =3D=3D 1) || i =3D=3D 1) + type =3D DRM_PLANE_TYPE_PRIMARY; + else + type =3D DRM_PLANE_TYPE_OVERLAY; + + if (phy_ch < UI_PLANE_OFFSET) + layer =3D sun8i_vi_layer_init_one(drm, type, planes->regs, + i, phy_ch, map->num_ch, + &quirks->cfg); + else + layer =3D sun8i_ui_layer_init_one(drm, type, planes->regs, + i, phy_ch, map->num_ch, + &quirks->cfg); + + if (IS_ERR(layer)) { + dev_err(drm->dev, + "Couldn't initialize DRM plane\n"); + return ERR_CAST(layer); + } + + drm_planes[i] =3D &layer->plane; + } + + return drm_planes; +} +EXPORT_SYMBOL(sun50i_planes_setup); + +static void sun50i_planes_init_mapping(struct sun50i_planes *planes) +{ + const struct sun50i_planes_quirks *quirks =3D planes->quirks; + unsigned int i, j; + u32 mapping; + + mapping =3D 0; + for (j =3D 0; j < MAX_DISP; j++) + for (i =3D 0; i < quirks->def_map[j].num_ch; i++) { + unsigned int ch =3D quirks->def_map[j].map[i]; + + if (ch < UI_PLANE_OFFSET) + mapping |=3D j << (ch * 2); + else + mapping |=3D j << ((ch - UI_PLANE_OFFSET) * 2 + 16); + } + regmap_write(planes->mapping, SUNXI_DE33_DE_CHN2CORE_MUX_REG, mapping); + + for (j =3D 0; j < MAX_DISP; j++) { + mapping =3D 0; + for (i =3D 0; i < quirks->def_map[j].num_ch; i++) { + unsigned int ch =3D quirks->def_map[j].map[i]; + + if (ch >=3D UI_PLANE_OFFSET) + ch +=3D 2; + + mapping |=3D ch << (i * 4); + } + regmap_write(planes->mapping, SUNXI_DE33_DE_PORT02CHN_MUX_REG + j * 4, m= apping); + } +} + +static const struct regmap_config sun50i_planes_regmap_config =3D { + .name =3D "planes", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x17fffc, +}; + +static int sun50i_planes_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sun50i_planes *planes; + void __iomem *regs; + + planes =3D devm_kzalloc(dev, sizeof(*planes), GFP_KERNEL); + if (!planes) + return -ENOMEM; + + planes->quirks =3D of_device_get_match_data(&pdev->dev); + if (!planes->quirks) + return dev_err_probe(dev, -EINVAL, "Unable to get quirks\n"); + + planes->mapping =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "allwinner,plane-mapping"); + if (IS_ERR(planes->mapping)) + return dev_err_probe(dev, PTR_ERR(planes->mapping), + "Unable to get mapping\n"); + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + planes->regs =3D devm_regmap_init_mmio(dev, regs, &sun50i_planes_regmap_c= onfig); + if (IS_ERR(planes->regs)) + return PTR_ERR(planes->regs); + + dev_set_drvdata(dev, planes); + + sun50i_planes_init_mapping(planes); + + return 0; +} + +static const struct sun50i_planes_quirks sun50i_h616_planes_quirks =3D { + .def_map =3D { + { + .map =3D {0, 6, 7}, + .num_ch =3D 3, + }, + { + .map =3D {1, 2, 8}, + .num_ch =3D 3, + }, + }, + .cfg =3D { + .de_type =3D SUN8I_MIXER_DE33, + /* + * TODO: All planes support scaling, but driver needs + * improvements to properly support it. + */ + .scaler_mask =3D 0, + .scanline_yuv =3D 4096, + }, +}; + +/* sun4i_drv uses this list to check if a device node is a plane */ +const struct of_device_id sun50i_planes_of_table[] =3D { + { + .compatible =3D "allwinner,sun50i-h616-de33-planes", + .data =3D &sun50i_h616_planes_quirks + }, + { } +}; +MODULE_DEVICE_TABLE(of, sun50i_planes_of_table); +EXPORT_SYMBOL(sun50i_planes_of_table); + +static struct platform_driver sun50i_planes_platform_driver =3D { + .probe =3D sun50i_planes_probe, + .driver =3D { + .name =3D "sun50i-planes", + .of_match_table =3D sun50i_planes_of_table, + }, +}; +module_platform_driver(sun50i_planes_platform_driver); + +MODULE_AUTHOR("Jernej Skrabec "); +MODULE_DESCRIPTION("Allwinner DE33 planes driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/sun4i/sun50i_planes.h b/drivers/gpu/drm/sun4i/= sun50i_planes.h new file mode 100644 index 000000000000..446feaeb03fc --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun50i_planes.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2025 Jernej Skrabec */ + +#ifndef _SUN50I_PLANES_H_ +#define _SUN50I_PLANES_H_ + +#include +#include + +#include "sun8i_mixer.h" + +/* mapping registers, located in clock register space */ +#define SUNXI_DE33_DE_CHN2CORE_MUX_REG 0x24 +#define SUNXI_DE33_DE_PORT02CHN_MUX_REG 0x28 +#define SUNXI_DE33_DE_PORT12CHN_MUX_REG 0x2c + +#define MAX_DISP 2 +#define MAX_CHANNELS 8 +#define UI_PLANE_OFFSET 6 + +struct default_map { + unsigned int map[MAX_CHANNELS]; + unsigned int num_ch; +}; + +struct sun50i_planes_quirks { + struct default_map def_map[MAX_DISP]; + struct sun8i_layer_cfg cfg; +}; + +struct sun50i_planes { + struct regmap *regs; + struct regmap *mapping; + const struct sun50i_planes_quirks *quirks; +}; + +extern const struct of_device_id sun50i_planes_of_table[]; + +struct drm_plane ** +sun50i_planes_setup(struct device *dev, struct drm_device *drm, + unsigned int mixer); + +#endif /* _SUN50I_PLANES_H_ */ --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DF4E3016E3 for ; Sat, 15 Nov 2025 14:14:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216065; cv=none; b=kBHrT9pPMJTFEBgMc3BWtsKVnPTMzFyW0jFAN878qMw93BIm69MRSLb3RJEPo3ChapH4gYwjFHX+BQZRysuJkykIgTxF6BNJoNERQIA59LluKq4RlMaUSpgjfBwBUhjByPEjKZgsXnfw05rOtHThGKaDSpMZ/NLRdBf1BfEiQbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216065; c=relaxed/simple; bh=/HxRScD2cq+UVkPX3OMV/vSVclwgfb2Shsd0VzOJaW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qAU6cDB45vfv88SRRhpt2zbJTVCUVBYBEMbnera5U8Ce1FRMAlP7xzDmWR3viNxaddTfDVE9wVPn+aTk4Fm3aR82DnY/NQ1wjWbhiKBgKzFelyB88x5BFvUE6eHoh1d50CotafzedPC9MoqBfbADYWi0JuZZzInb7JYD8YrLrr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hmg877+x; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hmg877+x" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-b73161849e1so500080266b.2 for ; Sat, 15 Nov 2025 06:14:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216062; x=1763820862; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LChDHbx4y116grQ6jx2/dXjEvBwJOxeh6WSv85ZRlvk=; b=hmg877+xRIyp2uBdsxoXhMnj+JbSiO3Q4DlNEQc7jDiFylhKCZsR/d1kdwFpZfq6Ua DboQcOATBTAIwTPwj6QCUgZlMQzTF1/g433plzX7K4XksbrjryUDD2LFjITfyS+l+2EH 1KgdnjcgFTTDm7LdVoleugOt2DVXtjkPlFdhCPNg9W0rEdiS3sjkwD8IgKqxScObfj2R VBFW7JoAe8jeV7haUz6UXNKU+P3IJmf7tgFDcH40jNet6sVTs7OVbOT7RnfuDb0W661p j9Ho7PQTcgEsRDhCzHf/QGGALjkH6Jftu8dDybR4cIxn9736/Nrd95+u5GImeMaqZX/w CpyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216062; x=1763820862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LChDHbx4y116grQ6jx2/dXjEvBwJOxeh6WSv85ZRlvk=; b=PRcmCqydqmkfD07CIgGu3R2vkbdHP/VO74ULkgMDTAS4FIZOV/0h9bCbgdOq0kGLJj R7Mv4ZogZ1FPwEWFUdOFAsx9s8jxkM1vVn8HzJRwsA6/zpFBo8wwH1CCwWaP9sM+Yrzw Q2SgVTMxQ3vc/QgX31ieHo84I2d7ZP+T21MiMYeqQR+G/cUFWLXXgHmxYPBeytB23QWk 1NZ9jeRzzAgL200B7rL0mL12zYtYLyxOvXga7TsKHAovp5JCA4wje2pvfTb65Ky7ol3d NLi/GeKEawtUy8ARJ3Su0vGwkMLKjr//tBXbmMi086lLHW027mdV2beLGpaaW7JCbZLL GKEA== X-Forwarded-Encrypted: i=1; AJvYcCWFQkVry2pm6TnwI2rppzkEGYbhFYS9mPt4PaZEzADaYSNZ/n7xQYlRf0j4+M+8TRZVWDawKGILQK3Jb7E=@vger.kernel.org X-Gm-Message-State: AOJu0Yzk6XEZCJBcV9TtVYiBCtzWgoRPVXuX3s3jw1Phagu7RIpFtbDJ D17BzaRY4nez3zqmRuc8y/Xsf/ra5UuAm5/v+u0080183WcO4KapNoUJ X-Gm-Gg: ASbGncsxSSaIiQB+HIHtgVmgQH8drJKPwdts8TYOIvvZp6CXySl8d6LrptWh42vyRha CmbRIeVH3oeb3yzmaPOO9FnSnrh8yZxcpVXaPt8qJAKYZw7ynWGE2qeoKDjE2838JpvNUXxnJoO LlHX6UfHdjIAMluJOJdSWhhd4ribjJiHEhNQq71aoQSQBMtZMhkXcBvCQd6w/3hDQ/aVZpHbfP8 ezprqlOdbMAl9lPolv9y7na3WvGpX/rY3TmV1uPWcTmHsp5DDOmKHMAJ1FIjTYGaRM7dCUu+T8g e1mrFljeau0munL9cFZNZou3RRniullalgnBbjbNPwffpj/IMwL5nWurZg7Bp6Yfes9Tj38/YVR WQNDt0x+jUZIPtraMCslDYNDrWPYBofNV3MeAjXnJrYvnl6OUsolLOgCPGIz9/f8PMjFILyHFOl wtEaKNwppnOuo55RHaDmOQX+TgIzDIbdjPBJDOHfs6EMSpa6pZZjf+24HU6cni0OoWtuE= X-Google-Smtp-Source: AGHT+IGK96g9RzM8eg44aCNe4s7zkdHo6HIsmO/rv+pQP0RPewfWCNhEzO33viKn6j62oVKNtGFutQ== X-Received: by 2002:a17:906:fe07:b0:b73:870f:fa2b with SMTP id a640c23a62f3a-b73870ffaf8mr113667666b.27.1763216061567; Sat, 15 Nov 2025 06:14:21 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:21 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 6/7] dt-bindings: display: allwinner: Update H616 DE33 binding Date: Sat, 15 Nov 2025 15:13:46 +0100 Message-ID: <20251115141347.13087-7-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As it turns out, current H616 DE33 binding was written based on incomplete understanding of DE33 design. Namely, planes are shared resource and not tied to specific mixer, which was the case for previous generations of Display Engine (DE3 and earlier). This means that current DE33 binding doesn't properly reflect HW and using it would mean that second mixer (used for second display output) can't be supported. Update DE33 mixer binding so instead of referencing planes register space, it contains phandle to newly introduced DE33 planes node. There is no user of this binding yet, so changes can be made safely, without breaking any backward compatibility. Signed-off-by: Jernej Skrabec --- .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t= -de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i= -a83t-de2-mixer.yaml index cbd18fd83e52..064e4ca7e419 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mi= xer.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mi= xer.yaml @@ -46,6 +46,10 @@ properties: resets: maxItems: 1 =20 + allwinner,planes: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of Display Engine 3.3 planes node + ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -74,22 +78,22 @@ allOf: properties: reg: description: | - Registers for controlling individual layers of the display - engine (layers), global control (top), and display blending - control (display). Names are from Allwinner BSP kernel. - maxItems: 3 + Registers for display blending control (display) and global + control (top). Names are from Allwinner BSP kernel. + maxItems: 2 reg-names: items: - - const: layers - - const: top - const: display + - const: top required: - reg-names + - allwinner,planes =20 else: properties: reg: maxItems: 1 + allwinner,planes: false =20 required: - compatible --=20 2.51.2 From nobody Sun Feb 8 00:11:46 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C35CB3019D6 for ; Sat, 15 Nov 2025 14:14:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216067; cv=none; b=oe5Df9sCAVabnFt3Dbjdb6nmH3mgV0A06PKFQaHVZsIIp9ao/BKHH8+GmRDK91yMPbS4aFJrZ2Sincvpezk6/aySBkTrIj1EXAHXJF7lccLhnACs+DX2gWMt4YxOTytqtJrnyfKOHckhATwy7N7gepDBP7jElPI8uMwZw6VTbH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763216067; c=relaxed/simple; bh=ARCr2MF2PDcGudo+PTuVZew5/GiYdu3vBhL2diGFAU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C6xBIhQRO84B7triTGXH6kqtc/3rFfgRJnsmRPG56wUz+e0SUcg6bmhsPbzE3TkJJE9Bejug0QAX16Jg6xxkyqkDwBEOJKPSd0kJe24esRhAQ6eS0c3B8cTy62CZPwz0RpnsVbtFeLV3DYHTF47ycKjE3NxvjV57+MyvpqIWGIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MNfDnyqa; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MNfDnyqa" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-640bd9039fbso4934309a12.2 for ; Sat, 15 Nov 2025 06:14:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1763216063; x=1763820863; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SznPGrtr2XDooq13sk6Kgg+QMqAR2LlCpjlNsch42gA=; b=MNfDnyqa6QO/ei3ZP0C9QEyeeRYz7fM3j/5U2AMlPRPgw319DDNBk8A6uNNET9imrd CVuwhJvVvxlc+ymKmCcoJMkyZuQNsYDZlPBfWNEHVFLGPVQe7qeSepXzQznJayVuimFt Fg406QROOSMBHKn/lz7d3QoTJ1OQgcr8Mv9/m6Ft8JGbmdWzhjMxfNVT8cGE844vFETJ 7bcnZKDFznaTEzSxv2WYEbJ+aZijUg+LVkRMNxE5eqWZgVs5+86mmPCBun0JIurWzdc1 11fFp+BUw1HruJGC6bpBAZPSjxtn41hhvyxQOVKp6OxpXZCH3y/Pk4gLdDxxLcneL0Ga bXZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1763216063; x=1763820863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SznPGrtr2XDooq13sk6Kgg+QMqAR2LlCpjlNsch42gA=; b=bfOD+n0+gZZITBL80mW9lpZuCLTlZl+/1d7eaB6F0uxvfCOhw+UhoSLfGJghINx/A0 Mhv4DnVDNX0t9GWe0PfOaqcoCX6MPMGUMm8LgrWJ5gGWg9Bbq08PECMQV7lRaOJ6BukB BWvKjzk2Li++r1nzv1JtqPnXizq2WNn3Qinv5noY4AbKuz47JTV2PunoTQUH6zlw0fxN 5MeEziaIby5gELvlzMT8OKJoMospDHqIPliRHCTsHzWyz5d5mFuqhLxJL/vF94eQnnIW vQbjiAPI8xj87BFiNqzqmLCzmYclUryL6g0x2tBVMNi7YN2ksZVIyQU731gRmm6m7J4T fg7w== X-Forwarded-Encrypted: i=1; AJvYcCU1jHrZ2iRoHp9wS+c88M7pB3LWnWsYZvWtJurbUikxRGKJNEfNNXIN0/Kro0nLDEAoYcu1LZ18e5T6Yhw=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/knRnCksdPOWa86ErQaf5yWRJ3bv/xcxX63U0zfcCkHfqJb6R dwFnP/2xYNS+0+8jjG50SurLHTfyMrzO6v8GX3WyfZUDqELUNk2uOlZ7 X-Gm-Gg: ASbGncsruLZGuyZjdf1LBH+VQfgAenzibj2NLQUdOUMEH2vqhp20DN7vC/5vSSUZGVO puG4FB6kpLQd0ExY80lBtefTBgXY+rH9VwCMS+UIegaA3gN9gc6O7+ND+FFzZwNr4paH+vyLfTO felsG53J5QcUGkDqVXhvWsXyoCycik8cX01VAh4pRQZ4PqxEghFC0GR8SCzvFYRbeHr2si1vdPk kJ7hMhOYfrrDOwxjjNWpQrGYSqVPZAZOrRgJn8bBO+oejFbcVtZnqVPY4yKNn7Zu62MwUd2s12S +06SUY5HciNXVw2X654VQg44LTb0H+qW1JZ6HdK0lbH798InyQppopw9U2uewIj8nZ+haCCefUl CAINBE8aDBlIqQI75Glvl6udJMuDLpCUIMPbaDLl6LIm2dq3oCpdRS28cijfn7WuuPlTPSvNaB+ NRiEXYJB13lWgdyEU7vc1ItQhgOHTH/ndcBdB3AQhKXRRaud4f/MOHPA5K X-Google-Smtp-Source: AGHT+IGNZo/U7zY8Q07lDbxVpkIabIMsA3romzMD93FNBaHxF7DsQi/nyue3LGz4eYZpXchvaLYh/g== X-Received: by 2002:a17:907:3d0b:b0:b39:57ab:ec18 with SMTP id a640c23a62f3a-b736794a6b3mr650833866b.45.1763216062968; Sat, 15 Nov 2025 06:14:22 -0800 (PST) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:22 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 7/7] drm/sun4i: switch DE33 to new bindings Date: Sat, 15 Nov 2025 15:13:47 +0100 Message-ID: <20251115141347.13087-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that everything is in place, switch DE33 to new bindings. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 130 +++++++++++++++------------- drivers/gpu/drm/sun4i/sun8i_mixer.h | 10 +-- 2 files changed, 71 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index fde3b677e925..da213e54e653 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -24,6 +25,7 @@ #include =20 #include "sun4i_drv.h" +#include "sun50i_planes.h" #include "sun8i_mixer.h" #include "sun8i_ui_layer.h" #include "sun8i_vi_layer.h" @@ -256,7 +258,6 @@ static void sun8i_mixer_commit(struct sunxi_engine *eng= ine, { struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); u32 bld_base =3D sun8i_blender_base(mixer); - struct regmap *bld_regs =3D sun8i_blender_regmap(mixer); struct drm_plane_state *plane_state; struct drm_plane *plane; u32 route =3D 0, pipe_en =3D 0; @@ -293,16 +294,16 @@ static void sun8i_mixer_commit(struct sunxi_engine *e= ngine, route |=3D layer->index << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); pipe_en |=3D SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); =20 - regmap_write(bld_regs, + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), SUN8I_MIXER_COORD(x, y)); - regmap_write(bld_regs, + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), SUN8I_MIXER_SIZE(w, h)); } =20 - regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); - regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + regmap_write(engine->regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); =20 if (mixer->cfg->de_type !=3D SUN8I_MIXER_DE33) @@ -317,7 +318,6 @@ static struct drm_plane **sun8i_layers_init(struct drm_= device *drm, struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); int plane_cnt =3D mixer->cfg->ui_num + mixer->cfg->vi_num; enum drm_plane_type type; - unsigned int phy_index; int i; =20 planes =3D devm_kcalloc(drm->dev, plane_cnt, sizeof(*planes), GFP_KERNEL); @@ -332,12 +332,8 @@ static struct drm_plane **sun8i_layers_init(struct drm= _device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - phy_index =3D i; - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) - phy_index =3D mixer->cfg->map[i]; - layer =3D sun8i_vi_layer_init_one(drm, type, mixer->engine.regs, - i, phy_index, plane_cnt, + i, i, plane_cnt, &mixer->cfg->lay_cfg); if (IS_ERR(layer)) { dev_err(drm->dev, @@ -357,12 +353,8 @@ static struct drm_plane **sun8i_layers_init(struct drm= _device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - phy_index =3D index; - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) - phy_index =3D mixer->cfg->map[index]; - layer =3D sun8i_ui_layer_init_one(drm, type, mixer->engine.regs, - index, phy_index, plane_cnt, + index, index, plane_cnt, &mixer->cfg->lay_cfg); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize %s plane\n", @@ -376,16 +368,25 @@ static struct drm_plane **sun8i_layers_init(struct dr= m_device *drm, return planes; } =20 +static struct drm_plane **sun50i_layers_init(struct drm_device *drm, + struct sunxi_engine *engine) +{ + struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); + + if (IS_ENABLED(CONFIG_DRM_SUN50I_PLANES)) + return sun50i_planes_setup(mixer->planes_dev, drm, engine->id); + + return NULL; +} + static void sun8i_mixer_mode_set(struct sunxi_engine *engine, const struct drm_display_mode *mode) { struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); - struct regmap *bld_regs; u32 bld_base, size, val; bool interlaced; =20 bld_base =3D sun8i_blender_base(mixer); - bld_regs =3D sun8i_blender_regmap(mixer); interlaced =3D !!(mode->flags & DRM_MODE_FLAG_INTERLACE); size =3D SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); =20 @@ -397,14 +398,14 @@ static void sun8i_mixer_mode_set(struct sunxi_engine = *engine, else regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size); =20 - regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); =20 if (interlaced) val =3D SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; else val =3D 0; =20 - regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), + regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); =20 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", @@ -417,8 +418,14 @@ static const struct sunxi_engine_ops sun8i_engine_ops = =3D { .mode_set =3D sun8i_mixer_mode_set, }; =20 +static const struct sunxi_engine_ops sun50i_engine_ops =3D { + .commit =3D sun8i_mixer_commit, + .layers_init =3D sun50i_layers_init, + .mode_set =3D sun8i_mixer_mode_set, +}; + static const struct regmap_config sun8i_mixer_regmap_config =3D { - .name =3D "layers", + .name =3D "display", .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, @@ -433,14 +440,6 @@ static const struct regmap_config sun8i_top_regmap_con= fig =3D { .max_register =3D 0x3c, }; =20 -static const struct regmap_config sun8i_disp_regmap_config =3D { - .name =3D "display", - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D 0x20000, -}; - static int sun8i_mixer_of_get_id(struct device_node *node) { struct device_node *ep, *remote; @@ -463,17 +462,14 @@ static int sun8i_mixer_of_get_id(struct device_node *= node) =20 static void sun8i_mixer_init(struct sun8i_mixer *mixer) { - struct regmap *top_regs, *disp_regs; unsigned int base =3D sun8i_blender_base(mixer); + struct regmap *top_regs; int plane_cnt, i; =20 - if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) top_regs =3D mixer->top_regs; - disp_regs =3D mixer->disp_regs; - } else { + else top_regs =3D mixer->engine.regs; - disp_regs =3D mixer->engine.regs; - } =20 /* Enable the mixer */ regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL, @@ -483,25 +479,25 @@ static void sun8i_mixer_init(struct sun8i_mixer *mixe= r) regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1); =20 /* Set background color to black */ - regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), SUN8I_MIXER_BLEND_COLOR_BLACK); =20 /* * Set fill color of bottom plane to black. Generally not needed * except when VI plane is at bottom (zpos =3D 0) and enabled. */ - regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); - regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), SUN8I_MIXER_BLEND_COLOR_BLACK); =20 plane_cnt =3D mixer->cfg->vi_num + mixer->cfg->ui_num; for (i =3D 0; i < plane_cnt; i++) - regmap_write(disp_regs, + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(base, i), SUN8I_MIXER_BLEND_MODE_DEF); =20 - regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); } =20 @@ -532,7 +528,6 @@ static int sun8i_mixer_bind(struct device *dev, struct = device *master, if (!mixer) return -ENOMEM; dev_set_drvdata(dev, mixer); - mixer->engine.ops =3D &sun8i_engine_ops; mixer->engine.node =3D dev->of_node; =20 if (of_property_present(dev->of_node, "iommus")) { @@ -562,6 +557,11 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, if (!mixer->cfg) return -EINVAL; =20 + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) + mixer->engine.ops =3D &sun50i_engine_ops; + else + mixer->engine.ops =3D &sun8i_engine_ops; + regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); @@ -584,17 +584,6 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, dev_err(dev, "Couldn't create the top regmap\n"); return PTR_ERR(mixer->top_regs); } - - regs =3D devm_platform_ioremap_resource_byname(pdev, "display"); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - mixer->disp_regs =3D devm_regmap_init_mmio(dev, regs, - &sun8i_disp_regmap_config); - if (IS_ERR(mixer->disp_regs)) { - dev_err(dev, "Couldn't create the disp regmap\n"); - return PTR_ERR(mixer->disp_regs); - } } =20 mixer->reset =3D devm_reset_control_get(dev, NULL); @@ -634,6 +623,33 @@ static int sun8i_mixer_bind(struct device *dev, struct= device *master, =20 clk_prepare_enable(mixer->mod_clk); =20 + if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33) { + struct platform_device *pdev; + struct device_node *np; + void *data; + + np =3D of_parse_phandle(dev->of_node, "allwinner,planes", 0); + if (!np) { + ret =3D -ENODEV; + goto err_disable_mod_clk; + } + + pdev =3D of_find_device_by_node(np); + of_node_put(np); + if (!pdev) { + ret =3D -EPROBE_DEFER; + goto err_disable_mod_clk; + } + + data =3D platform_get_drvdata(pdev); + if (!data) { + put_device(&pdev->dev); + return -EPROBE_DEFER; + } + + mixer->planes_dev =3D &pdev->dev; + } + list_add_tail(&mixer->engine.list, &drv->engine_list); =20 /* Reset registers and disable unused sub-engines */ @@ -668,6 +684,8 @@ static int sun8i_mixer_bind(struct device *dev, struct = device *master, =20 return 0; =20 +err_disable_mod_clk: + clk_disable_unprepare(mixer->mod_clk); err_disable_bus_clk: clk_disable_unprepare(mixer->bus_clk); err_assert_reset: @@ -863,16 +881,8 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg =3D { - .lay_cfg =3D { - .de_type =3D SUN8I_MIXER_DE33, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 4096, - }, .de_type =3D SUN8I_MIXER_DE33, .mod_rate =3D 600000000, - .ui_num =3D 3, - .vi_num =3D 1, - .map =3D {0, 6, 7, 8}, }; =20 static const struct of_device_id sun8i_mixer_of_table[] =3D { diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/su= n8i_mixer.h index e2f83301aae8..7abc88c898d9 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -202,7 +202,6 @@ struct sun8i_mixer_cfg { int ui_num; unsigned int de_type; unsigned long mod_rate; - unsigned int map[6]; }; =20 struct sun8i_mixer { @@ -216,7 +215,7 @@ struct sun8i_mixer { struct clk *mod_clk; =20 struct regmap *top_regs; - struct regmap *disp_regs; + struct device *planes_dev; }; =20 enum { @@ -252,13 +251,6 @@ sun8i_blender_base(struct sun8i_mixer *mixer) return mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE3 ? DE3_BLD_BASE : DE2_BL= D_BASE; } =20 -static inline struct regmap * -sun8i_blender_regmap(struct sun8i_mixer *mixer) -{ - return mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE33 ? - mixer->disp_regs : mixer->engine.regs; -} - static inline u32 sun8i_channel_base(struct sun8i_layer *layer) { --=20 2.51.2