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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:27:41.7514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a1f3f10-05d6-452c-d274-08de23ff5131 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9229 Content-Type: text/plain; charset="utf-8" From: Kartik Rajput On Tegra264, not all I2C controllers have the necessary interface to GPC DMA, this causes failures when function tegra_i2c_init_dma() is called. Ensure that "dmas" device-tree property is present before initializing DMA in function tegra_i2c_init_dma(). Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter --- v4 -> v9: * Moved the condition down to have all dma checks together. v2 -> v4: * Add debug print if DMA is not supported by the I2C controller. v1 -> v2: * Update commit message to clarify that some I2C controllers may not have the necessary interface to GPC DMA. --- drivers/i2c/busses/i2c-tegra.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index e533460bccc3..bd26b232ffb3 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -449,6 +449,11 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2= c_dev) if (IS_VI(i2c_dev)) return 0; =20 + if (!of_property_present(i2c_dev->dev->of_node, "dmas")) { + dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n"); + return 0; + } + if (i2c_dev->hw->has_apb_dma) { if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); --=20 2.50.1 From nobody Sun Feb 8 01:31:10 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013040.outbound.protection.outlook.com [40.93.201.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15B811DE2D7; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:27:54.4076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68fec197-464b-4976-1b65-08de23ff58c2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB54.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9642 Content-Type: text/plain; charset="utf-8" The current implementation uses a single value of THIGH, TLOW and setup hold time for both fast and fastplus. But these values can be different for each speed mode and should be using separate variables. Split the variables used for fast and fast plus mode. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- drivers/i2c/busses/i2c-tegra.c | 119 ++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 46 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index bd26b232ffb3..c0382c9a0430 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -196,12 +196,16 @@ enum msg_end_type { * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. * @tlow_std_mode: Low period of the clock in standard mode. * @thigh_std_mode: High period of the clock in standard mode. - * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus mod= es. - * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus m= odes. + * @tlow_fast_mode: Low period of the clock in fast mode. + * @thigh_fast_mode: High period of the clock in fast mode. + * @tlow_fastplus_mode: Low period of the clock in fast-plus mode. + * @thigh_fastplus_mode: High period of the clock in fast-plus mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop condi= tions * in standard mode. - * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and= stop - * conditions in fast/fast-plus modes. + * @setup_hold_time_fast_mode: Setup and hold time for start and stop + * conditions in fast mode. + * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop + * conditions in fast-plus mode. * @setup_hold_time_hs_mode: Setup and hold time for start and stop condit= ions * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the= tuned @@ -224,10 +228,13 @@ struct tegra_i2c_hw_feature { bool has_apb_dma; u32 tlow_std_mode; u32 thigh_std_mode; - u32 tlow_fast_fastplus_mode; - u32 thigh_fast_fastplus_mode; + u32 tlow_fast_mode; + u32 thigh_fast_mode; + u32 tlow_fastplus_mode; + u32 thigh_fastplus_mode; u32 setup_hold_time_std_mode; - u32 setup_hold_time_fast_fast_plus_mode; + u32 setup_hold_time_fast_mode; + u32 setup_hold_time_fastplus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; }; @@ -677,25 +684,21 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_d= ev) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); =20 - switch (t->bus_freq_hz) { - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: - default: - tlow =3D i2c_dev->hw->tlow_fast_fastplus_mode; - thigh =3D i2c_dev->hw->thigh_fast_fastplus_mode; - tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) - non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_plus_mode; - else - non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; - break; - - case 0 ... I2C_MAX_STANDARD_MODE_FREQ: + if (t->bus_freq_hz <=3D I2C_MAX_STANDARD_MODE_FREQ) { tlow =3D i2c_dev->hw->tlow_std_mode; thigh =3D i2c_dev->hw->thigh_std_mode; tsu_thd =3D i2c_dev->hw->setup_hold_time_std_mode; non_hs_mode =3D i2c_dev->hw->clk_divisor_std_mode; - break; + } else if (t->bus_freq_hz <=3D I2C_MAX_FAST_MODE_FREQ) { + tlow =3D i2c_dev->hw->tlow_fast_mode; + thigh =3D i2c_dev->hw->thigh_fast_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_mode; + non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; + } else { + tlow =3D i2c_dev->hw->tlow_fastplus_mode; + thigh =3D i2c_dev->hw->thigh_fastplus_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_fastplus_mode; + non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_plus_mode; } =20 /* make sure clock divisor programmed correctly */ @@ -1496,10 +1499,13 @@ static const struct tegra_i2c_hw_feature tegra20_i2= c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1521,10 +1527,13 @@ static const struct tegra_i2c_hw_feature tegra30_i2= c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1546,10 +1555,13 @@ static const struct tegra_i2c_hw_feature tegra114_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, }; @@ -1571,10 +1583,13 @@ static const struct tegra_i2c_hw_feature tegra124_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x0, - .setup_hold_time_fast_fast_plus_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, }; @@ -1596,10 +1611,13 @@ static const struct tegra_i2c_hw_feature tegra210_i= 2c_hw =3D { .has_apb_dma =3D true, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x2, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0, - .setup_hold_time_fast_fast_plus_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, }; @@ -1621,10 +1639,13 @@ static const struct tegra_i2c_hw_feature tegra186_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x4, .thigh_std_mode =3D 0x3, - .tlow_fast_fastplus_mode =3D 0x4, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0, - .setup_hold_time_fast_fast_plus_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, }; @@ -1646,10 +1667,13 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x8, .thigh_std_mode =3D 0x7, - .tlow_fast_fastplus_mode =3D 0x2, - .thigh_fast_fastplus_mode =3D 0x2, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x08080808, - .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, }; @@ -1671,10 +1695,13 @@ static const struct tegra_i2c_hw_feature tegra256_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x8, .thigh_std_mode =3D 0x7, - .tlow_fast_fastplus_mode =3D 0x3, - .thigh_fast_fastplus_mode =3D 0x3, + .tlow_fast_mode =3D 0x3, + .thigh_fast_mode =3D 0x3, + .tlow_fastplus_mode =3D 0x3, + .thigh_fastplus_mode =3D 0x3, .setup_hold_time_std_mode =3D 0x08080808, - .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, }; --=20 2.50.1 From nobody Sun Feb 8 01:31:10 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013015.outbound.protection.outlook.com [40.93.201.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9028311CBA; Sat, 15 Nov 2025 04:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:27:59.2714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16d76fcc-2387-4453-003f-08de23ff5ba2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7662 Content-Type: text/plain; charset="utf-8" Update the timing parameters of Tegra256 so that the signals are complaint with the I2C specification for SCL low time. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- drivers/i2c/busses/i2c-tegra.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c0382c9a0430..8a696c88882e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1677,14 +1677,13 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, }; - static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, .clk_divisor_hs_mode =3D 7, .clk_divisor_std_mode =3D 0x7a, .clk_divisor_fast_mode =3D 0x40, - .clk_divisor_fast_plus_mode =3D 0x19, + .clk_divisor_fast_plus_mode =3D 0x14, .has_config_load_reg =3D true, .has_multi_master_mode =3D true, .has_slcg_override_reg =3D true, @@ -1695,14 +1694,13 @@ static const struct tegra_i2c_hw_feature tegra256_i= 2c_hw =3D { .has_apb_dma =3D false, .tlow_std_mode =3D 0x8, .thigh_std_mode =3D 0x7, - .tlow_fast_mode =3D 0x3, - .thigh_fast_mode =3D 0x3, - .tlow_fastplus_mode =3D 0x3, - .thigh_fastplus_mode =3D 0x3, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x4, .setup_hold_time_std_mode =3D 0x08080808, - .setup_hold_time_fast_mode =3D 0x02020202, - .setup_hold_time_fastplus_mode =3D 0x02020202, - .setup_hold_time_hs_mode =3D 0x090909, + .setup_hold_time_fast_mode =3D 0x04010101, + .setup_hold_time_fastplus_mode =3D 0x04020202, .has_interface_timing_reg =3D true, }; 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Fri, 14 Nov 2025 20:27:53 -0800 From: Akhil R To: , , , , , , , , CC: , , , Subject: [PATCH v12 4/6] i2c: tegra: Add HS mode support Date: Sat, 15 Nov 2025 09:56:30 +0530 Message-ID: <20251115042632.69708-5-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251115042632.69708-1-akhilrajeev@nvidia.com> References: <20251115042632.69708-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB58:EE_|DS0PR12MB9324:EE_ X-MS-Office365-Filtering-Correlation-Id: 77d1f2f5-421b-4220-c0f7-08de23ff649c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EjpZ94ZDBVR+IpDDk04+K/aIFl/cg7ApOXGIESul5EROFnoQCQWs+hB+296D?= =?us-ascii?Q?xY3M0ekRqOQCwfIc26JIrmCbidSNEmCyKF5Xj3udBRE/JW401ZOtO+IV0wJL?= =?us-ascii?Q?gHVagTG/eyndyvbeAJiYMkUTg5tvCagjCQOW3yVTYRGA3W2Whk1e4KVJDtk2?= =?us-ascii?Q?8Ni3BptqT9/XfpXorEjRrwcmEmnq2D62cSqUa1lEX06c/pOztiZg0fOrxZdA?= =?us-ascii?Q?VKpKbeO2d1n4+hRYnQZDE/g/7VIlbCTXx39ohgSXHnIZR7C/Jr520Q/XJy5M?= =?us-ascii?Q?niRVk1O+HrSPaVjCZhs04QCAvQVqQVTErIHsbC8vwok3F5vONrCjJNZLObGW?= =?us-ascii?Q?SmQDyWRTwiLp/4IUGWOwyTHr3do3b3HB68MnM6owY2HZVo4aZ4pVpRYPLxA8?= =?us-ascii?Q?KoUZ+J2E3ljGDQb3L6Dg6PPDb43czyBvRQgS2e9Ks37+fBvLzm37SMlfFR4v?= =?us-ascii?Q?hjJG+YkVsz7by5wubAKYn/1/lwB11v6XIyH+V6Hf/3ASDdoivzt28wdtlxTS?= =?us-ascii?Q?YUAqYJJfN9i7BphwJX6jLGRz3cnn3cJgTQl8DEG8+jXZgefwrgt1/wLJ/eF3?= =?us-ascii?Q?CQPlyYox8w5rrCdYLxy4BYN5g0PTA0xBPeo1jiobCQ7UBMqyj9bm2i8TItYD?= =?us-ascii?Q?GB1NNmwZSktE8k4KA4zHAASzvE3725GpvV3Y5jsnYaqhwSwxybV/CEL/YV4j?= =?us-ascii?Q?K5wa/Nj2x+uCaUelbTSr/OPbHehuWsDnplM09c0Cg/I52GJpWKZ0ibXonnHu?= =?us-ascii?Q?3ysITUrHXrfw6qVo/82kqA9HDgw/JzM34mFkaz4/Sci/5kEpXP4rtdroBZBR?= =?us-ascii?Q?zKFZ0EQDToUNyr/5CBClfKN8z3r0GizAexDmdO9wfaMBdijyEy+9H4dF6tT2?= =?us-ascii?Q?Ebpez+yzl3MCM5l9bfgk5ASqlakK8Lu9/od4d47W76cgVacPeknGYRTux/rI?= =?us-ascii?Q?sTEB9XDb2CbrErDRXPZ81ZNFDUfy0dkYOkEmOd9RbeycFL04b5RCQSji79xf?= =?us-ascii?Q?jjq9xdfMrbx1Y40TQZJ/q6KSRcTPmC2w4HmjjzMWB7EVQ5HNohAL9FS0Cg5H?= =?us-ascii?Q?7lx6p+6TwBciS/Y1t+r7mt8M4cf9frbmHAXPsS8RxWQesJ87yWfyaV/8xHK5?= =?us-ascii?Q?mBbgs+pXJmS2oRo59w5bhRWlCnF0TI9Ac2jZc7Ta2pOKCTB/YlN8L+Vq8yq7?= =?us-ascii?Q?NVOP3twouiviqtG6cOo4/qtaaOXxVmiPjD0RF2LEXgdIDwBoxsB5MnL52mba?= =?us-ascii?Q?pHmUvBj/a1VrA/E32rXS/ffzxD8F1mv21cjd8q592c/zIw6IVRtAnZ6vbQMw?= =?us-ascii?Q?ahkyXc8Xn1+OR6yNTkjuBFHKsiAgTmFlVcxbqjutW4tL4SWGeTyDAth3SRzf?= =?us-ascii?Q?wj7dK9Hs69Ldp2AGzAteMDfKFb6KxLYn/h4hAL8NCFmw26VjWPfQguu1063L?= =?us-ascii?Q?PmAf/Yx22qWv2o7WZKlKF/NdD1iNi/qe7ug4b/7Z+R5pvCkfq55BTVgItxwx?= =?us-ascii?Q?N0x0Un3ZE1k4oh92hxnCWvy9Y8+gNLjZKBtcQpniBP6i7dabIJ2XYay1zYrt?= =?us-ascii?Q?Y2BC1S0TVa5YzumyuNoFSEJQOOSpF4RU2PxBCSvs?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:28:14.2816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77d1f2f5-421b-4220-c0f7-08de23ff649c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9324 Content-Type: text/plain; charset="utf-8" Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Also adjust the bus frequency such that it uses the fast plus mode when HS mode is not supported. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v10 -> v12: * Update bus_freq_hz to max supported freq and updates to accomodate the changes from Patch 2/6. v10 -> v11:=20 * Update the if condition as per the comments received on: https://lore.kernel.org/linux-tegra/20251110080502.865953-1-kkartik@nvid= ia.com/T/#t v9 -> v10: * Change switch block to an if-else block. v5 -> v9: * In the switch block, handle the case when hs mode is not supported. Also update it to use Fast mode for master code byte as per the I2C spec for HS mode. v3 -> v5: * Set has_hs_mode_support to false for unsupported SoCs. v2 -> v3: * Document tlow_hs_mode and thigh_hs_mode. v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 59 ++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 8a696c88882e..9ebeb6a2eaf5 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 =20 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -200,6 +201,8 @@ enum msg_end_type { * @thigh_fast_mode: High period of the clock in fast mode. * @tlow_fastplus_mode: Low period of the clock in fast-plus mode. * @thigh_fastplus_mode: High period of the clock in fast-plus mode. + * @tlow_hs_mode: Low period of the clock in HS mode. + * @thigh_hs_mode: High period of the clock in HS mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop condi= tions * in standard mode. * @setup_hold_time_fast_mode: Setup and hold time for start and stop @@ -210,6 +213,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -232,11 +236,14 @@ struct tegra_i2c_hw_feature { u32 thigh_fast_mode; u32 tlow_fastplus_mode; u32 thigh_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_mode; u32 setup_hold_time_fastplus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; =20 /** @@ -646,6 +653,7 @@ static int tegra_i2c_master_reset(struct tegra_i2c_dev = *i2c_dev) static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; + u32 max_bus_freq_hz; struct i2c_timings *t =3D &i2c_dev->timings; int err; =20 @@ -684,6 +692,14 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); =20 + if (i2c_dev->hw->has_hs_mode_support) + max_bus_freq_hz =3D I2C_MAX_HIGH_SPEED_MODE_FREQ; + else + max_bus_freq_hz =3D I2C_MAX_FAST_MODE_PLUS_FREQ; + + if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz)) + t->bus_freq_hz =3D max_bus_freq_hz; + if (t->bus_freq_hz <=3D I2C_MAX_STANDARD_MODE_FREQ) { tlow =3D i2c_dev->hw->tlow_std_mode; thigh =3D i2c_dev->hw->thigh_std_mode; @@ -694,11 +710,22 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_d= ev) thigh =3D i2c_dev->hw->thigh_fast_mode; tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_mode; non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; - } else { + } else if (t->bus_freq_hz <=3D I2C_MAX_FAST_MODE_PLUS_FREQ) { tlow =3D i2c_dev->hw->tlow_fastplus_mode; thigh =3D i2c_dev->hw->thigh_fastplus_mode; tsu_thd =3D i2c_dev->hw->setup_hold_time_fastplus_mode; non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_plus_mode; + } else { + /* + * When using HS mode, i.e. when the bus frequency is greater than fast = plus mode, + * the non-hs timing registers will be used for sending the master code = byte for + * transition to HS mode. Configure the non-hs timing registers for Fast= Mode to + * send the master code byte at 400kHz. + */ + tlow =3D i2c_dev->hw->tlow_fast_mode; + thigh =3D i2c_dev->hw->thigh_fast_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_fast_mode; + non_hs_mode =3D i2c_dev->hw->clk_divisor_fast_mode; } =20 /* make sure clock divisor programmed correctly */ @@ -720,6 +747,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); =20 + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow =3D i2c_dev->hw->tlow_hs_mode; + thigh =3D i2c_dev->hw->thigh_hs_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_hs_mode; + + val =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } + clk_multiplier =3D (tlow + thigh + 2) * (non_hs_mode + 1); =20 err =3D clk_set_rate(i2c_dev->div_clk, @@ -1217,6 +1256,9 @@ static void tegra_i2c_push_packet_header(struct tegra= _i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |=3D I2C_HEADER_READ; =20 + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |=3D I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else @@ -1508,6 +1550,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1536,6 +1579,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1564,6 +1608,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1592,6 +1637,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_fastplus_mode =3D 0x0, .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1620,6 +1666,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1648,6 +1695,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_fastplus_mode =3D 0, .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1671,16 +1719,19 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .thigh_fast_mode =3D 0x2, .tlow_fastplus_mode =3D 0x2, .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x3, .setup_hold_time_std_mode =3D 0x08080808, .setup_hold_time_fast_mode =3D 0x02020202, .setup_hold_time_fastplus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, }; static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, - .clk_divisor_hs_mode =3D 7, + .clk_divisor_hs_mode =3D 9, .clk_divisor_std_mode =3D 0x7a, .clk_divisor_fast_mode =3D 0x40, .clk_divisor_fast_plus_mode =3D 0x14, @@ -1698,10 +1749,14 @@ static const struct tegra_i2c_hw_feature tegra256_i= 2c_hw =3D { .thigh_fast_mode =3D 0x2, .tlow_fastplus_mode =3D 0x4, .thigh_fastplus_mode =3D 0x4, + .tlow_hs_mode =3D 0x3, + .thigh_hs_mode =3D 0x2, .setup_hold_time_std_mode =3D 0x08080808, .setup_hold_time_fast_mode =3D 0x04010101, .setup_hold_time_fastplus_mode =3D 0x04020202, + .setup_hold_time_hs_mode =3D 0x030303, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, }; 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Fri, 14 Nov 2025 20:28:06 -0800 From: Akhil R To: , , , , , , , , CC: , , , Subject: [PATCH v12 5/6] i2c: tegra: Add support for SW mutex register Date: Sat, 15 Nov 2025 09:56:31 +0530 Message-ID: <20251115042632.69708-6-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251115042632.69708-1-akhilrajeev@nvidia.com> References: <20251115042632.69708-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B5:EE_|PH7PR12MB7456:EE_ X-MS-Office365-Filtering-Correlation-Id: a9077aec-752a-4d4d-fabd-08de23ff66d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Lku5Cw3ExvlSWFHoycZAkgB8RoUvoMbWxDKQcLLJidq9fjJS3jqqHdZClaUF?= =?us-ascii?Q?2SgUKRbhMvkgY3rIusUNYjP53Ht5y5ZKXA330Ch/BQKeFEPN1+52mfU0BsBd?= =?us-ascii?Q?C4gYWCcAv8snw+AgucuxV7qEGyd05Uw1WDkBaUvttXosXEuIWDFPV20FINdN?= =?us-ascii?Q?jZmP9dBDUtRFqAcNKeIXyA0vSxBoCHHfm6397CNCCVrOWVU8k8UtBW9bOtac?= =?us-ascii?Q?2k+JsgeUK6zBhOHvmxQKtLudRe3Tvn4j9CsxOCaRz0rWQNLiTGzbsGMhZAnj?= =?us-ascii?Q?cfCrbrlDiER5J7TkFgAb7iD307+CX3ofvKMkB/z8wPEuyGiTON+AO4AX9vXj?= =?us-ascii?Q?k5sSoIOABFUjUovrSRKhiwI3cBj10Pf/CLOGWfvk/tIobLgwTPaIS208H6b2?= =?us-ascii?Q?oGvfgGNs8Ldt8AYU7bf5QdeKEip2bBgfHiOzHu8PuNZujn0qogEjR5AF9TY8?= =?us-ascii?Q?/es4IFzSOkzyh9TI7t6z3Pqgly0o9Z5Wk0Rs7ODQukPU82fgeNQSb/o4VE4Z?= =?us-ascii?Q?sfmM0VYqqYbpt+rOWTiS6LrpGIbNOkvFJAxitE92Oe/sAvXl9oUjCKp5Y4EG?= =?us-ascii?Q?5bko8cqEms9JJHDZeoZMnU47v463YC7LPKQUy5S47REyNs6jHUFM/j4eWiV/?= =?us-ascii?Q?51ZWWTEr1rs/Dz/32VZSkgyx9H0HqfsxUC6rZeRRR+KJksXXq9996AZjl4wr?= =?us-ascii?Q?JYSidL8f9u4OV6fQvBarcPHgmacVxja/xCC2r0jLKg1ifuPkOfzKM7SO8gt9?= =?us-ascii?Q?iNQ3NZ0XFbGfAik/SCAel5LSsrpsJMmAPbO0W+RXYdGBL5ot5uvwVTdlNuL/?= =?us-ascii?Q?v5avTjsLtkYenBlRZetUNFxOoDQY7s3Nl0cbCxLQJgQDymO5EIcx12VN7MLU?= =?us-ascii?Q?V7XDeH+4NWDJfLQvDPvDQzvxE3VNbfxC7jgGLLXE+RKXOiGX6homoGcqsUwM?= =?us-ascii?Q?4DNt5oW8htpMgy7QoAa1WKbEjH+shg2ERSlahMIfpHkD0IPAt9D4VZG9YC4n?= =?us-ascii?Q?KVJAyqGuBCpT58rIZsgcKJcAX27THiXzC8OtLbyUguvf+nifPZJoGe0+K1le?= =?us-ascii?Q?b5sXppKxHiPU17jPTtGfEv/rqmqtzipiT8mMNNQJRxscaZymeymYPqkr07sc?= =?us-ascii?Q?MlwaKExQrLj1A9Vn5HblhHIiakk0CLt7OfwYdtgFYweBnWBPBb24cvZgyMpw?= =?us-ascii?Q?PNsGlpA+b0aP9tCA+B4U51vly/rqyHNNb3/W2/BTJMUma7uxHPiE/SGpfSnD?= =?us-ascii?Q?s/y3AW1pijy54q7/QdSjt7HPKdaPxLspONk7Oox+FSRhlJSlfNx6v6VwsFa1?= =?us-ascii?Q?x2nwLZYiQ9Blp2CYvsJviqMpP2V1epT0nQwcvltRi6SqfHn2TQ0fkkRnlsHg?= =?us-ascii?Q?wybGU7gFcwjq1HvH9CLtkSwiRT7/oRVWxZG5sJvknQQ54tXMOO5/JMECKxnx?= =?us-ascii?Q?HKtxUJWAN/ibUY+y2lBB/H3ucCOK9nokov8+MfsahomoD/RKB3A6aP/X3R9f?= =?us-ascii?Q?mLmgqkV0cDSXmO4//c3OXJ8kNALPud4BoVlSXNyCpyIF4q4kGftvs+UkoVQ+?= =?us-ascii?Q?wnjYVUTjrXK64MPf5tk=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:28:18.0223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9077aec-752a-4d4d-fabd-08de23ff66d0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7456 Content-Type: text/plain; charset="utf-8" From: Kartik Rajput Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. This involves following steps: - A firmware/OS writes its unique ID to the mutex REQUEST field. - Ownership is established when reading the GRANT field returns the same ID. - If GRANT shows a different non-zero ID, the firmware/OS retries until timeout. - After completing access, it releases the mutex by writing 0. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Kartik Rajput Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- v7 -> v8: * Use `bool` instead of `int` for `locked` variable in tegra_i2c_mutex_lock() function. v6 -> v7: * Return bool from tegra_i2c_mutex_acquired() and tegra_i2c_mutex_trylock() functions. * Move `has_mutex` check inside tegra_i2c_mutex_lock/unlock functions. * Remove redundant empty line added in tegra_i2c_xfer() in v6. * Fix pm_runtime_put() not getting called if mutex unlock fails. * In tegra_i2c_mutex_lock() simplify the logic to check if the mutex is acquired or not by checking the value of `ret` variable. * Update commit message to describe the functioning of SW mutex feature. v4 -> v6: * Guard tegra_i2c_mutex_lock() and tegra_i2c_mutex_unlock() to ensure that they are called on platforms which support SW mutex. v3 -> v4: * Update timeout logic of tegra_i2c_mutex_lock() to use read_poll_timeout APIs for improving timeout logic. * Add tegra_i2c_mutex_acquired() to check if mutex is acquired or not. * Rename I2C_SW_MUTEX_ID as I2C_SW_MUTEX_ID_CCPLEX. * Function tegra_i2c_poll_register() was moved unnecessarily, it has now been moved to its original location. * Use tegra_i2c_mutex_lock/unlock APIs in the tegra_i2c_xfer() function. This ensures proper propagation of error in case mutex lock fails. Please note that as the function tegra_i2c_xfer() is already guarded by the bus lock operation there is no need of additional lock for the tegra_i2c_mutex_lock/unlock APIs. v2 -> v3: * Update tegra_i2c_mutex_trylock and tegra_i2c_mutex_unlock to use readl and writel APIs instead of i2c_readl and i2c_writel which use relaxed APIs. * Use dev_warn instead of WARN_ON if mutex lock/unlock fails. v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 93 ++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9ebeb6a2eaf5..135883388c1e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -137,6 +137,14 @@ =20 #define I2C_MASTER_RESET_CNTRL 0x0a8 =20 +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID_CCPLEX 9 + +/* SW mutex acquire timeout value in microseconds. */ +#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 =20 @@ -214,6 +222,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -244,6 +253,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; =20 /** @@ -388,6 +398,76 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, = void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } =20 +static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + return id =3D=3D I2C_SW_MUTEX_ID_CCPLEX; +} + +static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + val =3D readl(i2c_dev->base + reg); + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id !=3D 0 && id !=3D I2C_SW_MUTEX_ID_CCPLEX) + return false; + + val =3D FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); + writel(val, i2c_dev->base + reg); + + return tegra_i2c_mutex_acquired(i2c_dev); +} + +static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + bool locked; + int ret; + + if (!i2c_dev->hw->has_mutex) + return 0; + + if (i2c_dev->atomic_mode) + ret =3D read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, + false, i2c_dev); + else + ret =3D read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_= PER_MSEC, + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); + + if (ret) + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); + + return ret; +} + +static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + u32 val, id; + + if (!i2c_dev->hw->has_mutex) + return 0; + + val =3D readl(i2c_dev->base + reg); + + id =3D FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id && id !=3D I2C_SW_MUTEX_ID_CCPLEX) { + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n"= , id); + return -EPERM; + } + + writel(0, i2c_dev->base + reg); + + return 0; +} + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -1443,6 +1523,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, = struct i2c_msg msgs[], return ret; } =20 + ret =3D tegra_i2c_mutex_lock(i2c_dev); + if (ret) + return ret; + for (i =3D 0; i < num; i++) { enum msg_end_type end_type =3D MSG_END_STOP; =20 @@ -1472,6 +1556,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, s= truct i2c_msg msgs[], break; } =20 + ret =3D tegra_i2c_mutex_unlock(i2c_dev); pm_runtime_put(i2c_dev->dev); =20 return ret ?: i; @@ -1551,6 +1636,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { @@ -1580,6 +1666,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1609,6 +1696,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D false, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1638,6 +1726,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0x0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1667,6 +1756,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { @@ -1696,6 +1786,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .setup_hold_time_hs_mode =3D 0, .has_interface_timing_reg =3D true, .has_hs_mode_support =3D false, + .has_mutex =3D false, }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2025 04:28:22.8027 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 722c0354-c346-4e74-7c97-08de23ff69b0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8196 Content-Type: text/plain; charset="utf-8" Add support for Tegra264 SoC which supports 17 generic I2C controllers, two of which are in the AON (always-on) partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter --- v4 -> v10: * Set has_mst_reset =3D true for Tegra264. v1 -> v4: * Update commit message to mention the SW mutex feature available on Tegra264. --- drivers/i2c/busses/i2c-tegra.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 135883388c1e..919ef408f3c1 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1852,7 +1852,40 @@ static const struct tegra_i2c_hw_feature tegra256_i2= c_hw =3D { .has_mutex =3D true, }; =20 +static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x1d, + .clk_divisor_fast_mode =3D 0x15, + .clk_divisor_fast_plus_mode =3D 0x8, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .has_mst_reset =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x4, + .thigh_hs_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x090909, + .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, + .has_mutex =3D true, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { + { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra256-i2c", .data =3D &tegra256_i2c_hw, }, { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, --=20 2.50.1