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De Francesco" , Terry Bowman , Joshua Hahn , Robert Richter Subject: [PATCH v7 04/11] cxl: Simplify cxl_root_ops allocation and handling Date: Fri, 14 Nov 2025 22:39:17 +0100 Message-ID: <20251114213931.30754-5-rrichter@amd.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251114213931.30754-1-rrichter@amd.com> References: <20251114213931.30754-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|CH1PPF189669351:EE_ X-MS-Office365-Filtering-Correlation-Id: 18519ffd-b7a7-4a40-8df5-08de23c65d08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QMfCHvxWz2inUy2G6PIgURdo0nnZc+DCYxLR4FVa+sfj1N501D6HiNYpbGgj?= =?us-ascii?Q?2qE9N/FHIk3xAUO+4awUbTs9RuqReald3DL6Nfr4ZCfcIKTNfaQlwscV6WtT?= =?us-ascii?Q?D+pw+pqZ9ReBQL6/5gJm0fuGVPl4s+oNwutNlMtJUDZxrIRhOo7SAzAUImo7?= =?us-ascii?Q?jix6BNk9TiQJg4lFvzwGYEWbc3Tnx6bnFSnWXgbsyApgGDcMjMPXpDU0ATso?= =?us-ascii?Q?HGyCLaW5KBuBIBsGQycjwyZu641SxaFqHsyBKZMFoj3crsS6pflqgrxQJBcA?= =?us-ascii?Q?Ywvi+2HRQKYMLO+LiIsSF2Ffn9OnJDuGn0g7qHBDszs4GY25bU1KbKk64Jot?= =?us-ascii?Q?FJrlhGUsIHQczk3dvuMeq/AHZGudeMnuWyuTipzaIk+2NtIZlBaueuTTZwRr?= =?us-ascii?Q?VEjVdxKS5rq0Z+P5Ork5V5wCX7K+Ms/mwvzf/58RrKZIDlTkGvvFLCBL22Ax?= =?us-ascii?Q?b/DAZAcg7fWar491BN7LPk7NJchSsXqdY+7/oo4ZnfdI7dYWt5gJJu6MJFA9?= =?us-ascii?Q?kRR/NEUcwKlMgzqA70nu33TOz9UnnAgX1ecnjBUdOVtb+ZXOvbsrUNnPJMIs?= =?us-ascii?Q?8J+WhZLsDBVgwParLwQYrKJZYe6OcMoJHRRsngRDx3x9gg6M+DTlADguRcgU?= =?us-ascii?Q?8AyQo7ztkUcv+LzmotbseVO9WhAf6JRNJ9hHiYGts6C2Wdelo1QNtIY+HP2Y?= =?us-ascii?Q?Bv/5gIcCa7SfELlRCENtlWqhEvNR3D5xJRT+NCVF4Y1a7ebuzUB7Nv26b753?= =?us-ascii?Q?T452m16YsKsd5eWFw9HjmVsQu0lF8dHQmE5hyNg7MaN06sHxx58PntivKudd?= =?us-ascii?Q?H9qPZ0mNrcaUYGZWaFRS7jt+yE+NuyBdEf99u0nCNG+WkYgcj7H8qcPVrotf?= =?us-ascii?Q?nQvPNVXa0LkEMLk/2Ouklh4SexSIxQLh7IhPZIl5RKYd1s08a3RQcnDVA/wj?= =?us-ascii?Q?sKAj+lJ+VUblsuEs2v8lLv+ld39AHU0jtpbLNPV7wSm2Mu/qzNvUNgd96/EQ?= =?us-ascii?Q?NQA9qcRG6FFqN/mOU8MwBnYmnMn/roHy4Z3TJ7G+MRBjrdxa3fXeGibxOoFd?= =?us-ascii?Q?6N89/MhT/K+v1Oe9kO7rvwycgE/SPHLKX80rakB1iX/FTHeCYesjZtCIFqKd?= =?us-ascii?Q?DBam0+iR/MC2mryvVV5jdacT5RFmJVzEJZxXibzNSVVgpm8+dErPhvhpc9AJ?= =?us-ascii?Q?mbcwmC4Lg2s18egGadPC6kUnEUFgVGid41OKoZbXiJoz2c1sIg1/7xbKK0iw?= =?us-ascii?Q?N0D9TGb5pM0J8IS8rvwVUmzARTxKb41x43ypGiZmidteJaHfSaRvypqIzxN9?= =?us-ascii?Q?KI+tXhNNjM8Ip1YYH/DErTJE+MWZuhD1e/IJ+iCpfj5Rp0ngHuG0UYOZby5y?= =?us-ascii?Q?xnZ7R1RKOZ+s5Yg5NMunf271Vb76l30sQmkCJWKA8YNCDsI/vEn+nyInAQo7?= =?us-ascii?Q?DB9H/AB+WJDho/HTKwnQ8mqw8mdvmUBR9pRSXUyYjENM7zbymp1CH9Rgkbs8?= =?us-ascii?Q?0JriS4l+N15mxFsuaEDE4stnmNanVYxDqtia7pRERIgSLVxLSmUevFrcveNN?= =?us-ascii?Q?ikwsZzMoDShLp1C4L+4=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 21:40:00.3979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18519ffd-b7a7-4a40-8df5-08de23c65d08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF189669351 Content-Type: text/plain; charset="utf-8" A root port's callback handlers are collected in struct cxl_root_ops. The structure is dynamically allocated, though it contains only a single pointer in it. This also requires to check two pointers to check for the existance of a callback. Simplify the allocation, release and handler check by embedding the ops statically in struct cxl_root. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 7 ++----- drivers/cxl/core/cdat.c | 8 ++++---- drivers/cxl/core/port.c | 8 ++------ drivers/cxl/cxl.h | 19 ++++++++++--------- 4 files changed, 18 insertions(+), 24 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 0a1bad3cafa7..866813e1b729 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -299,10 +299,6 @@ static int cxl_acpi_qos_class(struct cxl_root *cxl_roo= t, return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class); } =20 -static const struct cxl_root_ops acpi_root_ops =3D { - .qos_class =3D cxl_acpi_qos_class, -}; - static void del_cxl_resource(struct resource *res) { if (!res) @@ -907,9 +903,10 @@ static int cxl_acpi_probe(struct platform_device *pdev) cxl_res->end =3D -1; cxl_res->flags =3D IORESOURCE_MEM; =20 - cxl_root =3D devm_cxl_add_root(host, &acpi_root_ops); + cxl_root =3D devm_cxl_add_root(host); if (IS_ERR(cxl_root)) return PTR_ERR(cxl_root); + cxl_root->ops.qos_class =3D cxl_acpi_qos_class; root_port =3D &cxl_root->port; =20 rc =3D bus_for_each_dev(adev->dev.bus, NULL, root_port, diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index c4bd6e8a0cf0..b84a9b52942c 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -213,7 +213,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port= *port, if (!cxl_root) return -ENODEV; =20 - if (!cxl_root->ops || !cxl_root->ops->qos_class) + if (!cxl_root->ops.qos_class) return -EOPNOTSUPP; =20 xa_for_each(dsmas_xa, index, dent) { @@ -221,9 +221,9 @@ static int cxl_port_perf_data_calculate(struct cxl_port= *port, =20 cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c); dent->entries =3D 1; - rc =3D cxl_root->ops->qos_class(cxl_root, - &dent->coord[ACCESS_COORDINATE_CPU], - 1, &qos_class); + rc =3D cxl_root->ops.qos_class(cxl_root, + &dent->coord[ACCESS_COORDINATE_CPU], + 1, &qos_class); if (rc !=3D 1) continue; =20 diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index fef3aa0c6680..2338d146577c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -954,19 +954,15 @@ struct cxl_port *devm_cxl_add_port(struct device *hos= t, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, "CXL"); =20 -struct cxl_root *devm_cxl_add_root(struct device *host, - const struct cxl_root_ops *ops) +struct cxl_root *devm_cxl_add_root(struct device *host) { - struct cxl_root *cxl_root; struct cxl_port *port; =20 port =3D devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); if (IS_ERR(port)) return ERR_CAST(port); =20 - cxl_root =3D to_cxl_root(port); - cxl_root->ops =3D ops; - return cxl_root; + return to_cxl_root(port); } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, "CXL"); =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4633004fb770..8945dc1532a7 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -638,6 +638,14 @@ struct cxl_port { resource_size_t component_reg_phys; }; =20 +struct cxl_root; + +struct cxl_root_ops { + int (*qos_class)(struct cxl_root *cxl_root, + struct access_coordinate *coord, int entries, + int *qos_class); +}; + /** * struct cxl_root - logical collection of root cxl_port items * @@ -646,7 +654,7 @@ struct cxl_port { */ struct cxl_root { struct cxl_port port; - const struct cxl_root_ops *ops; + struct cxl_root_ops ops; }; =20 static inline struct cxl_root * @@ -655,12 +663,6 @@ to_cxl_root(const struct cxl_port *port) return container_of(port, struct cxl_root, port); } =20 -struct cxl_root_ops { - int (*qos_class)(struct cxl_root *cxl_root, - struct access_coordinate *coord, int entries, - int *qos_class); -}; - static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_de= v) { @@ -755,8 +757,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); -struct cxl_root *devm_cxl_add_root(struct device *host, - const struct cxl_root_ops *ops); +struct cxl_root *devm_cxl_add_root(struct device *host); struct cxl_root *find_cxl_root(struct cxl_port *port); =20 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.= dev)) --=20 2.47.3