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Fri, 14 Nov 2025 06:57:19 -0800 (PST) Received: from hu-rdwivedi-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c244e13sm57548015ad.29.2025.11.14.06.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 06:57:19 -0800 (PST) From: Ram Kumar Dwivedi To: mani@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, ram.dwivedi@oss.qualcomm.com, quic_ahari@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V1 2/3] dt-bindings: ufs: Document bindings for SA8255P UFS Host Controller Date: Fri, 14 Nov 2025 20:26:45 +0530 Message-Id: <20251114145646.2291324-3-ram.dwivedi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251114145646.2291324-1-ram.dwivedi@oss.qualcomm.com> References: <20251114145646.2291324-1-ram.dwivedi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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The platform firmware implements the SCMI server and manages resources such as the PHY, clocks, regulators and resets via the SCMI power protocol. As a result, the OS-visible DT only describes the controller=E2=80=99s MMIO, interrupt, IOMMU and power-domain interfaces. The generic "qcom,ufshc" and "jedec,ufs-2.0" compatible strings are removed from the binding, since this firmware managed design won't be compatible with the drivers doing full resource management. Co-developed-by: Anjana Hari Signed-off-by: Anjana Hari Signed-off-by: Ram Kumar Dwivedi --- .../bindings/ufs/qcom,sa8255p-ufshc.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufsh= c.yaml diff --git a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml = b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml new file mode 100644 index 000000000000..3b31f6282feb --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sa8255p-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255P UFS Host Controller + +maintainers: + - Ram Kumar Dwivedi + - Anjana Hari + +properties: + compatible: + const: qcom,sa8255p-ufshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: + type: boolean + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - power-domains + - iommus + - dma-coherent + +allOf: + - $ref: ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ufshc@1d84000 { + compatible =3D "qcom,sa8255p-ufshc"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + interrupts =3D ; + lanes-per-direction =3D <2>; + + iommus =3D <&apps_smmu 0x100 0x0>; + power-domains =3D <&scmi3_pd 0>; + dma-coherent; + }; + }; --=20 2.34.1